// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
 */

/dts-v1/;

#include "stm32mp157c.dtsi"
#include "stm32mp157caa-pinctrl.dtsi"

/ {
	model = "STMicroelectronics STM32MP157C-ED1 pmic eval daughter";
	compatible = "st,stm32mp157c-ed1", "st,stm32mp157";

	chosen {
		bootargs = "earlyprintk console=ttyS3,115200 root=/dev/ram";
		stdout-path = "serial3:115200n8";
	};
};

&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_pins_a>;
	i2c-scl-rising-time-ns = <185>;
	i2c-scl-falling-time-ns = <20>;
	status = "okay";

	pmic: stpmu1@33 {
		compatible = "st,stpmu1";
		reg = <0x33>;
		status = "okay";

		st,main_control_register = <0x04>;
		st,vin_control_register = <0xc0>;
		st,usb_control_register = <0x30>;

		regulators {
			compatible = "st,stpmu1-regulators";

			v3v3: buck4 {
				regulator-name = "v3v3";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-over-current-protection;
				regulator-initial-mode = <8>;

				regulator-state-standby {
					regulator-suspend-microvolt = <3300000>;
					regulator-unchanged-in-suspend;
					regulator-mode = <8>;
				};
				regulator-state-mem {
					regulator-off-in-suspend;
				};
				regulator-state-disk {
					regulator-off-in-suspend;
				};
			};

			vdd_sd: ldo5 {
				regulator-name = "vdd_sd";
				regulator-min-microvolt = <2900000>;
				regulator-max-microvolt = <2900000>;
				regulator-boot-on;

				regulator-state-standby {
					regulator-suspend-microvolt = <2900000>;
					regulator-unchanged-in-suspend;
				};
				regulator-state-mem {
					regulator-off-in-suspend;
				};
				regulator-state-disk {
					regulator-off-in-suspend;
				};
			};
		};
	};
};

&iwdg2 {
	instance = <2>;
	timeout-sec = <32>;
	status = "okay";
};

&rng1 {
	status = "okay";
};

&sdmmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
	broken-cd;
	st,dirpol;
	st,negedge;
	st,pin-ckin;
	bus-width = <4>;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-ddr50;
	sd-uhs-sdr104;
	status = "okay";
};

&sdmmc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
	non-removable;
	no-sd;
	no-sdio;
	st,dirpol;
	st,negedge;
	bus-width = <8>;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart4_pins_a>;
	resets = <&rcc UART4_R>;
	status = "okay";
};

/* ATF Specific */
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"

/ {
	aliases {
		gpio0 = &gpioa;
		gpio1 = &gpiob;
		gpio2 = &gpioc;
		gpio3 = &gpiod;
		gpio4 = &gpioe;
		gpio5 = &gpiof;
		gpio6 = &gpiog;
		gpio7 = &gpioh;
		gpio8 = &gpioi;
		gpio9 = &gpioj;
		gpio10 = &gpiok;
		gpio25 = &gpioz;
		i2c3 = &i2c4;
	};

	soc {
		stgen: stgen@5C008000 {
			compatible = "st,stm32-stgen";
			reg = <0x5C008000 0x1000>;
			status = "okay";
		};
	};
};

/* CLOCK init */
&rcc {
	st,clksrc = <
		CLK_MPU_PLL1P
		CLK_AXI_PLL2P
		CLK_PLL12_HSE
		CLK_PLL3_HSE
		CLK_PLL4_HSE
		CLK_RTC_LSE
		CLK_MCO1_DISABLED
		CLK_MCO2_DISABLED
	>;

	st,clkdiv = <
		1 /*MPU*/
		0 /*AXI*/
		1 /*APB1*/
		1 /*APB2*/
		1 /*APB3*/
		1 /*APB4*/
		2 /*APB5*/
		23 /*RTC*/
		0 /*MCO1*/
		0 /*MCO2*/
	>;

	st,pkcs = <
		CLK_CKPER_HSE
		CLK_FMC_ACLK
		CLK_QSPI_ACLK
		CLK_ETH_DISABLED
		CLK_SDMMC12_PLL3R
		CLK_DSI_DSIPLL
		CLK_STGEN_HSE
		CLK_USBPHY_HSE
		CLK_SPI2S1_PLL3Q
		CLK_SPI2S23_PLL3Q
		CLK_SPI45_HSI
		CLK_SPI6_HSI
		CLK_I2C46_HSI
		CLK_SDMMC3_PLL3R
		CLK_USBO_USBPHY
		CLK_ADC_CKPER
		CLK_CEC_LSE
		CLK_I2C12_HSI
		CLK_I2C35_HSI
		CLK_UART1_HSI
		CLK_UART24_HSI
		CLK_UART35_HSI
		CLK_UART6_HSI
		CLK_UART78_HSI
		CLK_SPDIF_PLL3Q
		CLK_FDCAN_PLL4Q
		CLK_SAI1_PLL3Q
		CLK_SAI2_PLL3Q
		CLK_SAI3_PLL3Q
		CLK_SAI4_PLL3Q
		CLK_RNG1_CSI
		CLK_RNG2_CSI
		CLK_LPTIM1_PCLK1
		CLK_LPTIM23_PCLK3
		CLK_LPTIM45_PCLK3
	>;

	/* VCO = 1300.0 MHz => P = 650 (CPU) */
	pll1: st,pll@0 {
		cfg = < 2 80 0 0 0 PQR(1,0,0) >;
		frac = < 0x800 >;
	};

	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
	pll2: st,pll@1 {
		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
		frac = < 0x1400 >;
	};

	/* VCO = 786.4 MHz => P = 197, Q = 49, R = 98 */
	pll3: st,pll@2 {
		cfg = < 2 97 3 15 7 PQR(1,1,1) >;
		frac = < 0x9ba >;
	};

	/* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */
	pll4: st,pll@3 {
		cfg = < 5 126 8 8 8 PQR(1,1,1) >;
	};
};

/delete-node/ &clk_csi;
