GitBucket
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Rationalize UART usage among different BL stages
This patch changes the UART port assignment for various BL stages so as to make it consistent on the platform ports. The BL1, BL2 and BL3-1 now uses UART0 on the FVP port and SoC UART0 on the Juno port. The BL3-2 uses UART2 on the FVP port and FPGA UART0 on the Juno port. This provides an interim fix to ARM-software/tf-issues#220 until support is added for changing the UART port for a BL image between cold boot and runtime. Change-Id: Iae5faea90be3d59e41e597b34a902f93e737505a
WIP_v2.3-LS
master
v2.2-LS
v2.4-LS
v2.3-rc2
v2.3-rc1
v2.3-rc0
v2.3
v2.2-rc2
v2.2-rc1
v2.2-rc0
v2.2
v2.1-rc1
v2.1-rc0
v2.1
v2.0-rc0
v2.0
v1.6-rc1
v1.6-rc0
v1.6
v1.5-rc3
v1.5-rc2
v1.5-rc1
v1.5-rc0
v1.5
v1.4-rc0
v1.4
v1.3_rc2
v1.3_rc1
v1.3-rc0
v1.3
v1.2-rc0
v1.2
v1.1-rc3
v1.1-rc2
v1.1-rc1
v1.1-rc0
v1.1-Juno-0.1
v1.1
v1.0-rc0
v1.0
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| plat/fvp/tsp/tsp_fvp_setup.c |
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| plat/juno/bl1_plat_setup.c |
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| plat/juno/bl2_plat_setup.c |
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| plat/juno/bl31_plat_setup.c |
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| plat/juno/juno_def.h |
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| plat/juno/tsp/tsp_plat_setup.c |
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