Merge "intel: agilex: Clear PLL lostlock bypass mode" into integration
commit 3441952f61a62948ccf84c2e3eada9b340c3560d
2 parents de58048 + 960a12b
@Paul Beesley Paul Beesley authored on 28 Aug 2019
TrustedFirmware Code Review committed on 28 Aug 2019
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plat/intel/soc/agilex/include/agilex_clock_manager.h
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plat/intel/soc/agilex/soc/agilex_clock_manager.c