bl1-smc-handler: Ensure the lower-order 16 bits of SPSR are programmed
A bug recently fixed in bl2/aarch32/bl2_el3_entrypoint.S relates to
programming the lower-order 16 bits of the SPSR to populate into the CPSR
on eret.

The BL1 smc-handler code is identical and has the same shortfall in
programming the SPSR from the platform defined struct

msr spsr, r1 will only update bits f->[31:24] and c->[7:0] respectively. In
order to ensure the 16 lower-order processor mode bits x->[15:8] and
c->[7:0] this patch changes msr spsr, r1 to msr spsr_xc, r1.

This change ensures we capture the x field, which we are interested in and
not the f field which we are not.

Fixes: f3b4914be3b4 ('AArch32: Add generic changes in BL1')

Signed-off-by: Bryan O'Donoghue <>
1 parent eb20f04 commit 520f864e66f7e1253b294923196741536af41726
@Bryan O'Donoghue Bryan O'Donoghue authored on 12 Mar 2019
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