Add support for asynchronous FIQ handling in TSP
This patch adds support in the TSP to handle FIQ interrupts that are generated when execution is in the TSP. S-EL1 interrupt are handled normally and execution resumes at the instruction where the exception was originally taken. S-EL3 interrupts i.e. any interrupt not recognized by the TSP are handed to the TSPD. Execution resumes normally once such an interrupt has been handled at EL3. Change-Id: Ia3ada9a4fb15670afcc12538a6456f21efe58a8f
WIP_v2.3-LS
master
v2.2-LS
v2.4-LS
v2.3-rc2
v2.3-rc1
v2.3-rc0
v2.3
v2.2-rc2
v2.2-rc1
v2.2-rc0
v2.2
v2.1-rc1
v2.1-rc0
v2.1
v2.0-rc0
v2.0
v1.6-rc1
v1.6-rc0
v1.6
v1.5-rc3
v1.5-rc2
v1.5-rc1
v1.5-rc0
v1.5
v1.4-rc0
v1.4
v1.3_rc2
v1.3_rc1
v1.3-rc0
v1.3
v1.2-rc0
v1.2
v1.1-rc3
v1.1-rc2
v1.1-rc1
v1.1-rc0
v1.1-Juno-0.1
v1.1
v1.0-rc0
v1.0
v0.4-rc2
v0.4-rc1
v0.4-Juno-0.6-rc1
v0.4-Juno-0.6-rc0
v0.4-Juno-0.5-rc1
v0.4-Juno-0.5-rc0
v0.4-Juno-0.5
v0.4-Juno-0.4-rc0
v0.4-Juno-0.4
v0.4
for-v0.4-rc0
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bl32/tsp/aarch64/tsp_entrypoint.S |
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bl32/tsp/aarch64/tsp_exceptions.S 0 → 100644 |
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bl32/tsp/tsp.mk |
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