Add support for asynchronous FIQ handling in TSP
This patch adds support in the TSP to handle FIQ interrupts that are
generated when execution is in the TSP. S-EL1 interrupt are handled
normally and execution resumes at the instruction where the exception
was originally taken. S-EL3 interrupts i.e. any interrupt not
recognized by the TSP are handed to the TSPD. Execution resumes
normally once such an interrupt has been handled at EL3.

Change-Id: Ia3ada9a4fb15670afcc12538a6456f21efe58a8f
1 parent 1ad9e8f commit 757d591168a4de8f6507b79e62e9129849243e8e
@Achin Gupta Achin Gupta authored on 9 May 2014
Showing 3 changed files
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bl32/tsp/aarch64/tsp_entrypoint.S
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bl32/tsp/aarch64/tsp_exceptions.S 0 → 100644
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bl32/tsp/tsp.mk