Neoverse N1 Errata Workaround 1542419
Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6 |
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bl31/aarch64/ea_delegate.S |
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docs/design/cpu-specific-build-macros.rst |
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include/lib/cpus/aarch64/cpu_macros.S |
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include/lib/cpus/aarch64/neoverse_n1.h |
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lib/cpus/aarch64/cpu_helpers.S |
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lib/cpus/aarch64/neoverse_n1.S |
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lib/cpus/cpu-ops.mk |
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