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History for arm-trusted-firmware / fdts

2020-07-31	03a5225 Browse files » tbbr/dualroot: rename SP package certificate file ... Currently only single signing domain is supported for SP packages but there is plan to support dual signing domains if CoT is dualroot. SP_CONTENT_CERT_ID is the certificate file which is currently generated and signed with trusted world key which in-turn is derived from Silicon provider RoT key. To allow dual signing domain for SP packages, other certificate file will be derived from Platform owned RoT key. This patch renames "SP_CONTENT_CERT_ID" to "SIP_SP_CONTENT_CERT_ID" and does other related changes. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I0bc445a3ab257e2dac03faa64f46e36a9fed5e93 Manish Pandey committed on 31 Jul 2020
2020-07-30	000653b Browse files » fdts: n1sdp: DTS file for single-chip and multi-chip environment. ... N1SDP supports both single-chip and multi-chip environment. Added DTS file for both type of environment. Enabled DTS files compilation for N1SDP platform. Change-Id: I66af88dcfb841893eb6ed2ca18d3025de81236a0 Co-authored-by: Robin Murphy <Robin.Murphy@arm.com> Co-authored-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com> Co-authored-by: Manoj Kumar <manoj.kumar3@arm.com> Co-authored-by: Anurag Koul <anurag.koul@arm.com> Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com> Andre Przywara authored on 6 Jul 2020 Sayanta Pattanayak committed on 30 Jul 2020
2020-07-10	567bfe5 Browse files » dts: Add CoT descriptor nodes and properties in device tree ... Added CoT descriptor nodes and properties in device tree. Currently, CoT descriptors which are used by BL2 are added as part of device tree. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Iff23cff843e5489fac18bcee5f5d6a71de5ad0d0 Manish V Badarkhe authored on 29 Jun 2020 Sandrine Bailleux committed on 10 Jul 2020
2020-07-06	ef93cfa Browse files » corstone700: splitting the platform support into FVP and FPGA ... This patch performs the following: - Creating two corstone700 platforms under corstone700 board: fvp and fpga - Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform - The platform can be specified using the TARGET_PLATFORM Makefile variable (possible values are: fvp or fpga) - Allowing to use u-boot by: - Enabling NEED_BL33 option - Fixing non-secure image base: For no preloaded bl33 we want to have the NS base set on shared ram. Setup a memory map region for NS in shared map and set the bl33 address in the area. - Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected platform - Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163 Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Abdellatif El Khlifi committed on 6 Jul 2020
2020-06-09	452d5e5 Browse files » plat/fvp: Add support for dynamic description of secure interrupts ... Using the fconf framework, the Group 0 and Group 1 secure interrupt descriptors are moved to device tree and retrieved in runtime. This feature is enabled by the build flag SEC_INT_DESC_IN_FCONF. Change-Id: I360c63a83286c7ecc2426cd1ff1b4746d61e633c Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Madhukar Pappireddy committed on 9 Jun 2020
2020-06-03	bca652a Browse files » dts: stm32mp157c: fix etzpc node location in DTSI file ... Fix etzpc node location in stm32mp157c DTSI file as requested during the patch review. The comment was addressed then fixup change discarded while rebasing. Change-Id: Ie53531fec7da224de0b86c968a66aec441bfc25d Fixes: 627298d4b655 ("dts: stm32mp157c: add etzpc node") Reported-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Etienne Carriere committed on 3 Jun 2020
2020-06-03	627298d Browse files » dts: stm32mp157c: add etzpc node ... Add a node for the ETZPC device so that driver initializes during stm32mp15* boot sequence. Change-Id: I84bf10572e5df7b8f450163c79bcfe6956fc838f Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Etienne Carriere committed on 3 Jun 2020
2020-05-27	f5c58af Browse files » plat/arm: Introduce TC0 platform ... This patch adds support for Total Compute (TC0) platform. It is an initial port and additional features are expected to be added later. TC0 has a SCP which brings the primary Cortex-A out of reset which starts executing BL1. TF-A optionally authenticates the SCP ram-fw available in FIP and makes it available for SCP to copy. Some of the major features included and tested in this platform port include TBBR, PSCI, MHUv2 and DVFS. Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef Signed-off-by: Usama Arif <usama.arif@arm.com> Usama Arif committed on 27 May 2020
2020-05-19	003faaa Browse files » FVP: Add support for passing platform's topology to DTS ... This patch adds support for passing FVP platform's topology configuration to DTS files for compilation, which allows to build DTBs with correct number of clusters and CPUs. This removes non-existing clusters/CPUs from the compiled device tree blob and fixes reported Linux errors when trying to power on absent CPUs/PEs. If DTS file is passed using FVP_HW_CONFIG_DTS build option from the platform's makefile, FVP_CLUSTER_COUNT, FVP_MAX_CPUS_PER_CLUSTER and FVP_MAX_PE_PER_CPU parameters are used, otherwise CI script will use the default values from the corresponding DTS file. Change-Id: Idcb45dc6ad5e3eaea18573aff1a01c9344404ab3 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Alexei Fedorov committed on 19 May 2020
2020-05-15	cbf9e84 Browse files » plat/arm/fvp: Support performing SDEI platform setup in runtime ... This patch introduces dynamic configuration for SDEI setup and is supported when the new build flag SDEI_IN_FCONF is enabled. Instead of using C arrays and processing the configuration at compile time, the config is moved to dts files. It will be retrieved at runtime during SDEI init, using the fconf layer. Change-Id: If5c35a7517ba00a9f258d7f3e7c8c20cee169a31 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com> Co-authored-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Balint Dobszay authored on 18 Dec 2019 Madhukar Pappireddy committed on 15 May 2020
2020-04-17	e3c152d Browse files » fdts: a5ds: Fix for the system timer issue. ... A5DS FPGA system timer clock frequency is 7.5Mhz. The dt is file updated inline with the hardware clock frequency. Change-Id: I3f6c2e0d4a7b293175a42cf398a8730448504af9 Signed-off-by: lakshmi Kailasanathan <lakshmi.Kailasanathan@arm.com> lakshmi Kailasanathan committed on 17 Apr 2020
2020-03-24	e515c1d Browse files » corstone700: updating the kernel arguments to support initramfs ... In the context of enabling initramfs this change makes the kernel arguments compatible with the initramfs requirements Change-Id: Ifa955a5790ae1398fd8ad9ca1c8272f019c121a6 Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Abdellatif El Khlifi committed on 24 Mar 2020
2020-03-11	4682461 Browse files » fconf: Extract topology node properties from HW_CONFIG dtb ... Create, register( and implicitly invoke) fconf_populate_topology() function which extracts the topology related properties from dtb into the newly created fconf based configuration structure 'soc_topology'. Appropriate libfdt APIs are added to jmptbl.i file for use with USE_ROMLIB build feature. A new property which describes the power domain levels is added to the HW_CONFIG device tree source files. This patch also fixes a minor bug in the common device tree file fvp-base-gicv3-psci-dynamiq-common.dtsi As this file includes fvp-base-gicv3-psci-common.dtsi, it is necessary to delete all previous cluster node definitons because DynamIQ based models have upto 8 CPUs in each cluster. If not deleted, the final dts would have an inaccurate description of SoC topology, i.e., cluster0 with 8 or more core nodes and cluster1 with 4 core nodes. Change-Id: I9eb406da3ba4732008a66c01afec7c9fa8ef59bf Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Madhukar Pappireddy committed on 11 Mar 2020
2020-03-04	c84cbf4 Browse files » fdts: a5ds: add ethernet node in devicetree ... This change is to add ethernet and voltage regulator nodes into a5ds devicetree. Change-Id: If9ed67040d54e76af1813c9f99835f51f617e9df Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> Vishnu Banavath committed on 4 Mar 2020
2020-02-26	e718e61 Browse files » Modify multithreaded dts file of DynamIQ FVPs ... The dts file now contains a CPU map that precisely describes the topology including thread nodes. The map was also extended to have 16 PEs to be able to test multithreaded FVPs with 8 cores in the same cluster. Signed-off-by: Imre Kis <imre.kis@arm.com> Change-Id: If39559b05d20bfd68d0ecf830ddcbc5233b288a0 Imre Kis authored on 17 Dec 2019 Kis Imre committed on 26 Feb 2020
2020-02-18	d983b7a Browse files » corstone700: fdts: using DDR memory and XIP rootfs ... This patch allows to use DDR address in memory node because on FPGA we typically use DDR instead of shared RAM. This patch also modifies the kernel arguments to allow the rootfs to be mounted from a direct mapping of the QSPI NOR flash using the physmap driver in the kernel. This allows to support CRAMFS XIP. Change-Id: I4e2bc6a1f48449c7f60e00f5f1a698df8cb2ba89 Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Rui Silva authored on 9 Oct 2019 Manish Pandey committed on 18 Feb 2020
2020-02-17	6aa138d Browse files » corstone700: set UART clocks to 32MHz ... Adding support for 32MHz UART clock and selecting it as the default UART clock Change-Id: I9541eaff70424e85a3b5ee4820ca0e7efb040d2c Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Vishnu Banavath authored on 7 Aug 2019 Abdellatif El Khlifi committed on 17 Feb 2020
2020-02-13	0ad5b31 Browse files » Fix topology description of cpus for DynamIQ based FVP ... DynamIQ based designs have upto 8 CPUs in each cluster. This patch fixes the device tree node which describes the topology of the CPU for DynamIQ FVP Model. Change-Id: I7146bc79029ce38314026d4853e5b6406863725c Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Madhukar Pappireddy committed on 13 Feb 2020
2020-01-21	e5eaf88 Browse files » Merge "Replace dts includes with C preprocessor syntax" into integration Manish Pandey authored on 21 Jan 2020 TrustedFirmware Code Review committed on 21 Jan 2020
2020-01-20	46e9b7a Browse files » fdts: stm32mp1: remove second QSPI flash instance ... Remove second flash node as only one must be used by QSPI NOR driver. Change-Id: I48189f2fdf4e0455aabe7d4cd9b2f3d36bb9cfb5 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Lionel Debieve committed on 20 Jan 2020
2020-01-20	7e51e88 Browse files » fdts: stm32mp1: update for FMC2 pin muxing ... Include the required FMC2 pinmux definition for the NAND management. Change-Id: I80333deacdf3444b2f21f17f2fb5919e569a3591 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Lionel Debieve committed on 20 Jan 2020
2020-01-14	2d51b55 Browse files » Replace dts includes with C preprocessor syntax ... Using the /include/ syntax, the include was evaluated by dtc, only after running the preprocessor, therefore the .dtsi files were not preprocessed. This patch adds the #include syntax instead. Evaluating this and preprocessing the files now happens in a single step, done by the C preprocessor. Change-Id: I6d0104b6274316fc736e84973502a4d6c2c9d6e0 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com> Balint Dobszay committed on 14 Jan 2020
2020-01-07	786890c Browse files » A5DS: Correct system freq, Cache Writeback Granule ... Correct the system, timer and uart frequencies to successfully run the stack on FPGA Correct Cortex-A5MPcore to 8 word granularity for Cache writeback Change-Id: I2c59c26b7dca440791ad39f2297c68ae513da7b6 Signed-off-by: Avinash Mehta <avinash.mehta@arm.com> Avinash Mehta committed on 7 Jan 2020
2019-12-18	ab3b00f Browse files » fdts: a5ds: cleanup enable-method in devicetree ... Same enable method is used by all the four cores. So, make it globally for all the cores instead of adding it to individual level. Change-Id: I9b5728b0e0545c9e27160ea586009d929eb78cad Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> Vishnu Banavath authored on 13 Dec 2019 vishnu.banavath committed on 18 Dec 2019
2019-12-18	79c6c34 Browse files » fdts: a5ds: add L2 cache node in devicetree ... This change is to add L2 cache node into a5ds device tree. Change-Id: I64b4b3e839c3ee565abbcd1567d1aa358c32d947 Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> Vishnu Banavath authored on 13 Dec 2019 vishnu.banavath committed on 18 Dec 2019
2019-11-13	38c078e Browse files » Add multithreaded DynamIQ dts file ... The new dts file overrides the MPIDR values of the processing elements which were defined in the common dtsi file. The new dts file defines four cores in a single cluster, each core having two threads. Signed-off-by: Imre Kis <imre.kis@arm.com> Change-Id: I0f8d8d250289077aee11eede4508871bb61dbc88 Imre Kis committed on 13 Nov 2019
2019-10-03	2dc9fe7 Browse files » fdts: stm32mp1: move FDCAN to PLL4_R ... LTDC modifies the clock frequency to adapt it to the display. Such frequency change is not detected by the FDCAN driver that instead caches the value at probe and pretends to use it later. This change fixes the issue by moving the FDCAN to PLL4_R, leaving the LTDC alone on PLL4_Q. Signed-off-by: Antonio Borneo <antonio.borneo@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I8230868b2b5fd6deb6e3f9dc3911030d8d484c58 Antonio Borneo authored on 29 Jul 2019 Yann Gautier committed on 3 Oct 2019
2019-09-27	ace2368 Browse files » Merge changes from topic "ld/stm32-authentication" into integration ... * changes: stm32mp1: add authentication support for stm32image bsec: move bsec_mode_is_closed_device() service to platform crypto: stm32_hash: Add HASH driver Soby Mathew authored on 27 Sep 2019 TrustedFirmware Code Review committed on 27 Sep 2019
2019-09-23	ec885ba Browse files » a5ds: add multicore support ... Enable cores 1-3 using psci. On receiving the smc call from kernel, core 0 will bring the secondary cores out pen and signal an event for the cores. Currently on switching the cores is enabled i.e. it is not possible to suspend, switch cores off, etc. Change-Id: I6087e1d2ec650e1d587fd543efc1b08cbb50ae5f Signed-off-by: Usama Arif <usama.arif@arm.com> Usama Arif committed on 23 Sep 2019
2019-09-23	4bdb1a7 Browse files » stm32mp1: add authentication support for stm32image ... This commit adds authentication binary support for STM32MP1. It prints the bootrom authentication result if signed image is used and authenticates the next loaded STM32 images. It also enables the dynamic translation table support (PLAT_XLAT_TABLES_DYNAMIC) to use bootrom services. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: Iba706519e0dc6b6fae1f3dd498383351f0f75f51 Lionel Debieve committed on 23 Sep 2019