2014-06-08 |
Juno: Enable non-secure accesses to the system timer
...
This patch programs the CNTCTLBase.CNTNSAR to give non-secure access
to timer frame 1. It also programs the CNTCTLBase.CNTACR1 to give
access to all the timer registers in this frame.
Change-Id: Ia10c9572a70bd5910031de1994116bb9314efd80
Conflicts:
plat/juno/bl31_plat_setup.c
plat/juno/platform.h
Sandrine Bailleux
authored
on 3 Jun 2014
Achin Gupta
committed
on 8 Jun 2014
|
Juno: add support for PSCI cpu_suspend api
...
This patch adds support for the PSCI cpu_suspend api to allow entry
into low power states until affinity level 1 i.e. cluster. It mainly
ensures that a consolidated power off command which specifies the
level to which each affinity level should be powered down is sent to
the SCP. It also ensures the MHU driver waits for the SCP to pick up a
command before doing further processing.
Change-Id: I8ad10652d388525730a228f0900a659246dd5087
Achin Gupta
committed
on 8 Jun 2014
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Add support for selected Cortex-A57 r0p0 errata
...
This patch ensures that workarounds for erratas #806969, #813420 & #814670 that
affect Cortex-A57 r0p0 as described in the errata notice document are
implemented after every reset on each cpu.
Change-Id: I37ee16bafa623c405197925c5a0e66811d4c50ae
Achin Gupta
committed
on 8 Jun 2014
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2014-06-05 |
PL011: Fix a bug in the UART FIFO polling
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Before attempting to write a character, the PL011 driver polls
the PL011_UARTFR_TXFF bit to know whether the UART FIFO is full.
However, the comparison with 1 was incorrect because
PL011_UARTFR_TXFF is not at bit 0. This patch fixes it.
Change-Id: I4b53c28612f58581c6189ed6c794ed02cc2a89e3
Sandrine Bailleux
committed
on 5 Jun 2014
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juno: Make the build fail when RESET_TO_BL31 != 0
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Enabling BL3-1 entrypoint as the CPU reset vector in place of the
BL1 entrypoint is not supported on Juno at the moment. This patch
modifies the build system so that the build will crash straight
away if the user attempts to use this feature on Juno.
Change-Id: I641275fa37c2892fae7b944219b406f945e7e1b4
Sandrine Bailleux
committed
on 5 Jun 2014
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juno: Add a check to verify BL2 to BL31 plat. param
...
This concerns only debug builds. In BL2, we now pass a special value
to BL3-1 through x1. In BL3-1, we check that we receive the correct
value. This ensures that any platform set value is correctly passed
from BL2 to BL3-1.
Change-Id: Icb94d0e99ca445dcbe574a7d5e291659bba2209e
Sandrine Bailleux
committed
on 5 Jun 2014
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juno: Rename platform porting functions
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Change-Id: I069a552b772cffb06c9e9c8cbec68f21b46aa9d4
Sandrine Bailleux
committed
on 5 Jun 2014
|
juno: Use the enable_mmu_elX() functions from lib/aarch64/xlat_tables.c
...
Juno code can re-use the enable_mmu_elX() functions from
lib/aarch64/xlat_tables.c.
Because the Juno port now includes plat/common/aarch64/plat_common.c
the juno specific 'plat_common.c' needs to be renamed to avoid
name conflicts at build time.
Change-Id: I1e9cc6484643fbf516dfac0236573e0474ccc0a2
Sandrine Bailleux
committed
on 5 Jun 2014
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juno: Rework header file inclusion
...
Change-Id: I0837d787837a40a724a8b7f2e3abd82287f403f3
Sandrine Bailleux
committed
on 5 Jun 2014
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juno: Split platform.h into separate headers
...
Change-Id: Ic0abaa12f13a6a1dead41c914c6c103a65f273fa
Sandrine Bailleux
committed
on 5 Jun 2014
|
juno: Clean a few details in BL2 & BL3-1 plat setup code
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Change-Id: Id1cd218baf4e35ad2e82e413b030ac96763a8104
Sandrine Bailleux
committed
on 5 Jun 2014
|
juno: Move BL3-1 arguments from normal DRAM to trusted RAM
...
On Juno, BL3-1 arguments used to sit at the beginning of the normal
DRAM. This patch moves them in trusted RAM. BL2 now allocates them
as a platform-specific static variable. BL3-1 then copies them
internally before the MMU is enabled.
Change-Id: I5cf526edfab5b49925b685092ff78506a5882f49
Sandrine Bailleux
committed
on 5 Jun 2014
|
juno: Do not retrieve entry point info for BL3-0 image
...
The BL3-0 gets loaded by BL2 but it will never be executed by the AP.
Therefore we don't care about the entry point information returned
by load_image() function.
Change-Id: I9bf7e04fa41a205b7595f58f0c3484a2507141fc
Sandrine Bailleux
committed
on 5 Jun 2014
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Make the entry point parameter optional in load_image()
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There are cases where the entry point information is useless to the
caller, e.g. when an image just needs to be loaded in memory but won't
ever be executed.
This patch allows load_image() function to take a NULL pointer as the
entry point parameter. In this case, it won't be populated.
Change-Id: Ie9394b054457706c6699926c5e0206e0c3851c56
Sandrine Bailleux
committed
on 5 Jun 2014
|
juno: Pass primary CPU MPID to UEFI
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Change-Id: I734bf8a268d45a748dc2d1671656385212cdd465
Sandrine Bailleux
committed
on 5 Jun 2014
|
Revert commit "Workaround: Setup register context for BL3-3"
...
This reverts commit 033c52b
because the workaround it introduced is no longer needed since
BL3-1 interface rework.
This does not revert the change on BL33 base address on Juno, though.
Change-Id: Idc747718a0af94c54931d4a9932f145350b0a75f
Sandrine Bailleux
committed
on 5 Jun 2014
|
juno: Fix bl30_image() function
...
The interface to load an image has changed so load_bl30() function
needs to be modified accordingly.
Change-Id: I7ff3f808579f6dcd4ddab7aa17f18932152ea33f
Sandrine Bailleux
committed
on 5 Jun 2014
|
juno: Implement platform_mem_init() function
...
The platform_mem_init() function doesn't do anything on Juno.
We don't need to carry out any memory initialization as the
Secure RAM is accessible straight away.
Change-Id: Ic5f778a71279add95a75c20d0f7b2cf57968c5df
Sandrine Bailleux
committed
on 5 Jun 2014
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juno: Define the extents of all bootloader images
...
Define:
- Extents of BL1 RO and RW sections
- BL2 limit address
- BL3-1 limit address
- BL3-2 limit address
Change-Id: Id86243c4d5b1f769a9b0d5a639665c3cb5e14aee
Sandrine Bailleux
committed
on 5 Jun 2014
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juno: Limit BL3-1 read/write access to SRAM
...
At present BL3-1 has access to all of the SRAM, including
regions that are mapped as read-only and non-cacheable by other
firmware images.
This patch restricts BL3-1 to only be able to read/write from
memory used for its own data sections
Change-Id: I32126adaa93d8e42f4cea5a8f676b3efe3eb04f6
Sandrine Bailleux
committed
on 5 Jun 2014
|
juno: Compile GIC files in BL3-2
...
Change-Id: Id57a159edf2a54596f4647ab80bc3ff6e4c6a7d0
Sandrine Bailleux
committed
on 5 Jun 2014
|
juno: Implement functions to access an ARM GIC
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Change-Id: I8be0cc5e2495864463c310f2d2d64740495e3bb4
Sandrine Bailleux
committed
on 5 Jun 2014
|
juno: Implement plat_interrupt_type_to_line() function
...
Change-Id: I87083b5891fa8037cdee567ebadeaa1952f52d0c
Sandrine Bailleux
committed
on 5 Jun 2014
|
juno: Use the reworked handover interface between BL stages
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Propagate FVP changes introduced by these 3 commits:
- 29fb905d5f Rework handover interface between BL stages
- 4112bfa0c2 Populate BL31 input parameters as per new spec
- 6871c5d3a2 Rework memory information passing to BL3-x images
Change-Id: If024f575782d9c74db4cf929a2ab40563921dedd
Sandrine Bailleux
committed
on 5 Jun 2014
|
Document 'BL30' build configuration in user guide
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Change-Id: I67d8d44a708aefb04b285436dd45ff4589e3b3e9
Sandrine Bailleux
committed
on 5 Jun 2014
|
juno: Implement 'plat_print_gic_regs' macro
...
The 'plat_print_gic_regs' macro will print the contents of
the GICC_IAR and GICC_CTLR registers.
Change-Id: Ib435522c2d597e15c31fe05f9b0b310b9053206c
Sandrine Bailleux
committed
on 5 Jun 2014
|
juno: Provide per-EL MMU setup functions
...
Instead of having a single version of the MMU setup functions for all
bootloader images that can execute either in EL3 or in EL1, provide
separate functions for EL1 and EL3. Each bootloader image can then
call the appropriate version of these functions. The aim is to reduce
the amount of code compiled in each BL image by embedding only what's
needed (e.g. BL1 to embed only EL3 variants).
Change-Id: Ie3f6fb58f7d9ea4e4085b5069e27d6b9dceaa286
Sandrine Bailleux
committed
on 5 Jun 2014
|
juno: Add support for BL3-2 image
...
This patch implements the TSP on Juno. It executes from Secure RAM.
Also, the other bootloader images (i.e. BL1 R/W, BL2 and BL3-1) have
been moved around. The reason is, although there was enough space
overall to store the TSP in SRAM, there was no contiguous free chunk
of SRAM big enough to hold it.
This patch keeps the overall memory layout (i.e. keeping BL1 R/W at
the bottom, BL2 at the top and BL3-1 in between) but moves the base
addresses of all the bootloader images in such a way that:
- memory fragmentation is reduced enough to fit BL3-2 in;
- new base addresses are suitable for release builds as well as debug
ones;
- each image has a few extra kilobytes for future growth.
BL3-1 and BL3-2 are the images which received the biggest slice
of the cake since they will most probably grow the most.
A few useful numbers for reference (valid at the time of this patch):
|-----------------------|-------------------------------
| image size (debug) | extra space for the future
--------|-----------------------|-------------------------------
BL1 R/W | 28 KB | 4 KB
BL2 | 48 KB | 4 KB
BL3-1 | 96 KB | 8 KB
BL3-2 | 56 KB | 8 KB
--------|-----------------------|-------------------------------
Total | 228 KB | 24 KB = 252 KB
--------|-----------------------|-------------------------------
Note: On Juno, although the Secure RAM is 256 KB, the first 4KB
are reserved for the AP/SCP mailboxes.
Change-Id: I999ec39589c45beabe1ecd772641623e58569a6e
Sandrine Bailleux
committed
on 5 Jun 2014
|
juno: Access MPIDR_EL1 register directly in assembler
...
Instead of using the read_mpidr() helper functions to read the
MPIDR_EL1 system register, assembler coded functions should
use MRS/MSR instructions. This results in faster and more
compact code.
Change-Id: I42bb61a926113c4f80aa1ce72ee29ab26cd8fa43
Sandrine Bailleux
committed
on 5 Jun 2014
|
juno: Correct usage of mem. barriers in MMU setup code
...
Add memory barriers to ensure that all translation table writes
have drained into memory, the TLB invalidation is complete,
and translation register writes are committed before enabling
the MMU.
Also ensure the MMU enable takes effect immediately.
These changes are necessary because of commit 8cec598ba3b6.
Change-Id: I65b5c3593af27f19da3fd2170c55f631f1ce7b81
Sandrine Bailleux
committed
on 5 Jun 2014
|