Merge pull request #1900 from soby-mathew/sm/revert_xlat_changes ...

xlat_tables_v2: Revert recent changes to remove recursion

xlat_tables_v2: Revert recent changes to remove recursion ...

This commit reverts the following commits:

- c54c7fc35842 ("xlat_tables_v2: print xlat tables without recursion")
- db8cac2d986a ("xlat_tables_v2: unmap region without recursion.")
- 0ffe269215bd ("xlat_tables_v2: map region without recursion.")

This was part of PR#1843.

A problem has been detected in one of our test run configurations
involving dynamic mapping of regions and it is blocking the next
release. Until the problem can be solved, it is safer to revert
the changes.

Change-Id: I3d5456e4dbebf291c8b74939c6fb02a912e0903b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Merge pull request #1894 from jts-arm/e1_midr ...

Fix MIDR_EL1 value for Neoverse E1

Merge pull request #1895 from AlexeiFedorov/af/declare_pauth_experimental ...

Declare ENABLE_PAUTH build option as experimental

Declare PAuth for Secure world as experimental ...

Declare ENABLE_PAUTH and CTX_INCLUDE_PAUTH_REGS
build options as experimental.
Pointer Authentication is enabled for Non-secure world
irrespective of the value of these build flags if the
CPU supports it.
The patch also fixes the description of fiptool 'help' command.

Change-Id: I46de3228fbcce774a2624cd387798680d8504c38
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Merge pull request #1892 from sandrine-bailleux-arm/sb/pauth ...

Pointer authentication fixes

Fix wrong MIDR_EL1 value for Neoverse E1 ...

Change-Id: I75ee39d78c81ecb528a671c0cfadfc2fe7b5d818
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Merge pull request #1866 from mmind/rockchip-fdt-param ...

rockchip: add an fdt parsing stub for platform param

Merge pull request #1888 from jts-arm/zeus ...

Introduce preliminary support for Neoverse Zeus

Merge pull request #1889 from jts-arm/var4 ...

Apply variant 4 mitigation for Neoverse N1

Merge pull request #1890 from jts-arm/mbedtls ...

Update documentation for mbed TLS v2.16

Merge pull request #1891 from soby-mathew/sm/increase_fvp_stack ...

fvp: Increase the size of the stack for FVP

rockchip: add an fdt parsing stub for platform param ...

The Rockchip ATF platform can be entered from both Coreboot and U-Boot.
While Coreboot does submit the list of linked parameter structs as
platform param, upstream u-boot actually always provides a pointer
to a devicetree as parameter.
This results in current ATF not running at all when started from U-Boot.

To fix this, add a stub that checks if the parameter is a fdt so we
can at least boot and not get stuck. Later on we can extend this with
actual parsing of information from the devicetree.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

fvp: Increase the size of the stack for FVP ...

When RECLAIM_INIT_CODE is 1, the stack is used to contain the .text.init
section. This is by default enable on FVP. Due to the size increase of
the .text.init section, the stack had to be adjusted contain it.

Change-Id: Ia392341970fb86c0426cf2229b1a7295453e2e32
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Update documentation for mbed TLS v2.16 ...

Change-Id: I1854b5830dbd48e909a4ce1b931c13fb3e997600
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Put Pointer Authentication key value in BSS section ...

The dummy implementation of the plat_init_apiakey() platform API uses
an internal 128-bit buffer to store the initial key value used for
Pointer Authentication support.

The intent - as stated in the file comments - was for this buffer to
be write-protected by the MMU. Initialization of the buffer would be
performed before enabling the MMU, thus bypassing write protection
checks.

However, the key buffer ended up into its own read-write section by
mistake due to a typo on the section name ('rodata.apiakey' instead of
'.rodata.apiakey', note the leading dot). As a result, the linker
script was not pulling it into the .rodata output section.

One way to address this issue could have been to fix the section
name. However, this approach does not work well for BL1. Being the
first image in the boot flow, it typically is sitting in real ROM
so we don't have the capacity to update the key buffer at any time.

The dummy implementation of plat_init_apiakey() provided at the moment
is just there to demonstrate the Pointer Authentication feature in
action. Proper key management and key generation would have to be a
lot more careful on a production system.

Therefore, the approach chosen here to leave the key buffer in
writable memory but move it to the BSS section. This does mean that
the key buffer could be maliciously updated for intalling unintended
keys on the warm boot path but at the feature is only at an
experimental stage right now, this is deemed acceptable.

Change-Id: I121ccf35fe7bc86c73275a4586b32d4bc14698d6
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Fix restoring APIBKey registers ...

Instruction key A was incorrectly restored in the instruction key B
registers.

Change-Id: I4cb81ac72180442c077898509cb696c9d992eda3
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Introduce preliminary support for Neoverse Zeus ...

Change-Id: If56d1e200a31bd716726d7fdc1cc0ae8a63ba3ee
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Apply variant 4 mitigation for Neoverse N1 ...

This patch applies the new MSR instruction to directly set the
PSTATE.SSBS bit which controls speculative loads. This new instruction
is available at Neoverse N1 core so it's utilised.

Change-Id: Iee18a8b042c90fdb72d2b98f364dcfbb17510728
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Merge pull request #1859 from JackyBai/master ...

refact the imx8m common code and add the imx8mm support

Merge pull request #1883 from ambroise-arm/av/a17-errata ...

Apply workarounds for errata of Cortex-A17

Cortex-A17: Implement workaround for errata 852423 ...

Change-Id: I3a101e540f0b134ecf9a51fa3d7d8e3d0369b297
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Cortex-A17: Implement workaround for errata 852421 ...

Change-Id: Ic3004fc43229d63c5a59ca74c1837fb0604e1f33
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Merge pull request #1884 from AlexeiFedorov/af/set_march_to_arch_minor ...

Allow setting compiler's target architecture

Merge pull request #1882 from ambroise-arm/av/a15-errata ...

Apply workarounds for errata of Cortex-A15

Merge pull request #1881 from sandrine-bailleux-arm/sb/doc-fixes ...

Minor doc fixes

Merge pull request #1880 from lmayencourt/lm/pie ...

PIE: fix linking with pie and binutils > 2.27

Merge pull request #1879 from pbeesley-arm/pb/todo-removal ...

Pb/todo removal

Merge pull request #1878 from jts-arm/sctlr ...

Apply stricter speculative load restriction

Merge pull request #1874 from hadi-asyrafi/qspi_boot ...

intel: QSPI boot enablement