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History for arm-trusted-firmware / maintainers.rst

2019-03-04	4a56163 Browse files » rcar_gen3: Add myself as a maintainer ... Add myself into the maintainers file to make Jorge's life easier. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Marek Vasut committed on 4 Mar 2019
2019-02-07	1f0d710 Browse files » maintainers: Fix broken links to some Github accounts ... Change-Id: I89a451fa22d517f9c59dfa0a74f28deb6d750b8f Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Sandrine Bailleux committed on 7 Feb 2019
2019-02-05	Unverified 49dd048 Browse files » Merge pull request #1806 from thomas-arm/master ... sgi/sgm: add a second maintainer for Arm's SGI and SGM platforms Antonio Niño Díaz authored on 5 Feb 2019 GitHub committed on 5 Feb 2019
2019-02-05	e64044b Browse files » sgi/sgm: add a second maintainer for Arm's SGI and SGM platforms ... Add a second maintainer for Arm's SGI and SGM platform support in trusted firmware to handle the review and maintenance of existing and upcoming platforms. Change-Id: Ie7fa8da280d9351f7543122fb261d6ac6c7e15ad Signed-off-by: Thomas Abraham <thomas.abraham@arm.com> Thomas Abraham committed on 5 Feb 2019
2019-02-04	Unverified 6ce3034 Browse files » Merge pull request #1783 from thloh85-intel/integration_v2 ... plat: intel: Add BL2 support for Stratix 10 SoC Antonio Niño Díaz authored on 4 Feb 2019 GitHub committed on 4 Feb 2019
2019-02-04	9d82ef2 Browse files » plat: intel: Add BL2 support for Stratix 10 SoC ... This adds BL2 support for Intel Stratix 10 SoC FPGA. Functionality includes: - Release and setup peripherals from reset - Calibrate DDR - ECC DDR Scrubbing - Load FIP (bl31 and bl33) Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com> Loh Tien Hock committed on 4 Feb 2019
2019-01-31	92d2f49 Browse files » maintainers: Add maintainter for Raspberry Pi 3 platform. ... This patch adds myself to co-maintainer list of Raspberry Pi 3 platform. Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org> Ying-Chun Liu (PaulLiu) committed on 31 Jan 2019
2019-01-14	dc20d26 Browse files » maintainers: Add maintainter for NXP i.MX8M platform. ... This patch adds me to various maintainer activities in the ATF tree associated with the NXP i.MX8M platform. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Jacky Bai committed on 14 Jan 2019
2019-01-04	bc8522a Browse files » maintainers: Fix path of Marvell documentation ... Change-Id: Idd5a2b700b936b22e94194dfadee68b968d03380 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Antonio Nino Diaz committed on 4 Jan 2019
2018-12-06	65d8582 Browse files » maintainers: Add Julius Werner for coreboot and console API ... I wrote most of this code and have a vested interest in keeping it healthy, so adding myself as a maintainer. Change-Id: I0edeebbc8336b6976dfaf393b3cfc7bc94089ac6 Signed-off-by: Julius Werner <jwerner@chromium.org> Julius Werner committed on 6 Dec 2018
2018-11-01	Unverified eb47f14 Browse files » Merge pull request #1623 from MISL-EBU-System-SW/a3700-support ... Add support for Armada 3700 and COMPHY porting layer Antonio Niño Díaz authored on 1 Nov 2018 GitHub committed on 1 Nov 2018
2018-10-26	37f647a Browse files » docs: gxbb: Add documentation ... Change-Id: Ie2465c1ccc482bd8eb5e5a71c580543095e4ba94 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Antonio Nino Diaz committed on 26 Oct 2018
2018-10-22	6414dc6 Browse files » tools: Move doimage to marvell folder for future add-ons ... Move doimage utility from toos/doimage to tools/marvell/doimage. This is done for supporting mode Marvell tools in the future. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin committed on 22 Oct 2018
2018-10-17	7e532c4 Browse files » rcar-gen3: initial commit for the rcar-gen3 boards ... Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com> Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1" MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher <simon.butcher@arm.com> Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas' Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com> Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com> * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam <festevam@gmail.com> Date: Tue Sep 4 10:23:12 2018 -0300 linux: The port has beent tested using mainline kernel. Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas' ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- cpuidle ------- enable kernel's cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p "Switch off SW23 and press return " foo echo mem > /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline Signed-off-by: ldts <jramirez@baylibre.com> Jorge Ramirez-Ortiz authored on 23 Sep 2018 ldts committed on 17 Oct 2018
2018-10-07	5e5e4d8 Browse files » add Marvell tools to maintained sources list ... Declate Marvell's ownership on tools/doimage Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin committed on 7 Oct 2018
2018-10-03	0c66e64 Browse files » maintainers: Correct github username for nariman to npoushin ... Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org> Nariman Poushin committed on 3 Oct 2018
2018-09-07	5686b2e Browse files » allwinner: add I2C glue driver ... Allwinner 64-bit SoCs all use the Mentor Graphics MI2CV I2C controller core, with inverted clear quirk. Add a glue driver for this. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Icenowy Zheng committed on 7 Sep 2018
2018-09-04	622e890 Browse files » maintainers: Add entries for imx7/WaARP7 and associated shared code ... This patch adds me to various maintainer activities in the ATF tree associated with the NXP i.MX7 generally and WaARP7 in particular. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Bryan O'Donoghue committed on 4 Sep 2018
2018-08-29	2485a3a Browse files » maintainers: Update maintainer for sgi/sgm platforms Nariman Poushin committed on 29 Aug 2018
2018-08-28	776e214 Browse files » maintainers: add drivers folders for STM32MP1 ... Folders drivers/st/ and include/drivers/st/ are added in maintainers.rst, under STM32MP1 platform port. This will allow notifications for the files modified there. Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 28 Aug 2018
2018-08-10	fcda63b Browse files » doc/maintainers: remove emmc framework ... Remove emmc framework from maintain list. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Haojian Zhuang committed on 10 Aug 2018
2018-07-24	efb3728 Browse files » Update list of maintainers for STM32MP1 ... Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 24 Jul 2018
2018-07-19	Unverified ba0248b Browse files » Merge pull request #1450 from MISL-EBU-System-SW/marvell-support-v6 ... Marvell support for Armada 8K SoC family danh-arm authored on 19 Jul 2018 GitHub committed on 19 Jul 2018
2018-07-18	752faf8 Browse files » maintainers: Add Marvell to maintainers list ... Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin committed on 18 Jul 2018
2018-07-04	0d0380c Browse files » maintainers: allwinner: add missing link to github page ... A proper link to Samuel's github page was missing. Add this to make the link actually work. Change-Id: I68b116935bf045df60b2e9309b5fd58a1c694d47 Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara committed on 4 Jul 2018
2018-06-28	aea86d8 Browse files » allwinner: Add Samuel as second maintainer ... As Samuel contributed most of the original code and he has an interest in that, add him as a second maintainer for the Allwinner port. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara committed on 28 Jun 2018
2018-06-28	9c9ba0b Browse files » maintainers: Modify format of file ... The previous format was not very practical and hard to parse by scripts. The current format is easier as it uses more tokens that can be identified by scripts, while maintaining a reasonably good result when it is rendered. Some maintainers maintain more than one subsystem but they were all part of the same entry. In cases like this the entry has been split into two to clarify what file belongs to which subsystem. The list of maintainers of the Trusted Firmware has been updated. Change-Id: I4be2d527c5171e8d2d86fb49e45e1d9dbcbd2d80 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Antonio Nino Diaz committed on 28 Jun 2018
2018-06-22	8b382b8 Browse files » maintainers.rst: separate maintainership of uniphier and synquacer ... Socionext has multiple product lines. The UniPhier is not the only platform any more. Correct the maintainership. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Masahiro Yamada committed on 22 Jun 2018
2018-06-21	150c38e Browse files » synquacer: Add platform makefile and documentation ... Add Makefile and plaform definations file. My thanks to Daniel Thompson and Ard Biesheuvel for the bits and pieces I've taken from their earlier work regarding build and deploy steps for Developerbox based on Synquacer SoCs. They deserve much of the credit for this work although, since I assembled and tested things, any blame is probably mine. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Daniel Thompson <daniel.thompson@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Sumit Garg committed on 21 Jun 2018
2018-06-19	1841c53 Browse files » ti: k3: Setup initial files for platform ... Create the baseline Makefile, platform definitions file and platform specific assembly macros file. This includes first set of constants for the platform including cache sizes and linker format and a stub for BL31 and the basic memory layout K3 SoC family of processors do not use require a BL1 or BL2 binary, since such functions are provided by an system controller on the SoC. This lowers the burden of ATF to purely managing the local ARM cores themselves. Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Nishanth Menon authored on 13 Oct 2016 Andrew F. Davis committed on 19 Jun 2018