fdts: stm32mp1: move FDCAN to PLL4_R ...

LTDC modifies the clock frequency to adapt it to the display. Such
frequency change is not detected by the FDCAN driver that instead
caches the value at probe and pretends to use it later.

This change fixes the issue by moving the FDCAN to PLL4_R,
leaving the LTDC alone on PLL4_Q.

Signed-off-by: Antonio Borneo <antonio.borneo@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I8230868b2b5fd6deb6e3f9dc3911030d8d484c58

Merge changes from topic "ld/stm32-authentication" into integration ...

* changes:
  stm32mp1: add authentication support for stm32image
  bsec: move bsec_mode_is_closed_device() service to platform
  crypto: stm32_hash: Add HASH driver

a5ds: add multicore support ...

Enable cores 1-3 using psci. On receiving the smc call from kernel,
core 0 will bring the secondary cores out pen and signal an event for
the cores. Currently on switching the cores is enabled i.e. it is not
possible to suspend, switch cores off, etc.

Change-Id: I6087e1d2ec650e1d587fd543efc1b08cbb50ae5f
Signed-off-by: Usama Arif <usama.arif@arm.com>

stm32mp1: add authentication support for stm32image ...

This commit adds authentication binary support for STM32MP1.
It prints the bootrom authentication result if signed
image is used and authenticates the next loaded STM32 images.
It also enables the dynamic translation table support
(PLAT_XLAT_TABLES_DYNAMIC) to use bootrom services.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Iba706519e0dc6b6fae1f3dd498383351f0f75f51

Add Linux DTS files for 32 bit threaded FVPs ...

RevC models have the MT bit set and the affinities shifted in the MPIDR
register. To make the Linux able to boot all CPUs it needs a modified
DTS file containing the shifted affinity values.

Beside these values the DTS files should be the same so the common part
was moved into a new file which is included in the DTS files with
shifted and non-shifted affinities.

The same setup already exists for 64 bit systems.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: I90f7b9c8d8a24c9b3f97232441dbe0a29aa8976d

plat/arm: Introduce corstone700 platform. ...

This patch adds support for Corstone-700 foundation IP, which integrates
both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible
subsystem.
This is an example implementation of Corstone-700 IP host firmware.

Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as
bringing Host out RESET. Host will start execution directly from BL32 and
then will jump to Linux.

It is an initial port and additional features are expected to be added
later.

Change-Id: I7b5c0278243d574284b777b2408375d007a7736e
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

plat/arm: Introduce A5 DesignStart platform. ...

This patch adds support for Cortex-A5 FVP for the
DesignStart program. DesignStart aims at providing
low cost and fast access to Arm IP.

Currently with this patch only the primary CPU is booted
and the rest of them wait for an interrupt.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I3a2281ce6de2402dda4610a89939ed53aa045fab

fdts: stm32mp1: realign device tree files with internal devs ...

Update DDR parameters to version 1.45.
Remove useless sdmmc1_dir_pins_b node.
Add USART3 and UART7 nodes.
Correct a PMIC value for USB regulator.
Add TIMER12, TIMER15, CRYP, HASH and USBOTG_HS nodes.
Update DTSI file for SDMMC compatible, but overwrite it with the former
name.
Move BSEC board_id node to boards DTS files, as this OTP is specific to
STMicroelectronics boards.

Change-Id: If4d2fe090c6a8368afe8e21e5ac70579911d3939
Signed-off-by: Yann Gautier <yann.gautier@st.com>

stm32mp1: add general SYSCFG management ...

The system configuration controller is mainly used to manage
the compensation cell and other IOs and system related settings.

The SYSCFG driver is in charge of configuring masters on the interconnect,
IO compensation, low voltage boards, or pull-ups for boot pins.
All other configurations should be handled in Linux drivers requiring it.

Device tree files are also updated to manage vdd-supply regulator.

Change-Id: I10fb513761a7d1f2b7afedca9c723ad9d1bccf42
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

fdts: Fix DTC warnings for STM32MP1 platform ...

DTC issues below warnings for STM32MP1 platform for using upper case
in unit address:

fdts/stm32mp15-ddr.dtsi:8.20-151.5: Warning (simple_bus_reg): /soc/ddr@5A003000: simple-bus unit address format error, expected "5a003000"
fdts/stm32mp157c-security.dtsi:9.25-13.5: Warning (simple_bus_reg): /soc/stgen@5C008000: simple-bus unit address format error, expected "5c008000"

Fix this by using the lower case unit address for concerned nodes.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Change-Id: Id3d19ac3b47ec6bcea2bd3382225e2e923dc4a70

stm32mp1: Add Avenger96 board support ...

Add board support for Avenger96 board from Arrow Electronics. This
board is based on STM32MP157A SoC and is one of the 96Boards Consumer
Edition platform.

More information about this board can be found in 96Boards website:
https://www.96boards.org/product/avenger96/

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Change-Id: Ic905f26c38d03883c6e4ea221b4b275a4b534857

fdts: stm32mp1: add bsec node ...

This node is added in a new file stm32mp157c-security.dtsi.
This node includes OTPs that should be shadowed and made readable
to non secure world.
Explicitly add status and secure-status, as these OTPs are accessible
by secure and non-secure world.

The stgen node is also moved to this file.

Change-Id: I3c89a01588d2e411fecfc44997e1c5df2fc37cad
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Merge pull request #1836 from Yann-lms/docs_and_m4 ...

Update documentation for STM32MP1 and add Cortex-M4 support

stm32mp1: add minimal support for co-processor Cortex-M4 ...

STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4.
The support for Cortex-M4 clocks is added when configuring the clock tree.
Some minimal security features to allow communications between A7 and M4
are also added.

Change-Id: I60417e244a476f60a2758f4969700b2684056665
Signed-off-by: Yann Gautier <yann.gautier@st.com>

plat/arm: Support for Cortex A5 in FVP Versatile Express platform ...

Cortex A5 doesnt support VFP, Large Page addressing and generic timer
which are addressed in this patch. The device tree for Cortex a5
is also included.

Change-Id: I0722345721b145dfcc80bebd36a1afbdc44bb678
Signed-off-by: Usama Arif <usama.arif@arm.com>

plat/arm: Introduce FVP Versatile Express platform. ...

This patch adds support for Versatile express FVP (Fast models).
Versatile express is a family of platforms that are based on ARM v7.
Currently this port has only been tested on Cortex A7, although it
should work with other ARM V7 cores that support LPAE, generic timers,
VFP and hardware divide. Future patches will support other
cores like Cortex A5 that dont support features like LPAE
and hardware divide. This platform is tested on and only expected to
work on single core models.

Change-Id: I10893af65b8bb64da7b3bd851cab8231718e61dd
Signed-off-by: Usama Arif <usama.arif@arm.com>

stm32mp1: introduce STM32MP1 discovery boards ...

Add the device tree files to support the 2 discovery boards: DK1 & DK2.

Change-Id: I90b4797dc69bd0aab1b643a72c932ead48a03c1f
Signed-off-by: Yann Gautier <yann.gautier@st.com>

stm32mp1: update I2C and PMIC drivers ...

Regulator configuration at boot takes more information from DT.
I2C configuration from DT is done in I2C driver.
I2C driver manages more transfer modes.
The min voltage of buck1 should also be increased to 1.2V,
else the platform does not boot.

Heavily modifies stm32_i2c.c since many functions move inside the source
file to remove redundant declarations.

Change-Id: I0bee5d776cf3ff15e687427cd6abc06ab237d025
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>

stm32mp1: update device tree files ...

The drivers are also updated to reflect the changes.
Set RCC as non-secure.

Change-Id: I568fa1f418355830ad1d4d1cdcdb910fb362231b
Signed-off-by: Yann Gautier <yann.gautier@st.com>

stm32mp1: rename stpmu1 to stpmic1 ...

This is the correct name of the IP.
Rename stm32mp1_pmic files to stm32mp_pmic.

Change-Id: I238a7d1f9a1d099daf7788dc9ebbd3146ba2f15f
Signed-off-by: Yann Gautier <yann.gautier@st.com>

stm32mp1: Add device tree files ...

Those device tree files are taken from STM32MP1 U-Boot and Linux.
And they are updated to fit TF-A needs.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

Dynamic_config: remove the FVP dtb files ...

Since FVP enables dynamic configuration by default, the DT blobs are
compiled from source and included in FIP during build. Hence this
patch removes the dtb files from the `fdts` folder.

Change-Id: Ic155ecd257384a33eb2aa38c9b4430e47b09cd31
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

Remove dtc warnings ...

DTC generates warnings when unit names begin with 0, or
when a node containing a reg or range property doesn't have a unit name
in the node name. This patch fixes those cases.

Change-Id: If24ec68ef3034fb3fcefb96c5625c47a0bbd8474
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

fdts: Add DTS for DynamIQ platforms ...

DynamIQ platforms host all CPUs in a single cluster. This patch adds a
DTS and DTB for DynamicQ platforms hosting up to 8 CPUs.

Change-Id: I2d97bc740ac3062818767e7251020644f5bb9100
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

FVP: Fix AArch32 dts for `interrupts` node ...

The commit 8d2c497 changed the interrupt map in `rtsm_ve-motherboard.dtsi`
for the Linux FDT sources to be compatible for FreeBSD. But this also
introduced a regression for FVP AArch32 mode but was undetected till now
because the corresponding DTB was not updated. This patch creates a
new `rtsm_ve-motherboard-aarch32.dtsi` which reverts the change and is
now included by the AArch32 DTS files.

Change-Id: Ibefbbf43a91c8fb890f0fa7a22be91f0227dad34
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

Add Linux DTS for FVP with threaded CPUs ...

In contrast with the non-multi-threading DTS, this enumerates MPIDR
values shifted by one affinity level to the left. The newly added DTS
reflects CPUs with a single thread in them.

Since both DTS files are the same apart from MPIDR contents, the common
bits have been moved to a separate file that's then included from the
top-level DTS files. The multi-threading version only updates the MPIDR
contents.

Change-Id: Id225cd93574f764171df8962ac76f42fcb6bba4b
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

Device tree changes to boot FreeBSD on FVPs ...

FreeBSD does not understand #interrupt-map in a device tree. This prevents the
GIC from being set up correctly. This patch removes the #interrupt-map in the
device trees for the Base and Foundation FVPs. This enables correct boot of
FreeBSD on these platforms.

These changes have been tested with FreeBSD and an Ubuntu cloud image
(ubuntu-16.04-server-cloudimg-arm64-uefi1.img) to ensure compatibility with
Linux.

Change-Id: I1347acdcf994ec4b1dd843ba32af9951aa54db73
Signed-off-by: Achin Gupta <achin.gupta@arm.com>

Fix incorrect copyright notices ...

Some files have incorrect copyright notices, this patch fixes all
files with deviations from the standard notice.

Change-Id: I66b73e78a50a235acb55f1e2ec2052a42c0570d2
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Merge pull request #727 from soby-mathew/sm/PSCI_lib_doc ...

AArch32: Update user-guide and add DTBs

AArch32: Update user-guide and add DTBs ...

This patch adds necessary updates for building and running Trusted
Firmware for AArch32 to user-guide.md. The instructions for running
on both `FVP_Base_AEMv8A-AEMv8A` in AArch32 mode and
`FVP_Base_Cortex-A32x4` models are added. The device tree files for
AArch32 Linux kernel are also added in the `fdts` folder.

Change-Id: I0023b6b03e05f32637cb5765fdeda8c8df2d0d3e