diff --git a/plat/juno/bl1_plat_setup.c b/plat/juno/bl1_plat_setup.c
index 7284521..3e97a8c 100644
--- a/plat/juno/bl1_plat_setup.c
+++ b/plat/juno/bl1_plat_setup.c
@@ -174,6 +174,18 @@
 		);
 }
 
+#define PCIE_SECURE_REG		0x3000
+#define PCIE_SEC_ACCESS_MASK	((1 << 0) | (1 << 1)) /* REG and MEM access bits */
+
+static void init_pcie(void)
+{
+	/*
+	 * PCIE Root Complex Security settings to enable non-secure
+	 * access to config registers.
+	 */
+	mmio_write_32(PCIE_CONTROL_BASE + PCIE_SECURE_REG, PCIE_SEC_ACCESS_MASK);
+}
+
 
 /*******************************************************************************
  * Function which will perform any remaining platform-specific setup that can
@@ -183,6 +195,7 @@
 {
 	init_nic400();
 	init_tzc400();
+	init_pcie();
 
 	/* Initialise the IO layer and register platform IO devices */
 	io_setup();
diff --git a/plat/juno/platform.h b/plat/juno/platform.h
index d032a12..1a57252 100644
--- a/plat/juno/platform.h
+++ b/plat/juno/platform.h
@@ -119,6 +119,7 @@
 #define DEVICE1_BASE		0x40000000
 #define DEVICE1_SIZE		0x40000000
 #define SOC_NIC400_BASE		0x7fd00000
+#define PCIE_CONTROL_BASE	0x7ff20000
 
 #define DRAM_BASE		0x80000000
 #define DRAM_SIZE		0x80000000