diff --git a/drivers/st/clk/stm32mp1_clkfunc.c b/drivers/st/clk/stm32mp1_clkfunc.c
index 1d92271..e176f97 100644
--- a/drivers/st/clk/stm32mp1_clkfunc.c
+++ b/drivers/st/clk/stm32mp1_clkfunc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -34,8 +34,8 @@
 /*******************************************************************************
  * This function reads the frequency of an oscillator from its name.
  * It reads the value indicated inside the device tree.
- * Returns 0 if success, and a negative value else.
- * If success, value is stored in the second parameter.
+ * Returns 0 on success, and a negative FDT/ERRNO error code on failure.
+ * On success, value is stored in the second parameter.
  ******************************************************************************/
 int fdt_osc_read_freq(const char *name, uint32_t *freq)
 {
@@ -127,7 +127,7 @@
 
 /*******************************************************************************
  * This function reads a value of a oscillator property from its id.
- * Returns value if success, and a default value if property not found.
+ * Returns value on success, and a default value if property not found.
  * Default value is passed as parameter.
  ******************************************************************************/
 uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
diff --git a/drivers/st/ddr/stm32mp1_ddr.c b/drivers/st/ddr/stm32mp1_ddr.c
index 9a50546..79aff6e 100644
--- a/drivers/st/ddr/stm32mp1_ddr.c
+++ b/drivers/st/ddr/stm32mp1_ddr.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  */
 
+#include <errno.h>
 #include <stddef.h>
 
 #include <platform_def.h>
@@ -233,40 +234,67 @@
 
 static const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = {
 	[REG_REG] = {
-		"static", ddr_reg, ARRAY_SIZE(ddr_reg), DDR_BASE
+		.name = "static",
+		.desc = ddr_reg,
+		.size = ARRAY_SIZE(ddr_reg),
+		.base = DDR_BASE
 	},
 	[REG_TIMING] = {
-		"timing", ddr_timing, ARRAY_SIZE(ddr_timing), DDR_BASE
+		.name = "timing",
+		.desc = ddr_timing,
+		.size = ARRAY_SIZE(ddr_timing),
+		.base = DDR_BASE
 	},
 	[REG_PERF] = {
-		"perf", ddr_perf, ARRAY_SIZE(ddr_perf), DDR_BASE
+		.name = "perf",
+		.desc = ddr_perf,
+		.size = ARRAY_SIZE(ddr_perf),
+		.base = DDR_BASE
 	},
 	[REG_MAP] = {
-		"map", ddr_map, ARRAY_SIZE(ddr_map), DDR_BASE
+		.name = "map",
+		.desc = ddr_map,
+		.size = ARRAY_SIZE(ddr_map),
+		.base = DDR_BASE
 	},
 	[REGPHY_REG] = {
-		"static", ddrphy_reg, ARRAY_SIZE(ddrphy_reg), DDRPHY_BASE
+		.name = "static",
+		.desc = ddrphy_reg,
+		.size = ARRAY_SIZE(ddrphy_reg),
+		.base = DDRPHY_BASE
 	},
 	[REGPHY_TIMING] = {
-		"timing", ddrphy_timing, ARRAY_SIZE(ddrphy_timing), DDRPHY_BASE
+		.name = "timing",
+		.desc = ddrphy_timing,
+		.size = ARRAY_SIZE(ddrphy_timing),
+		.base = DDRPHY_BASE
 	},
 	[REGPHY_CAL] = {
-		"cal", ddrphy_cal, ARRAY_SIZE(ddrphy_cal), DDRPHY_BASE
+		.name = "cal",
+		.desc = ddrphy_cal,
+		.size = ARRAY_SIZE(ddrphy_cal),
+		.base = DDRPHY_BASE
 	},
 	[REG_DYN] = {
-		"dyn", ddr_dyn, ARRAY_SIZE(ddr_dyn), DDR_BASE
+		.name = "dyn",
+		.desc = ddr_dyn,
+		.size = ARRAY_SIZE(ddr_dyn),
+		.base = DDR_BASE
 	},
 	[REGPHY_DYN] = {
-		"dyn", ddrphy_dyn, ARRAY_SIZE(ddrphy_dyn), DDRPHY_BASE
+		.name = "dyn",
+		.desc = ddrphy_dyn,
+		.size = ARRAY_SIZE(ddrphy_dyn),
+		.base = DDRPHY_BASE
 	},
 };
 
-static uint32_t get_base_addr(const struct ddr_info *priv, enum base_type base)
+static uintptr_t get_base_addr(const struct ddr_info *priv, enum base_type base)
 {
 	if (base == DDRPHY_BASE) {
-		return (uint32_t)priv->phy;
+		return (uintptr_t)priv->phy;
 	} else {
-		return (uint32_t)priv->ctl;
+		return (uintptr_t)priv->ctl;
 	}
 }
 
@@ -275,21 +303,22 @@
 		    const void *param)
 {
 	unsigned int i;
-	unsigned int *ptr, value;
+	unsigned int value;
 	enum base_type base = ddr_registers[type].base;
-	uint32_t base_addr = get_base_addr(priv, base);
+	uintptr_t base_addr = get_base_addr(priv, base);
 	const struct reg_desc *desc = ddr_registers[type].desc;
 
 	VERBOSE("init %s\n", ddr_registers[type].name);
 	for (i = 0; i < ddr_registers[type].size; i++) {
-		ptr = (unsigned int *)(base_addr + desc[i].offset);
+		uintptr_t ptr = base_addr + desc[i].offset;
+
 		if (desc[i].par_offset == INVALID_OFFSET) {
 			ERROR("invalid parameter offset for %s", desc[i].name);
 			panic();
 		} else {
-			value = *((uint32_t *)((uint32_t)param +
+			value = *((uint32_t *)((uintptr_t)param +
 					       desc[i].par_offset));
-			mmio_write_32((uint32_t)ptr, value);
+			mmio_write_32(ptr, value);
 		}
 	}
 }
@@ -305,15 +334,15 @@
 	time0 = start;
 
 	do {
-		pgsr = mmio_read_32((uint32_t)&phy->pgsr);
+		pgsr = mmio_read_32((uintptr_t)&phy->pgsr);
 		time = get_timer(start);
 		if (time != time0) {
-			VERBOSE("  > [0x%x] pgsr = 0x%x &\n",
-				(uint32_t)&phy->pgsr, pgsr);
-			VERBOSE("    [0x%x] pir = 0x%x (time=%x)\n",
-				(uint32_t)&phy->pir,
-				mmio_read_32((uint32_t)&phy->pir),
-				(uint32_t)time);
+			VERBOSE("  > [0x%lx] pgsr = 0x%x &\n",
+				(uintptr_t)&phy->pgsr, pgsr);
+			VERBOSE("    [0x%lx] pir = 0x%x (time=%lx)\n",
+				(uintptr_t)&phy->pir,
+				mmio_read_32((uintptr_t)&phy->pir),
+				time);
 		}
 
 		time0 = time;
@@ -341,18 +370,18 @@
 			error++;
 		}
 	} while ((pgsr & DDRPHYC_PGSR_IDONE) == 0U && error == 0);
-	VERBOSE("\n[0x%x] pgsr = 0x%x\n",
-		(uint32_t)&phy->pgsr, pgsr);
+	VERBOSE("\n[0x%lx] pgsr = 0x%x\n",
+		(uintptr_t)&phy->pgsr, pgsr);
 }
 
 static void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, uint32_t pir)
 {
 	uint32_t pir_init = pir | DDRPHYC_PIR_INIT;
 
-	mmio_write_32((uint32_t)&phy->pir, pir_init);
-	VERBOSE("[0x%x] pir = 0x%x -> 0x%x\n",
-		(uint32_t)&phy->pir, pir_init,
-		mmio_read_32((uint32_t)&phy->pir));
+	mmio_write_32((uintptr_t)&phy->pir, pir_init);
+	VERBOSE("[0x%lx] pir = 0x%x -> 0x%x\n",
+		(uintptr_t)&phy->pir, pir_init,
+		mmio_read_32((uintptr_t)&phy->pir));
 
 	/* Need to wait 10 configuration clock before start polling */
 	udelay(10);
@@ -364,9 +393,9 @@
 /* Start quasi dynamic register update */
 static void stm32mp1_start_sw_done(struct stm32mp1_ddrctl *ctl)
 {
-	mmio_clrbits_32((uint32_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
-	VERBOSE("[0x%x] swctl = 0x%x\n",
-		(uint32_t)&ctl->swctl,  mmio_read_32((uint32_t)&ctl->swctl));
+	mmio_clrbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
+	VERBOSE("[0x%lx] swctl = 0x%x\n",
+		(uintptr_t)&ctl->swctl,  mmio_read_32((uintptr_t)&ctl->swctl));
 }
 
 /* Wait quasi dynamic register update */
@@ -375,15 +404,15 @@
 	unsigned long start;
 	uint32_t swstat;
 
-	mmio_setbits_32((uint32_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
-	VERBOSE("[0x%x] swctl = 0x%x\n",
-		(uint32_t)&ctl->swctl, mmio_read_32((uint32_t)&ctl->swctl));
+	mmio_setbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
+	VERBOSE("[0x%lx] swctl = 0x%x\n",
+		(uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl));
 
 	start = get_timer(0);
 	do {
-		swstat = mmio_read_32((uint32_t)&ctl->swstat);
-		VERBOSE("[0x%x] swstat = 0x%x ",
-			(uint32_t)&ctl->swstat, swstat);
+		swstat = mmio_read_32((uintptr_t)&ctl->swstat);
+		VERBOSE("[0x%lx] swstat = 0x%x ",
+			(uintptr_t)&ctl->swstat, swstat);
 		VERBOSE("timer in ms 0x%x = start 0x%lx\r",
 			get_timer(0), start);
 		if (get_timer(start) > plat_get_syscnt_freq2()) {
@@ -391,8 +420,8 @@
 		}
 	} while ((swstat & DDRCTRL_SWSTAT_SW_DONE_ACK) == 0U);
 
-	VERBOSE("[0x%x] swstat = 0x%x\n",
-		(uint32_t)&ctl->swstat, swstat);
+	VERBOSE("[0x%lx] swstat = 0x%x\n",
+		(uintptr_t)&ctl->swstat, swstat);
 }
 
 /* Wait quasi dynamic register update */
@@ -406,11 +435,11 @@
 
 	start = get_timer(0);
 	for ( ; ; ) {
-		stat = mmio_read_32((uint32_t)&priv->ctl->stat);
+		stat = mmio_read_32((uintptr_t)&priv->ctl->stat);
 		operating_mode = stat & DDRCTRL_STAT_OPERATING_MODE_MASK;
 		selref_type = stat & DDRCTRL_STAT_SELFREF_TYPE_MASK;
-		VERBOSE("[0x%x] stat = 0x%x\n",
-			(uint32_t)&priv->ctl->stat, stat);
+		VERBOSE("[0x%lx] stat = 0x%x\n",
+			(uintptr_t)&priv->ctl->stat, stat);
 		VERBOSE("timer in ms 0x%x = start 0x%lx\r",
 			get_timer(0), start);
 		if (get_timer(start) > plat_get_syscnt_freq2()) {
@@ -441,8 +470,8 @@
 		}
 	}
 
-	VERBOSE("[0x%x] stat = 0x%x\n",
-		(uint32_t)&priv->ctl->stat, stat);
+	VERBOSE("[0x%lx] stat = 0x%x\n",
+		(uintptr_t)&priv->ctl->stat, stat);
 }
 
 /* Mode Register Writes (MRW or MRS) */
@@ -459,7 +488,7 @@
 	 *    No write should be performed to MRCTRL0 and MRCTRL1
 	 *    if MRSTAT.mr_wr_busy = 1.
 	 */
-	while ((mmio_read_32((uint32_t)&priv->ctl->mrstat) &
+	while ((mmio_read_32((uintptr_t)&priv->ctl->mrstat) &
 		DDRCTRL_MRSTAT_MR_WR_BUSY) != 0U) {
 		;
 	}
@@ -472,14 +501,14 @@
 		  DDRCTRL_MRCTRL0_MR_RANK_ALL |
 		  (((uint32_t)addr << DDRCTRL_MRCTRL0_MR_ADDR_SHIFT) &
 		   DDRCTRL_MRCTRL0_MR_ADDR_MASK);
-	mmio_write_32((uint32_t)&priv->ctl->mrctrl0, mrctrl0);
-	VERBOSE("[0x%x] mrctrl0 = 0x%x (0x%x)\n",
-		(uint32_t)&priv->ctl->mrctrl0,
-		mmio_read_32((uint32_t)&priv->ctl->mrctrl0), mrctrl0);
-	mmio_write_32((uint32_t)&priv->ctl->mrctrl1, data);
-	VERBOSE("[0x%x] mrctrl1 = 0x%x\n",
-		(uint32_t)&priv->ctl->mrctrl1,
-		mmio_read_32((uint32_t)&priv->ctl->mrctrl1));
+	mmio_write_32((uintptr_t)&priv->ctl->mrctrl0, mrctrl0);
+	VERBOSE("[0x%lx] mrctrl0 = 0x%x (0x%x)\n",
+		(uintptr_t)&priv->ctl->mrctrl0,
+		mmio_read_32((uintptr_t)&priv->ctl->mrctrl0), mrctrl0);
+	mmio_write_32((uintptr_t)&priv->ctl->mrctrl1, data);
+	VERBOSE("[0x%lx] mrctrl1 = 0x%x\n",
+		(uintptr_t)&priv->ctl->mrctrl1,
+		mmio_read_32((uintptr_t)&priv->ctl->mrctrl1));
 
 	/*
 	 * 3. In a separate APB transaction, write the MRCTRL0.mr_wr to 1. This
@@ -489,22 +518,22 @@
 	 *    initiated until it is deasserted.
 	 */
 	mrctrl0 |= DDRCTRL_MRCTRL0_MR_WR;
-	mmio_write_32((uint32_t)&priv->ctl->mrctrl0, mrctrl0);
+	mmio_write_32((uintptr_t)&priv->ctl->mrctrl0, mrctrl0);
 
-	while ((mmio_read_32((uint32_t)&priv->ctl->mrstat) &
+	while ((mmio_read_32((uintptr_t)&priv->ctl->mrstat) &
 	       DDRCTRL_MRSTAT_MR_WR_BUSY) != 0U) {
 		;
 	}
 
-	VERBOSE("[0x%x] mrctrl0 = 0x%x\n",
-		(uint32_t)&priv->ctl->mrctrl0, mrctrl0);
+	VERBOSE("[0x%lx] mrctrl0 = 0x%x\n",
+		(uintptr_t)&priv->ctl->mrctrl0, mrctrl0);
 }
 
 /* Switch DDR3 from DLL-on to DLL-off */
 static void stm32mp1_ddr3_dll_off(struct ddr_info *priv)
 {
-	uint32_t mr1 = mmio_read_32((uint32_t)&priv->phy->mr1);
-	uint32_t mr2 = mmio_read_32((uint32_t)&priv->phy->mr2);
+	uint32_t mr1 = mmio_read_32((uintptr_t)&priv->phy->mr1);
+	uint32_t mr2 = mmio_read_32((uintptr_t)&priv->phy->mr2);
 	uint32_t dbgcam;
 
 	VERBOSE("mr1: 0x%x\n", mr1);
@@ -514,10 +543,10 @@
 	 * 1. Set the DBG1.dis_hif = 1.
 	 *    This prevents further reads/writes being received on the HIF.
 	 */
-	mmio_setbits_32((uint32_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF);
-	VERBOSE("[0x%x] dbg1 = 0x%x\n",
-		(uint32_t)&priv->ctl->dbg1,
-		mmio_read_32((uint32_t)&priv->ctl->dbg1));
+	mmio_setbits_32((uintptr_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF);
+	VERBOSE("[0x%lx] dbg1 = 0x%x\n",
+		(uintptr_t)&priv->ctl->dbg1,
+		mmio_read_32((uintptr_t)&priv->ctl->dbg1));
 
 	/*
 	 * 2. Ensure all commands have been flushed from the uMCTL2 by polling
@@ -528,9 +557,9 @@
 	 *    DBGCAM.dbg_hpr_q_depth = 0.
 	 */
 	do {
-		dbgcam = mmio_read_32((uint32_t)&priv->ctl->dbgcam);
-		VERBOSE("[0x%x] dbgcam = 0x%x\n",
-			(uint32_t)&priv->ctl->dbgcam, dbgcam);
+		dbgcam = mmio_read_32((uintptr_t)&priv->ctl->dbgcam);
+		VERBOSE("[0x%lx] dbgcam = 0x%x\n",
+			(uintptr_t)&priv->ctl->dbgcam, dbgcam);
 	} while ((((dbgcam & DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY) ==
 		   DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY)) &&
 		 ((dbgcam & DDRCTRL_DBGCAM_DBG_Q_DEPTH) == 0U));
@@ -574,11 +603,11 @@
 	 *    PWRCTL.selfref_sw = 1, and polling STAT.operating_mode to ensure
 	 *    the DDRC has entered self-refresh.
 	 */
-	mmio_setbits_32((uint32_t)&priv->ctl->pwrctl,
+	mmio_setbits_32((uintptr_t)&priv->ctl->pwrctl,
 			DDRCTRL_PWRCTL_SELFREF_SW);
-	VERBOSE("[0x%x] pwrctl = 0x%x\n",
-		(uint32_t)&priv->ctl->pwrctl,
-		mmio_read_32((uint32_t)&priv->ctl->pwrctl));
+	VERBOSE("[0x%lx] pwrctl = 0x%x\n",
+		(uintptr_t)&priv->ctl->pwrctl,
+		mmio_read_32((uintptr_t)&priv->ctl->pwrctl));
 
 	/*
 	 * 8. Wait until STAT.operating_mode[1:0]==11 indicating that the
@@ -594,10 +623,10 @@
 	 */
 	stm32mp1_start_sw_done(priv->ctl);
 
-	mmio_setbits_32((uint32_t)&priv->ctl->mstr, DDRCTRL_MSTR_DLL_OFF_MODE);
-	VERBOSE("[0x%x] mstr = 0x%x\n",
-		(uint32_t)&priv->ctl->mstr,
-		mmio_read_32((uint32_t)&priv->ctl->mstr));
+	mmio_setbits_32((uintptr_t)&priv->ctl->mstr, DDRCTRL_MSTR_DLL_OFF_MODE);
+	VERBOSE("[0x%lx] mstr = 0x%x\n",
+		(uintptr_t)&priv->ctl->mstr,
+		mmio_read_32((uintptr_t)&priv->ctl->mstr));
 
 	stm32mp1_wait_sw_done_ack(priv->ctl);
 
@@ -611,26 +640,26 @@
 
 	/* Change Bypass Mode Frequency Range */
 	if (stm32mp1_clk_get_rate(DDRPHYC) < 100000000U) {
-		mmio_clrbits_32((uint32_t)&priv->phy->dllgcr,
+		mmio_clrbits_32((uintptr_t)&priv->phy->dllgcr,
 				DDRPHYC_DLLGCR_BPS200);
 	} else {
-		mmio_setbits_32((uint32_t)&priv->phy->dllgcr,
+		mmio_setbits_32((uintptr_t)&priv->phy->dllgcr,
 				DDRPHYC_DLLGCR_BPS200);
 	}
 
-	mmio_setbits_32((uint32_t)&priv->phy->acdllcr, DDRPHYC_ACDLLCR_DLLDIS);
+	mmio_setbits_32((uintptr_t)&priv->phy->acdllcr, DDRPHYC_ACDLLCR_DLLDIS);
 
-	mmio_setbits_32((uint32_t)&priv->phy->dx0dllcr,
+	mmio_setbits_32((uintptr_t)&priv->phy->dx0dllcr,
 			DDRPHYC_DXNDLLCR_DLLDIS);
-	mmio_setbits_32((uint32_t)&priv->phy->dx1dllcr,
+	mmio_setbits_32((uintptr_t)&priv->phy->dx1dllcr,
 			DDRPHYC_DXNDLLCR_DLLDIS);
-	mmio_setbits_32((uint32_t)&priv->phy->dx2dllcr,
+	mmio_setbits_32((uintptr_t)&priv->phy->dx2dllcr,
 			DDRPHYC_DXNDLLCR_DLLDIS);
-	mmio_setbits_32((uint32_t)&priv->phy->dx3dllcr,
+	mmio_setbits_32((uintptr_t)&priv->phy->dx3dllcr,
 			DDRPHYC_DXNDLLCR_DLLDIS);
 
 	/* 12. Exit the self-refresh state by setting PWRCTL.selfref_sw = 0. */
-	mmio_clrbits_32((uint32_t)&priv->ctl->pwrctl,
+	mmio_clrbits_32((uintptr_t)&priv->ctl->pwrctl,
 			DDRCTRL_PWRCTL_SELFREF_SW);
 	stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
 
@@ -646,20 +675,20 @@
 	 */
 
 	/* 15. Write DBG1.dis_hif = 0 to re-enable reads and writes. */
-	mmio_clrbits_32((uint32_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF);
-	VERBOSE("[0x%x] dbg1 = 0x%x\n",
-		(uint32_t)&priv->ctl->dbg1,
-		mmio_read_32((uint32_t)&priv->ctl->dbg1));
+	mmio_clrbits_32((uintptr_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF);
+	VERBOSE("[0x%lx] dbg1 = 0x%x\n",
+		(uintptr_t)&priv->ctl->dbg1,
+		mmio_read_32((uintptr_t)&priv->ctl->dbg1));
 }
 
 static void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
 {
 	stm32mp1_start_sw_done(ctl);
 	/* Quasi-dynamic register update*/
-	mmio_setbits_32((uint32_t)&ctl->rfshctl3,
+	mmio_setbits_32((uintptr_t)&ctl->rfshctl3,
 			DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
-	mmio_clrbits_32((uint32_t)&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
-	mmio_clrbits_32((uint32_t)&ctl->dfimisc,
+	mmio_clrbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
+	mmio_clrbits_32((uintptr_t)&ctl->dfimisc,
 			DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
 	stm32mp1_wait_sw_done_ack(ctl);
 }
@@ -669,14 +698,14 @@
 {
 	stm32mp1_start_sw_done(ctl);
 	if ((rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH) == 0U) {
-		mmio_clrbits_32((uint32_t)&ctl->rfshctl3,
+		mmio_clrbits_32((uintptr_t)&ctl->rfshctl3,
 				DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
 	}
 	if ((pwrctl & DDRCTRL_PWRCTL_POWERDOWN_EN) != 0U) {
-		mmio_setbits_32((uint32_t)&ctl->pwrctl,
+		mmio_setbits_32((uintptr_t)&ctl->pwrctl,
 				DDRCTRL_PWRCTL_POWERDOWN_EN);
 	}
-	mmio_setbits_32((uint32_t)&ctl->dfimisc,
+	mmio_setbits_32((uintptr_t)&ctl->dfimisc,
 			DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
 	stm32mp1_wait_sw_done_ack(ctl);
 }
@@ -694,12 +723,14 @@
 		       struct stm32mp1_ddr_config *config)
 {
 	uint32_t pir;
-	int ret;
+	int ret = -EINVAL;
 
 	if ((config->c_reg.mstr & DDRCTRL_MSTR_DDR3) != 0U) {
 		ret = board_ddr_power_init(STM32MP_DDR3);
-	} else {
+	} else if ((config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2) != 0U) {
 		ret = board_ddr_power_init(STM32MP_LPDDR2);
+	} else {
+		ERROR("DDR type not supported\n");
 	}
 
 	if (ret != 0) {
@@ -746,11 +777,11 @@
 
 	/* 1.5. initialize registers ddr_umctl2 */
 	/* Stop uMCTL2 before PHY is ready */
-	mmio_clrbits_32((uint32_t)&priv->ctl->dfimisc,
+	mmio_clrbits_32((uintptr_t)&priv->ctl->dfimisc,
 			DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
-	VERBOSE("[0x%x] dfimisc = 0x%x\n",
-		(uint32_t)&priv->ctl->dfimisc,
-		mmio_read_32((uint32_t)&priv->ctl->dfimisc));
+	VERBOSE("[0x%lx] dfimisc = 0x%x\n",
+		(uintptr_t)&priv->ctl->dfimisc,
+		mmio_read_32((uintptr_t)&priv->ctl->dfimisc));
 
 	set_reg(priv, REG_REG, &config->c_reg);
 
@@ -759,23 +790,23 @@
 	     (DDRCTRL_MSTR_DDR3 | DDRCTRL_MSTR_DLL_OFF_MODE))
 	    == (DDRCTRL_MSTR_DDR3 | DDRCTRL_MSTR_DLL_OFF_MODE)) {
 		VERBOSE("deactivate DLL OFF in mstr\n");
-		mmio_clrbits_32((uint32_t)&priv->ctl->mstr,
+		mmio_clrbits_32((uintptr_t)&priv->ctl->mstr,
 				DDRCTRL_MSTR_DLL_OFF_MODE);
-		VERBOSE("[0x%x] mstr = 0x%x\n",
-			(uint32_t)&priv->ctl->mstr,
-			mmio_read_32((uint32_t)&priv->ctl->mstr));
+		VERBOSE("[0x%lx] mstr = 0x%x\n",
+			(uintptr_t)&priv->ctl->mstr,
+			mmio_read_32((uintptr_t)&priv->ctl->mstr));
 	}
 
 	set_reg(priv, REG_TIMING, &config->c_timing);
 	set_reg(priv, REG_MAP, &config->c_map);
 
 	/* Skip CTRL init, SDRAM init is done by PHY PUBL */
-	mmio_clrsetbits_32((uint32_t)&priv->ctl->init0,
+	mmio_clrsetbits_32((uintptr_t)&priv->ctl->init0,
 			   DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK,
 			   DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL);
-	VERBOSE("[0x%x] init0 = 0x%x\n",
-		(uint32_t)&priv->ctl->init0,
-		mmio_read_32((uint32_t)&priv->ctl->init0));
+	VERBOSE("[0x%lx] init0 = 0x%x\n",
+		(uintptr_t)&priv->ctl->init0,
+		mmio_read_32((uintptr_t)&priv->ctl->init0));
 
 	set_reg(priv, REG_PERF, &config->c_perf);
 
@@ -797,10 +828,10 @@
 	     (DDRCTRL_MSTR_DDR3 | DDRCTRL_MSTR_DLL_OFF_MODE))
 	    == (DDRCTRL_MSTR_DDR3 | DDRCTRL_MSTR_DLL_OFF_MODE)) {
 		VERBOSE("deactivate DLL OFF in mr1\n");
-		mmio_clrbits_32((uint32_t)&priv->phy->mr1, BIT(0));
-		VERBOSE("[0x%x] mr1 = 0x%x\n",
-			(uint32_t)&priv->phy->mr1,
-			mmio_read_32((uint32_t)&priv->phy->mr1));
+		mmio_clrbits_32((uintptr_t)&priv->phy->mr1, BIT(0));
+		VERBOSE("[0x%lx] mr1 = 0x%x\n",
+			(uintptr_t)&priv->phy->mr1,
+			mmio_read_32((uintptr_t)&priv->phy->mr1));
 	}
 
 	/*
@@ -830,11 +861,11 @@
 	 */
 	stm32mp1_start_sw_done(priv->ctl);
 
-	mmio_setbits_32((uint32_t)&priv->ctl->dfimisc,
+	mmio_setbits_32((uintptr_t)&priv->ctl->dfimisc,
 			DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
-	VERBOSE("[0x%x] dfimisc = 0x%x\n",
-		(uint32_t)&priv->ctl->dfimisc,
-		mmio_read_32((uint32_t)&priv->ctl->dfimisc));
+	VERBOSE("[0x%lx] dfimisc = 0x%x\n",
+		(uintptr_t)&priv->ctl->dfimisc,
+		mmio_read_32((uintptr_t)&priv->ctl->dfimisc));
 
 	stm32mp1_wait_sw_done_ack(priv->ctl);
 
@@ -884,14 +915,16 @@
 				 config->c_reg.pwrctl);
 
 	/* Enable uMCTL2 AXI port 0 */
-	mmio_setbits_32((uint32_t)&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
-	VERBOSE("[0x%x] pctrl_0 = 0x%x\n",
-		(uint32_t)&priv->ctl->pctrl_0,
-		mmio_read_32((uint32_t)&priv->ctl->pctrl_0));
+	mmio_setbits_32((uintptr_t)&priv->ctl->pctrl_0,
+			DDRCTRL_PCTRL_N_PORT_EN);
+	VERBOSE("[0x%lx] pctrl_0 = 0x%x\n",
+		(uintptr_t)&priv->ctl->pctrl_0,
+		mmio_read_32((uintptr_t)&priv->ctl->pctrl_0));
 
 	/* Enable uMCTL2 AXI port 1 */
-	mmio_setbits_32((uint32_t)&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);
-	VERBOSE("[0x%x] pctrl_1 = 0x%x\n",
-		(uint32_t)&priv->ctl->pctrl_1,
-		mmio_read_32((uint32_t)&priv->ctl->pctrl_1));
+	mmio_setbits_32((uintptr_t)&priv->ctl->pctrl_1,
+			DDRCTRL_PCTRL_N_PORT_EN);
+	VERBOSE("[0x%lx] pctrl_1 = 0x%x\n",
+		(uintptr_t)&priv->ctl->pctrl_1,
+		mmio_read_32((uintptr_t)&priv->ctl->pctrl_1));
 }
diff --git a/drivers/st/ddr/stm32mp1_ram.c b/drivers/st/ddr/stm32mp1_ram.c
index ddfc4a7..e65fbea 100644
--- a/drivers/st/ddr/stm32mp1_ram.c
+++ b/drivers/st/ddr/stm32mp1_ram.c
@@ -266,8 +266,8 @@
 	VERBOSE("%s : ram size(%x, %x)\n", __func__,
 		(uint32_t)priv->info.base, (uint32_t)priv->info.size);
 
-	dcsw_op_all(DC_OP_CISW);
 	write_sctlr(read_sctlr() & ~SCTLR_C_BIT);
+	dcsw_op_all(DC_OP_CISW);
 
 	uret = ddr_test_data_bus();
 	if (uret != 0U) {
diff --git a/drivers/st/gpio/stm32_gpio.c b/drivers/st/gpio/stm32_gpio.c
index 9591e37..bbee138 100644
--- a/drivers/st/gpio/stm32_gpio.c
+++ b/drivers/st/gpio/stm32_gpio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -29,59 +29,60 @@
 void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
 	      uint32_t pull, uint32_t alternate)
 {
-	volatile uint32_t bank_address;
+	uintptr_t base;
 
 	if (!check_gpio(bank, pin)) {
 		return;
 	}
 
 	if (bank == GPIO_BANK_Z) {
-		bank_address = STM32_GPIOZ_BANK;
+		base = STM32_GPIOZ_BANK;
 	} else {
-		bank_address = STM32_GPIOA_BANK +
+		base = STM32_GPIOA_BANK +
 			(bank * STM32_GPIO_BANK_OFFSET);
 	}
 
-	mmio_clrbits_32(bank_address + GPIO_MODE_OFFSET,
+	mmio_clrbits_32(base + GPIO_MODE_OFFSET,
 			((uint32_t)GPIO_MODE_MASK << (pin << 1)));
-	mmio_setbits_32(bank_address + GPIO_MODE_OFFSET,
+	mmio_setbits_32(base + GPIO_MODE_OFFSET,
 			(mode & ~GPIO_OPEN_DRAIN) << (pin << 1));
 
 	if ((mode & GPIO_OPEN_DRAIN) != 0U) {
-		mmio_setbits_32(bank_address + GPIO_TYPE_OFFSET,
-				BIT(pin));
+		mmio_setbits_32(base + GPIO_TYPE_OFFSET, BIT(pin));
+	} else {
+		mmio_clrbits_32(base + GPIO_TYPE_OFFSET, BIT(pin));
 	}
 
-	mmio_clrbits_32(bank_address + GPIO_SPEED_OFFSET,
+	mmio_clrbits_32(base + GPIO_SPEED_OFFSET,
 			((uint32_t)GPIO_SPEED_MASK << (pin << 1)));
-	mmio_setbits_32(bank_address + GPIO_SPEED_OFFSET, speed << (pin << 1));
+	mmio_setbits_32(base + GPIO_SPEED_OFFSET, speed << (pin << 1));
 
-	mmio_clrbits_32(bank_address + GPIO_PUPD_OFFSET,
+	mmio_clrbits_32(base + GPIO_PUPD_OFFSET,
 			((uint32_t)GPIO_PULL_MASK << (pin << 1)));
-	mmio_setbits_32(bank_address + GPIO_PUPD_OFFSET, pull << (pin << 1));
+	mmio_setbits_32(base + GPIO_PUPD_OFFSET, pull << (pin << 1));
 
 	if (pin < GPIO_ALT_LOWER_LIMIT) {
-		mmio_clrbits_32(bank_address + GPIO_AFRL_OFFSET,
+		mmio_clrbits_32(base + GPIO_AFRL_OFFSET,
 				((uint32_t)GPIO_ALTERNATE_MASK << (pin << 2)));
-		mmio_setbits_32(bank_address + GPIO_AFRL_OFFSET,
+		mmio_setbits_32(base + GPIO_AFRL_OFFSET,
 				alternate << (pin << 2));
 	} else {
-		mmio_clrbits_32(bank_address + GPIO_AFRH_OFFSET,
+		mmio_clrbits_32(base + GPIO_AFRH_OFFSET,
 				((uint32_t)GPIO_ALTERNATE_MASK <<
 				 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)));
-		mmio_setbits_32(bank_address + GPIO_AFRH_OFFSET,
+		mmio_setbits_32(base + GPIO_AFRH_OFFSET,
 				alternate << ((pin - GPIO_ALT_LOWER_LIMIT) <<
 					      2));
 	}
 
 	VERBOSE("GPIO %u mode set to 0x%x\n", bank,
-		mmio_read_32(bank_address + GPIO_MODE_OFFSET));
+		mmio_read_32(base + GPIO_MODE_OFFSET));
 	VERBOSE("GPIO %u speed set to 0x%x\n", bank,
-		mmio_read_32(bank_address + GPIO_SPEED_OFFSET));
+		mmio_read_32(base + GPIO_SPEED_OFFSET));
 	VERBOSE("GPIO %u mode pull to 0x%x\n", bank,
-		mmio_read_32(bank_address + GPIO_PUPD_OFFSET));
+		mmio_read_32(base + GPIO_PUPD_OFFSET));
 	VERBOSE("GPIO %u mode alternate low to 0x%x\n", bank,
-		mmio_read_32(bank_address + GPIO_AFRL_OFFSET));
+		mmio_read_32(base + GPIO_AFRL_OFFSET));
 	VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank,
-		mmio_read_32(bank_address + GPIO_AFRH_OFFSET));
+		mmio_read_32(base + GPIO_AFRH_OFFSET));
 }
diff --git a/drivers/st/io/io_stm32image.c b/drivers/st/io/io_stm32image.c
index 0164a2d..dc2977d 100644
--- a/drivers/st/io/io_stm32image.c
+++ b/drivers/st/io/io_stm32image.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -94,6 +94,8 @@
 	for (i = 0; i < STM32_PART_NUM; i++) {
 		memcpy(stm32image_dev.part_info[i].name,
 		       device_info->part_info[i].name, MAX_PART_NAME_SIZE);
+		stm32image_dev.part_info[i].binary_type =
+			device_info->part_info[i].binary_type;
 		stm32image_dev.part_info[i].part_offset =
 			device_info->part_info[i].part_offset;
 		stm32image_dev.part_info[i].bkp_offset =
@@ -193,21 +195,29 @@
 		result = io_read(backend_handle, (uintptr_t)header,
 				 MAX_LBA_SIZE, (size_t *)&bytes_read);
 		if (result != 0) {
-			ERROR("%s: io_read (%i)\n", __func__, result);
-			break;
+			if (current_part->bkp_offset == 0U) {
+				ERROR("%s: io_read (%i)\n", __func__, result);
+			}
+			header->magic = 0;
 		}
 
 		if ((header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) ||
 		    (header->binary_type != current_part->binary_type) ||
 		    (header->image_length >= stm32image_dev.device_size)) {
-			WARN("%s: partition %s wrong header\n",
-			     __func__, current_part->name);
+			VERBOSE("%s: partition %s not found at %x\n",
+				__func__, current_part->name, *stm32_img);
+
+			if (current_part->bkp_offset == 0U) {
+				result = -ENOMEM;
+				break;
+			}
 
 			/* Header not correct, check next offset for backup */
 			*stm32_img += current_part->bkp_offset;
 			if (*stm32_img > stm32image_dev.device_size) {
 				/* No backup found, end of device reached */
-				WARN("Out of memory\n");
+				WARN("%s : partition %s not found\n",
+				     __func__, current_part->name);
 				result = -ENOMEM;
 				break;
 			}
@@ -221,9 +231,13 @@
 		return result;
 	}
 
-	*length = header->image_length;
+	if (header->image_length < stm32image_dev.lba_size) {
+		*length = stm32image_dev.lba_size;
+	} else {
+		*length = header->image_length;
+	}
 
-	INFO("STM32 Image size : %i\n", *length);
+	INFO("STM32 Image size : %lu\n", (unsigned long)*length);
 
 	return 0;
 }
@@ -266,11 +280,10 @@
 static int stm32image_partition_read(io_entity_t *entity, uintptr_t buffer,
 				     size_t length, size_t *length_read)
 {
-	int result = 0, offset, local_length = 0;
+	int result = 0;
 	uint8_t *local_buffer = (uint8_t *)buffer;
 	boot_api_image_header_t *header =
 		(boot_api_image_header_t *)first_lba_buffer;
-	uintptr_t backend_handle;
 
 	assert(entity != NULL);
 	assert(buffer != 0U);
@@ -279,8 +292,17 @@
 	*length_read = 0U;
 
 	while (*length_read == 0U) {
+		int offset;
+		int local_length;
+		uintptr_t backend_handle;
+
 		if (header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) {
 			/* Check for backup as image is corrupted */
+			if (current_part->bkp_offset == 0U) {
+				result = -ENOMEM;
+				break;
+			}
+
 			*stm32_img += current_part->bkp_offset;
 			if (*stm32_img >= stm32image_dev.device_size) {
 				/* End of device reached */
@@ -342,8 +364,8 @@
 		if (result != 0) {
 			ERROR("%s: io_read (%i)\n", __func__, result);
 			*length_read = 0;
-			io_close(backend_handle);
-			break;
+			header->magic = 0;
+			continue;
 		}
 
 		result = check_header(header, buffer);
@@ -351,8 +373,6 @@
 			ERROR("Header check failed\n");
 			*length_read = 0;
 			header->magic = 0;
-			io_close(backend_handle);
-			break;
 		}
 
 		io_close(backend_handle);
diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c
index 7445d88..453455c 100644
--- a/drivers/st/mmc/stm32_sdmmc2.c
+++ b/drivers/st/mmc/stm32_sdmmc2.c
@@ -470,12 +470,11 @@
 	}
 
 	/* Prepare CMD 16*/
-	mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX);
+	mmio_write_32(base + SDMMC_DTIMER, 0);
 
 	mmio_write_32(base + SDMMC_DLENR, 0);
 
-	mmio_clrsetbits_32(base + SDMMC_DCTRLR,
-			   SDMMC_DCTRLR_CLEAR_MASK, SDMMC_DCTRLR_DTDIR);
+	mmio_write_32(base + SDMMC_DCTRLR, 0);
 
 	zeromem(&cmd, sizeof(struct mmc_cmd));
 
diff --git a/include/drivers/st/stm32_gpio.h b/include/drivers/st/stm32_gpio.h
index acd95ec..4fb27e0 100644
--- a/include/drivers/st/stm32_gpio.h
+++ b/include/drivers/st/stm32_gpio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2015-2019, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -82,8 +82,8 @@
 
 #define GPIO_SPEED_LOW		0x00
 #define GPIO_SPEED_MEDIUM	0x01
-#define GPIO_SPEED_FAST		0x02
-#define GPIO_SPEED_HIGH		0x03
+#define GPIO_SPEED_HIGH		0x02
+#define GPIO_SPEED_VERY_HIGH	0x03
 #define GPIO_SPEED_MASK		U(0x03)
 
 #define GPIO_NO_PULL		0x00
diff --git a/include/drivers/st/stm32mp1_ddr_regs.h b/include/drivers/st/stm32mp1_ddr_regs.h
index bfcd5e2..342239a 100644
--- a/include/drivers/st/stm32mp1_ddr_regs.h
+++ b/include/drivers/st/stm32mp1_ddr_regs.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  */
@@ -247,11 +247,14 @@
 #define DDRCTRL_DBGSTAT				0x310
 #define DDRCTRL_SWCTL				0x320
 #define DDRCTRL_SWSTAT				0x324
+#define DDRCTRL_PSTAT				0x3FC
 #define DDRCTRL_PCTRL_0				0x490
 #define DDRCTRL_PCTRL_1				0x540
 
 /* DDR Controller Register fields */
 #define DDRCTRL_MSTR_DDR3			BIT(0)
+#define DDRCTRL_MSTR_LPDDR2			BIT(2)
+#define DDRCTRL_MSTR_LPDDR3			BIT(3)
 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK	GENMASK(13, 12)
 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL	0
 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF	BIT(12)
@@ -269,7 +272,7 @@
 /* Only one rank supported */
 #define DDRCTRL_MRCTRL0_MR_RANK_SHIFT		4
 #define DDRCTRL_MRCTRL0_MR_RANK_ALL \
-		(0x1U << DDRCTRL_MRCTRL0_MR_RANK_SHIFT)
+					BIT(DDRCTRL_MRCTRL0_MR_RANK_SHIFT)
 #define DDRCTRL_MRCTRL0_MR_ADDR_SHIFT		12
 #define DDRCTRL_MRCTRL0_MR_ADDR_MASK		GENMASK(15, 12)
 #define DDRCTRL_MRCTRL0_MR_WR			BIT(31)
@@ -367,6 +370,7 @@
 
 #define DDRPHYC_DLLGCR_BPS200			BIT(23)
 
+#define DDRPHYC_ACDLLCR_DLLSRST			BIT(30)
 #define DDRPHYC_ACDLLCR_DLLDIS			BIT(31)
 
 #define DDRPHYC_PTR0_TDLLSRST_OFFSET		0
diff --git a/include/drivers/st/stm32mp1_rcc.h b/include/drivers/st/stm32mp1_rcc.h
index fd406c5..2f29e84 100644
--- a/include/drivers/st/stm32mp1_rcc.h
+++ b/include/drivers/st/stm32mp1_rcc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2015-2019, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -68,6 +68,14 @@
 #define RCC_MP_AHB6ENCLRR		U(0x21C)
 #define RCC_MP_TZAHB6ENSETR		U(0x220)
 #define RCC_MP_TZAHB6ENCLRR		U(0x224)
+#define RCC_MC_APB4ENSETR		U(0x280)
+#define RCC_MC_APB4ENCLRR		U(0x284)
+#define RCC_MC_APB5ENSETR		U(0x288)
+#define RCC_MC_APB5ENCLRR		U(0x28C)
+#define RCC_MC_AHB5ENSETR		U(0x290)
+#define RCC_MC_AHB5ENCLRR		U(0x294)
+#define RCC_MC_AHB6ENSETR		U(0x298)
+#define RCC_MC_AHB6ENCLRR		U(0x29C)
 #define RCC_MP_APB4LPENSETR		U(0x300)
 #define RCC_MP_APB4LPENCLRR		U(0x304)
 #define RCC_MP_APB5LPENSETR		U(0x308)
@@ -78,6 +86,14 @@
 #define RCC_MP_AHB6LPENCLRR		U(0x31C)
 #define RCC_MP_TZAHB6LPENSETR		U(0x320)
 #define RCC_MP_TZAHB6LPENCLRR		U(0x324)
+#define RCC_MC_APB4LPENSETR		U(0x380)
+#define RCC_MC_APB4LPENCLRR		U(0x384)
+#define RCC_MC_APB5LPENSETR		U(0x388)
+#define RCC_MC_APB5LPENCLRR		U(0x38C)
+#define RCC_MC_AHB5LPENSETR		U(0x390)
+#define RCC_MC_AHB5LPENCLRR		U(0x394)
+#define RCC_MC_AHB6LPENSETR		U(0x398)
+#define RCC_MC_AHB6LPENCLRR		U(0x39C)
 #define RCC_BR_RSTSCLRR			U(0x400)
 #define RCC_MP_GRSTCSETR		U(0x404)
 #define RCC_MP_RSTSCLRR			U(0x408)
@@ -162,6 +178,22 @@
 #define RCC_MP_AHB4ENCLRR		U(0xA2C)
 #define RCC_MP_MLAHBENSETR		U(0xA38)
 #define RCC_MP_MLAHBENCLRR		U(0xA3C)
+#define RCC_MC_APB1ENSETR		U(0xA80)
+#define RCC_MC_APB1ENCLRR		U(0xA84)
+#define RCC_MC_APB2ENSETR		U(0xA88)
+#define RCC_MC_APB2ENCLRR		U(0xA8C)
+#define RCC_MC_APB3ENSETR		U(0xA90)
+#define RCC_MC_APB3ENCLRR		U(0xA94)
+#define RCC_MC_AHB2ENSETR		U(0xA98)
+#define RCC_MC_AHB2ENCLRR		U(0xA9C)
+#define RCC_MC_AHB3ENSETR		U(0xAA0)
+#define RCC_MC_AHB3ENCLRR		U(0xAA4)
+#define RCC_MC_AHB4ENSETR		U(0xAA8)
+#define RCC_MC_AHB4ENCLRR		U(0xAAC)
+#define RCC_MC_AXIMENSETR		U(0xAB0)
+#define RCC_MC_AXIMENCLRR		U(0xAB4)
+#define RCC_MC_MLAHBENSETR		U(0xAB8)
+#define RCC_MC_MLAHBENCLRR		U(0xABC)
 #define RCC_MP_APB1LPENSETR		U(0xB00)
 #define RCC_MP_APB1LPENCLRR		U(0xB04)
 #define RCC_MP_APB2LPENSETR		U(0xB08)
@@ -178,10 +210,31 @@
 #define RCC_MP_AXIMLPENCLRR		U(0xB34)
 #define RCC_MP_MLAHBLPENSETR		U(0xB38)
 #define RCC_MP_MLAHBLPENCLRR		U(0xB3C)
+#define RCC_MC_APB1LPENSETR		U(0xB80)
+#define RCC_MC_APB1LPENCLRR		U(0xB84)
+#define RCC_MC_APB2LPENSETR		U(0xB88)
+#define RCC_MC_APB2LPENCLRR		U(0xB8C)
+#define RCC_MC_APB3LPENSETR		U(0xB90)
+#define RCC_MC_APB3LPENCLRR		U(0xB94)
+#define RCC_MC_AHB2LPENSETR		U(0xB98)
+#define RCC_MC_AHB2LPENCLRR		U(0xB9C)
+#define RCC_MC_AHB3LPENSETR		U(0xBA0)
+#define RCC_MC_AHB3LPENCLRR		U(0xBA4)
+#define RCC_MC_AHB4LPENSETR		U(0xBA8)
+#define RCC_MC_AHB4LPENCLRR		U(0xBAC)
+#define RCC_MC_AXIMLPENSETR		U(0xBB0)
+#define RCC_MC_AXIMLPENCLRR		U(0xBB4)
+#define RCC_MC_MLAHBLPENSETR		U(0xBB8)
+#define RCC_MC_MLAHBLPENCLRR		U(0xBBC)
+#define RCC_MC_RSTSCLRR			U(0xC00)
+#define RCC_MC_CIER			U(0xC14)
+#define RCC_MC_CIFR			U(0xC18)
 #define RCC_VERR			U(0xFF4)
 #define RCC_IDR				U(0xFF8)
 #define RCC_SIDR			U(0xFFC)
 
+#define RCC_OFFSET_MASK			GENMASK(11, 0)
+
 /* Values for RCC_TZCR register */
 #define RCC_TZCR_TZEN			BIT(0)
 
@@ -221,6 +274,9 @@
 #define RCC_MPUDIV_MASK			GENMASK(2, 0)
 #define RCC_AXIDIV_MASK			GENMASK(2, 0)
 
+/* Used for TIMER Prescaler */
+#define RCC_TIMGXPRER_TIMGXPRE		BIT(0)
+
 /* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
 #define RCC_MP_ENCLRR_OFFSET		U(4)
 
@@ -228,6 +284,7 @@
 #define RCC_BDCR_LSEON			BIT(0)
 #define RCC_BDCR_LSEBYP			BIT(1)
 #define RCC_BDCR_LSERDY			BIT(2)
+#define RCC_BDCR_DIGBYP			BIT(3)
 #define RCC_BDCR_LSEDRV_MASK		GENMASK(5, 4)
 #define RCC_BDCR_LSEDRV_SHIFT		4
 #define RCC_BDCR_LSECSSON		BIT(8)
@@ -243,6 +300,7 @@
 /* Used for all RCC_PLL<n>CR registers */
 #define RCC_PLLNCR_PLLON		BIT(0)
 #define RCC_PLLNCR_PLLRDY		BIT(1)
+#define RCC_PLLNCR_SSCG_CTRL		BIT(2)
 #define RCC_PLLNCR_DIVPEN		BIT(4)
 #define RCC_PLLNCR_DIVQEN		BIT(5)
 #define RCC_PLLNCR_DIVREN		BIT(6)
@@ -281,8 +339,12 @@
 
 /* Used for RCC_OCENSETR and RCC_OCENCLRR registers */
 #define RCC_OCENR_HSION			BIT(0)
+#define RCC_OCENR_HSIKERON		BIT(1)
 #define RCC_OCENR_CSION			BIT(4)
+#define RCC_OCENR_CSIKERON		BIT(5)
+#define RCC_OCENR_DIGBYP		BIT(7)
 #define RCC_OCENR_HSEON			BIT(8)
+#define RCC_OCENR_HSEKERON		BIT(9)
 #define RCC_OCENR_HSEBYP		BIT(10)
 #define RCC_OCENR_HSECSSON		BIT(11)
 
@@ -319,6 +381,16 @@
 
 /* Fields of RCC_HSICFGR register */
 #define RCC_HSICFGR_HSIDIV_MASK		GENMASK(1, 0)
+#define RCC_HSICFGR_HSITRIM_SHIFT	8
+#define RCC_HSICFGR_HSITRIM_MASK	GENMASK(14, 8)
+#define RCC_HSICFGR_HSICAL_SHIFT	16
+#define RCC_HSICFGR_HSICAL_MASK		GENMASK(27, 16)
+
+/* Fields of RCC_CSICFGR register */
+#define RCC_CSICFGR_CSITRIM_SHIFT	8
+#define RCC_CSICFGR_CSITRIM_MASK	GENMASK(12, 8)
+#define RCC_CSICFGR_CSICAL_SHIFT	16
+#define RCC_CSICFGR_CSICAL_MASK		GENMASK(23, 16)
 
 /* Used for RCC_MCO related operations */
 #define RCC_MCOCFG_MCOON		BIT(12)
@@ -330,22 +402,36 @@
 #define RCC_DBGCFGR_DBGCKEN		BIT(8)
 
 /* RCC register fields for reset reasons */
-#define  RCC_MP_RSTSCLRR_PORRSTF	BIT(0)
-#define  RCC_MP_RSTSCLRR_BORRSTF	BIT(1)
-#define  RCC_MP_RSTSCLRR_PADRSTF	BIT(2)
-#define  RCC_MP_RSTSCLRR_HCSSRSTF	BIT(3)
-#define  RCC_MP_RSTSCLRR_VCORERSTF	BIT(4)
-#define  RCC_MP_RSTSCLRR_MPSYSRSTF	BIT(6)
-#define  RCC_MP_RSTSCLRR_IWDG1RSTF	BIT(8)
-#define  RCC_MP_RSTSCLRR_IWDG2RSTF	BIT(9)
-#define  RCC_MP_RSTSCLRR_STDBYRSTF	BIT(11)
-#define  RCC_MP_RSTSCLRR_CSTDBYRSTF	BIT(12)
+#define RCC_MP_RSTSCLRR_PORRSTF		BIT(0)
+#define RCC_MP_RSTSCLRR_BORRSTF		BIT(1)
+#define RCC_MP_RSTSCLRR_PADRSTF		BIT(2)
+#define RCC_MP_RSTSCLRR_HCSSRSTF	BIT(3)
+#define RCC_MP_RSTSCLRR_VCORERSTF	BIT(4)
+#define RCC_MP_RSTSCLRR_MPSYSRSTF	BIT(6)
+#define RCC_MP_RSTSCLRR_MCSYSRSTF	BIT(7)
+#define RCC_MP_RSTSCLRR_IWDG1RSTF	BIT(8)
+#define RCC_MP_RSTSCLRR_IWDG2RSTF	BIT(9)
+#define RCC_MP_RSTSCLRR_STDBYRSTF	BIT(11)
+#define RCC_MP_RSTSCLRR_CSTDBYRSTF	BIT(12)
+#define RCC_MP_RSTSCLRR_MPUP0RSTF	BIT(13)
+#define RCC_MP_RSTSCLRR_MPUP1RSTF	BIT(14)
 
 /* Global Reset Register */
 #define RCC_MP_GRSTCSETR_MPSYSRST	BIT(0)
+#define RCC_MP_GRSTCSETR_MPUP0RST	BIT(4)
+#define RCC_MP_GRSTCSETR_MPUP1RST	BIT(5)
 
 /* Clock Source Interrupt Flag Register */
 #define RCC_MP_CIFR_MASK		U(0x110F1F)
+#define RCC_MP_CIFR_LSIRDYF		BIT(0)
+#define RCC_MP_CIFR_LSERDYF		BIT(1)
+#define RCC_MP_CIFR_HSIRDYF		BIT(2)
+#define RCC_MP_CIFR_HSERDYF		BIT(3)
+#define RCC_MP_CIFR_CSIRDYF		BIT(4)
+#define RCC_MP_CIFR_PLL1DYF		BIT(8)
+#define RCC_MP_CIFR_PLL2DYF		BIT(9)
+#define RCC_MP_CIFR_PLL3DYF		BIT(10)
+#define RCC_MP_CIFR_PLL4DYF		BIT(11)
 #define RCC_MP_CIFR_WKUPF		BIT(20)
 
 /* Stop Request Set Register */
@@ -362,7 +448,29 @@
 /* Values of RCC_MP_APB1ENSETR register */
 #define RCC_MP_APB1ENSETR_UART4EN	BIT(16)
 
+/* Values of RCC_MP_APB5ENSETR register */
+#define RCC_MP_APB5ENSETR_SPI6EN	BIT(0)
+#define RCC_MP_APB5ENSETR_I2C4EN	BIT(2)
+#define RCC_MP_APB5ENSETR_I2C6EN	BIT(3)
+#define RCC_MP_APB5ENSETR_USART1EN	BIT(4)
+#define RCC_MP_APB5ENSETR_RTCAPBEN	BIT(8)
+#define RCC_MP_APB5ENSETR_IWDG1APBEN	BIT(15)
+
 /* Values of RCC_MP_AHB4ENSETR register */
 #define RCC_MP_AHB4ENSETR_GPIOGEN	BIT(6)
+#define RCC_MP_AHB4ENSETR_GPIOHEN	BIT(7)
+
+/* Values of RCC_MP_AHB5ENSETR register */
+#define RCC_MP_AHB5ENSETR_GPIOZEN	BIT(0)
+#define RCC_MP_AHB5ENSETR_CRYP1EN	BIT(4)
+#define RCC_MP_AHB5ENSETR_HASH1EN	BIT(5)
+#define RCC_MP_AHB5ENSETR_RNG1EN	BIT(6)
+
+/* Values of RCC_MP_IWDGFZSETR register */
+#define RCC_MP_IWDGFZSETR_IWDG1		BIT(0)
+#define RCC_MP_IWDGFZSETR_IWDG2		BIT(1)
+
+/* Values of RCC_PWRLPDLYCR register */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK	GENMASK(21, 0)
 
 #endif /* STM32MP1_RCC_H */