diff --git a/plat/qemu/include/platform_def.h b/plat/qemu/include/platform_def.h index 2dd10ad..d7f77cc 100644 --- a/plat/qemu/include/platform_def.h +++ b/plat/qemu/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -197,7 +197,7 @@ #define PLAT_QEMU_FIP_MAX_SIZE QEMU_FLASH0_SIZE #define DEVICE0_BASE 0x08000000 -#define DEVICE0_SIZE 0x00021000 +#define DEVICE0_SIZE 0x01000000 #define DEVICE1_BASE 0x09000000 #define DEVICE1_SIZE 0x00041000 @@ -207,7 +207,7 @@ #define GICD_BASE 0x8000000 #define GICC_BASE 0x8010000 -#define GICR_BASE 0 +#define GICR_BASE 0x80A0000 #define QEMU_IRQ_SEC_SGI_0 8 @@ -219,6 +219,30 @@ #define QEMU_IRQ_SEC_SGI_6 14 #define QEMU_IRQ_SEC_SGI_7 15 +/****************************************************************************** + * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 + * interrupts. + *****************************************************************************/ +#define PLATFORM_G1S_PROPS(grp) \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE) + +#define PLATFORM_G0_PROPS(grp) + /* * DT related constants */ diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk index 85d83ea..6b9749c 100644 --- a/plat/qemu/platform.mk +++ b/plat/qemu/platform.mk @@ -1,9 +1,12 @@ # -# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # +# Use the GICv2 driver on QEMU by default +QEMU_USE_GIC_DRIVER := QEMU_GICV2 + ifeq (${ARM_ARCH_MAJOR},7) # ARMv7 Qemu support in trusted firmware expects the Cortex-A15 model. # Qemu Cortex-A15 model does not implement the virtualization extension. @@ -120,20 +123,36 @@ BL2_SOURCES += lib/optee/optee_utils.c endif +QEMU_GICV2_SOURCES := drivers/arm/gic/v2/gicv2_helpers.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/common/gic_common.c \ + plat/common/plat_gicv2.c \ + plat/qemu/qemu_gicv2.c + +QEMU_GICV3_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \ + drivers/arm/gic/v3/gicv3_main.c \ + drivers/arm/gic/common/gic_common.c \ + plat/common/plat_gicv3.c \ + plat/qemu/qemu_gicv3.c + +ifeq (${QEMU_USE_GIC_DRIVER}, QEMU_GICV2) +QEMU_GIC_SOURCES := ${QEMU_GICV2_SOURCES} +else ifeq (${QEMU_USE_GIC_DRIVER}, QEMU_GICV3) +QEMU_GIC_SOURCES := ${QEMU_GICV3_SOURCES} +else +$(error "Incorrect GIC driver chosen for QEMU platform") +endif ifeq (${ARM_ARCH_MAJOR},8) BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ - drivers/arm/gic/v2/gicv2_helpers.c \ - drivers/arm/gic/v2/gicv2_main.c \ - drivers/arm/gic/common/gic_common.c \ - plat/common/plat_gicv2.c \ plat/common/plat_psci_common.c \ plat/qemu/qemu_pm.c \ plat/qemu/topology.c \ plat/qemu/aarch64/plat_helpers.S \ - plat/qemu/qemu_bl31_setup.c + plat/qemu/qemu_bl31_setup.c \ + ${QEMU_GIC_SOURCES} endif # Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images diff --git a/plat/qemu/qemu_bl31_setup.c b/plat/qemu/qemu_bl31_setup.c index 7453b89..4d36b03 100644 --- a/plat/qemu/qemu_bl31_setup.c +++ b/plat/qemu/qemu_bl31_setup.c @@ -1,16 +1,12 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include -#include - #include -#include -#include #include #include "qemu_private.h" @@ -73,49 +69,9 @@ BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); } -/****************************************************************************** - * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 - * interrupts. - *****************************************************************************/ -#define PLATFORM_G1S_PROPS(grp) \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_EDGE) - -#define PLATFORM_G0_PROPS(grp) - -static const interrupt_prop_t qemu_interrupt_props[] = { - PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0), - PLATFORM_G0_PROPS(GICV2_INTR_GROUP0) -}; - -static const struct gicv2_driver_data plat_gicv2_driver_data = { - .gicd_base = GICD_BASE, - .gicc_base = GICC_BASE, - .interrupt_props = qemu_interrupt_props, - .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props), -}; - void bl31_platform_setup(void) { - /* Initialize the gic cpu and distributor interfaces */ - gicv2_driver_init(&plat_gicv2_driver_data); - gicv2_distif_init(); - gicv2_pcpu_distif_init(); - gicv2_cpuif_enable(); + plat_qemu_gic_init(); } unsigned int plat_get_syscnt_freq2(void) diff --git a/plat/qemu/qemu_gicv2.c b/plat/qemu/qemu_gicv2.c new file mode 100644 index 0000000..fb56622 --- /dev/null +++ b/plat/qemu/qemu_gicv2.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +static const interrupt_prop_t qemu_interrupt_props[] = { + PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0), + PLATFORM_G0_PROPS(GICV2_INTR_GROUP0) +}; + +static const struct gicv2_driver_data plat_gicv2_driver_data = { + .gicd_base = GICD_BASE, + .gicc_base = GICC_BASE, + .interrupt_props = qemu_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props), +}; + +void plat_qemu_gic_init(void) +{ + /* Initialize the gic cpu and distributor interfaces */ + gicv2_driver_init(&plat_gicv2_driver_data); + gicv2_distif_init(); + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} + +void qemu_pwr_gic_on_finish(void) +{ + /* TODO: This setup is needed only after a cold boot */ + gicv2_pcpu_distif_init(); + + /* Enable the gic cpu interface */ + gicv2_cpuif_enable(); +} diff --git a/plat/qemu/qemu_gicv3.c b/plat/qemu/qemu_gicv3.c new file mode 100644 index 0000000..28572c5 --- /dev/null +++ b/plat/qemu/qemu_gicv3.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2019, Linaro Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +static const interrupt_prop_t qemu_interrupt_props[] = { + PLATFORM_G1S_PROPS(INTR_GROUP1S), + PLATFORM_G0_PROPS(INTR_GROUP0) +}; + +static uintptr_t qemu_rdistif_base_addrs[PLATFORM_CORE_COUNT]; + +static unsigned int qemu_mpidr_to_core_pos(unsigned long mpidr) +{ + return (unsigned int)plat_core_pos_by_mpidr(mpidr); +} + +static const gicv3_driver_data_t qemu_gicv3_driver_data = { + .gicd_base = GICD_BASE, + .gicr_base = GICR_BASE, + .interrupt_props = qemu_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props), + .rdistif_num = PLATFORM_CORE_COUNT, + .rdistif_base_addrs = qemu_rdistif_base_addrs, + .mpidr_to_core_pos = qemu_mpidr_to_core_pos +}; + +void plat_qemu_gic_init(void) +{ + gicv3_driver_init(&qemu_gicv3_driver_data); + gicv3_distif_init(); + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); +} + +void qemu_pwr_gic_on_finish(void) +{ + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); +} diff --git a/plat/qemu/qemu_pm.c b/plat/qemu/qemu_pm.c index 3249d6e..a199688 100644 --- a/plat/qemu/qemu_pm.c +++ b/plat/qemu/qemu_pm.c @@ -1,19 +1,19 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include - #include #include #include -#include #include #include +#include "qemu_private.h" + /* * The secure entry point to be used on warm reset. */ @@ -173,11 +173,7 @@ assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == PLAT_LOCAL_STATE_OFF); - /* TODO: This setup is needed only after a cold boot */ - gicv2_pcpu_distif_init(); - - /* Enable the gic cpu interface */ - gicv2_cpuif_enable(); + qemu_pwr_gic_on_finish(); } /******************************************************************************* diff --git a/plat/qemu/qemu_private.h b/plat/qemu/qemu_private.h index 754831a..46b1ca1 100644 --- a/plat/qemu/qemu_private.h +++ b/plat/qemu/qemu_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -33,4 +33,7 @@ void qemu_console_init(void); +void plat_qemu_gic_init(void); +void qemu_pwr_gic_on_finish(void); + #endif /* QEMU_PRIVATE_H */