diff --git a/fdts/corstone700.dts b/fdts/corstone700.dts deleted file mode 100644 index 851f5e6..0000000 --- a/fdts/corstone700.dts +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/dts-v1/; - -/ { - model = "corstone700"; - compatible = "arm,Corstone-700"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { - bootargs = "console=ttyAMA0 \ - loglevel=9"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0>; - next-level-cache = <&L2_0>; - }; - - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - gic: interrupt-controller@1c000000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x1c010000 0x1000>, - <0x1c02f000 0x2000>, - <0x1c04f000 0x1000>, - <0x1c06f000 0x2000>; - interrupts = <1 9 0xf08>; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - - refclk100mhz: refclk100mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "apb_pclk"; - }; - - smbclk: refclk24mhzx2 { - /* Reference 24MHz clock x 2 */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - clock-output-names = "smclk"; - }; - - uartclk: uartclk { - /* UART clock - 32MHz */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000000>; - clock-output-names = "uartclk"; - }; - - serial0: uart@1a510000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1a510000 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 19 4>; - clocks = <&uartclk>, <&refclk100mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - serial1: uart@1a520000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1a520000 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 20 4>; - clocks = <&uartclk>, <&refclk100mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - mbox_es0mhu0: mhu@1b000000 { - compatible = "arm,mhuv2","arm,primecell"; - reg = <0x1b000000 0x1000>, - <0x1b010000 0x1000>; - clocks = <&refclk100mhz>; - clock-names = "apb_pclk"; - interrupts = <0 12 4>; - interrupt-names = "mhu_rx"; - #mbox-cells = <1>; - mbox-name = "arm-es0-mhu0"; - }; - - mbox_es0mhu1: mhu@1b020000 { - compatible = "arm,mhuv2","arm,primecell"; - reg = <0x1b020000 0x1000>, - <0x1b030000 0x1000>; - clocks = <&refclk100mhz>; - clock-names = "apb_pclk"; - interrupts = <0 47 4>; - interrupt-names = "mhu_rx"; - #mbox-cells = <1>; - mbox-name = "arm-es0-mhu1"; - }; - - mbox_semhu1: mhu@1b820000 { - compatible = "arm,mhuv2","arm,primecell"; - reg = <0x1b820000 0x1000>, - <0x1b830000 0x1000>; - clocks = <&refclk100mhz>; - clock-names = "apb_pclk"; - interrupts = <0 45 4>; - interrupt-names = "mhu_rx"; - #mbox-cells = <1>; - mbox-name = "arm-se-mhu1"; - }; - - client { - compatible = "arm,client"; - mboxes = <&mbox_es0mhu0 0>, <&mbox_es0mhu1 0>, <&mbox_semhu1 0>; - mbox-names = "es0mhu0", "es0mhu1", "semhu1"; - }; - - extsys0: extsys@1A010310 { - compatible = "arm,extsys_ctrl"; - reg = <0x1A010310 0x4>, - <0x1A010314 0x4>; - reg-names = "rstreg", "streg"; - }; - -}; diff --git a/fdts/corstone700.dtsi b/fdts/corstone700.dtsi new file mode 100644 index 0000000..2372207 --- /dev/null +++ b/fdts/corstone700.dtsi @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +/ { + compatible = "arm,Corstone-700"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0>; + next-level-cache = <&L2_0>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + gic: interrupt-controller@1c000000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1c010000 0x1000>, + <0x1c02f000 0x2000>, + <0x1c04f000 0x1000>, + <0x1c06f000 0x2000>; + interrupts = <1 9 0xf08>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + + refclk100mhz: refclk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "apb_pclk"; + }; + + smbclk: refclk24mhzx2 { + /* Reference 24MHz clock x 2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "smclk"; + }; + + uartclk: uartclk { + /* UART clock - 32MHz */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000000>; + clock-output-names = "uartclk"; + }; + + serial0: uart@1a510000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1a510000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 19 4>; + clocks = <&uartclk>, <&refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + serial1: uart@1a520000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1a520000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 20 4>; + clocks = <&uartclk>, <&refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + refclk: refclk@1a220000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x1a220000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@1a230000 { + frame-number = <0>; + interrupts = <0 2 0xf04>; + reg = <0x1a230000 0x1000>; + }; + }; + + mbox_es0mhu0: mhu@1b000000 { + compatible = "arm,mhuv2","arm,primecell"; + reg = <0x1b000000 0x1000>, + <0x1b010000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = <0 12 4>; + interrupt-names = "mhu_rx"; + #mbox-cells = <1>; + mbox-name = "arm-es0-mhu0"; + }; + + mbox_es0mhu1: mhu@1b020000 { + compatible = "arm,mhuv2","arm,primecell"; + reg = <0x1b020000 0x1000>, + <0x1b030000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = <0 47 4>; + interrupt-names = "mhu_rx"; + #mbox-cells = <1>; + mbox-name = "arm-es0-mhu1"; + }; + + mbox_semhu1: mhu@1b820000 { + compatible = "arm,mhuv2","arm,primecell"; + reg = <0x1b820000 0x1000>, + <0x1b830000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = <0 45 4>; + interrupt-names = "mhu_rx"; + #mbox-cells = <1>; + mbox-name = "arm-se-mhu1"; + }; + + client { + compatible = "arm,client"; + mboxes = <&mbox_es0mhu0 0>, <&mbox_es0mhu1 0>, <&mbox_semhu1 0>; + mbox-names = "es0mhu0", "es0mhu1", "semhu1"; + }; + + extsys0: extsys@1A010310 { + compatible = "arm,extsys_ctrl"; + reg = <0x1A010310 0x4>, + <0x1A010314 0x4>; + reg-names = "rstreg", "streg"; + }; +}; diff --git a/fdts/corstone700_fpga.dts b/fdts/corstone700_fpga.dts new file mode 100644 index 0000000..814d6a8 --- /dev/null +++ b/fdts/corstone700_fpga.dts @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/dts-v1/; + +#include "corstone700.dtsi" + +/ { + model = "corstone700-fpga"; + + ethernet: eth@40100000 { + compatible = "smsc,lan9115"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupt-parent = <&gic>; + interrupts = ; + reg-io-width = <2>; + smsc,irq-push-pull; + }; +}; + +&refclk { + clock-frequency = <32000000>; +}; diff --git a/fdts/corstone700_fvp.dts b/fdts/corstone700_fvp.dts new file mode 100644 index 0000000..3b1202d --- /dev/null +++ b/fdts/corstone700_fvp.dts @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/dts-v1/; + +#include "corstone700.dtsi" + +/ { + model = "corstone700-fvp"; + + /* + * Intel StrataFlash J3 NOR flash: 2 x 16-bit interleaved components + * Flash total size: 32 MB + * Allocated flash space: 8 MB + */ + + flash@8500000 { + compatible = "cfi-flash"; + reg = <0x8500000 0x800000>; + bank-width = <4>; + device-width= <2>; + }; + + ethernet: eth@4010000 { + compatible = "smsc,lan91c111"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupt-parent = <&gic>; + interrupts = ; + reg-io-width = <2>; + smsc,irq-push-pull; + }; +}; + +&refclk { + clock-frequency = <50000000>; +}; diff --git a/plat/arm/board/corstone700/common/corstone700_helpers.S b/plat/arm/board/corstone700/common/corstone700_helpers.S new file mode 100644 index 0000000..c713f4f --- /dev/null +++ b/plat/arm/board/corstone700/common/corstone700_helpers.S @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + + .globl plat_secondary_cold_boot_setup + .globl plat_get_my_entrypoint + .globl plat_is_my_cpu_primary + .globl plat_arm_calc_core_pos + + /* -------------------------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * For AArch32, cold-booting secondary CPUs is not yet + * implemented and they panic. + * -------------------------------------------------------------------- + */ +func plat_secondary_cold_boot_setup +cb_panic: + b cb_panic +endfunc plat_secondary_cold_boot_setup + + /* --------------------------------------------------------------------- + * unsigned long plat_get_my_entrypoint (void); + * + * Main job of this routine is to distinguish between a cold and warm + * boot. On Corstone700, this information can be queried from the power + * controller. The Power Control SYS Status Register (PSYSR) indicates + * the wake-up reason for the CPU. + * + * For a cold boot, return 0. + * For a warm boot, Not yet supported. + * + * TODO: PSYSR is a common register and should be + * accessed using locks. Since it is not possible + * to use locks immediately after a cold reset + * we are relying on the fact that after a cold + * reset all cpus will read the same WK field + * --------------------------------------------------------------------- + */ +func plat_get_my_entrypoint + /* TODO support warm boot */ + /* Cold reset */ + mov r0, #0 + bx lr +endfunc plat_get_my_entrypoint + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary (void); + * + * Find out whether the current CPU is the primary + * CPU. + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + ldcopr r0, MPIDR + ldr r1, =MPIDR_AFFINITY_MASK + and r0, r1 + cmp r0, #0 + moveq r0, #1 + movne r0, #0 + bx lr +endfunc plat_is_my_cpu_primary + + /* --------------------------------------------------------------------- + * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) + * + * Function to calculate the core position on Corstone700. + * + * (ClusterId * MAX_CPUS_PER_CLUSTER * MAX_PE_PER_CPU) + + * (CPUId * MAX_PE_PER_CPU) + + * ThreadId + * + * which can be simplified as: + * + * ((ClusterId * MAX_CPUS_PER_CLUSTER + CPUId) * MAX_PE_PER_CPU) + * + ThreadId + * --------------------------------------------------------------------- + */ +func plat_arm_calc_core_pos + mov r3, r0 + + /* Extract individual affinity fields from MPIDR */ + ubfx r0, r3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS + ubfx r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS + ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS + + /* Compute linear position */ + mov r3, #CORSTONE700_MAX_CPUS_PER_CLUSTER + mla r1, r2, r3, r1 + mov r3, #CORSTONE700_MAX_PE_PER_CPU + mla r0, r1, r3, r0 + + bx lr +endfunc plat_arm_calc_core_pos diff --git a/plat/arm/board/corstone700/common/corstone700_plat.c b/plat/arm/board/corstone700/common/corstone700_plat.c new file mode 100644 index 0000000..629f076 --- /dev/null +++ b/plat/arm/board/corstone700/common/corstone700_plat.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include +#include + +/* + * Table of regions to map using the MMU. + * Replace or extend the below regions as required + */ + +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + ARM_MAP_NS_SHARED_RAM, + ARM_MAP_NS_DRAM1, + CORSTONE700_MAP_DEVICE, + {0} +}; + +/* Corstone700 only has one always-on power domain and there + * is no power control present + */ +void __init plat_arm_pwrc_setup(void) +{ + mhu_secure_init(); +} + +unsigned int plat_get_syscnt_freq2(void) +{ + /* Returning the Generic Timer Frequency */ + return SYS_COUNTER_FREQ_IN_TICKS; +} diff --git a/plat/arm/board/corstone700/common/corstone700_pm.c b/plat/arm/board/corstone700/common/corstone700_pm.c new file mode 100644 index 0000000..4884ea5 --- /dev/null +++ b/plat/arm/board/corstone700/common/corstone700_pm.c @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +/******************************************************************************* + * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard + * platform layer will take care of registering the handlers with PSCI. + ******************************************************************************/ +plat_psci_ops_t plat_arm_psci_pm_ops = { + /* dummy struct */ + .validate_ns_entrypoint = NULL +}; + +const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) +{ + return ops; +} diff --git a/plat/arm/board/corstone700/common/corstone700_security.c b/plat/arm/board/corstone700/common/corstone700_security.c new file mode 100644 index 0000000..39b2fc9 --- /dev/null +++ b/plat/arm/board/corstone700/common/corstone700_security.c @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * We assume that all security programming is done by the primary core. + */ +void plat_arm_security_setup(void) +{ + /* + * If the platform had additional peripheral specific security + * configurations, those would be configured here. + */ +} diff --git a/plat/arm/board/corstone700/common/corstone700_stack_protector.c b/plat/arm/board/corstone700/common/corstone700_stack_protector.c new file mode 100644 index 0000000..6fd09da --- /dev/null +++ b/plat/arm/board/corstone700/common/corstone700_stack_protector.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include + +static uint32_t plat_generate_random_number(void) +{ + uintptr_t return_addr = (uintptr_t)__builtin_return_address(0U); + uintptr_t frame_addr = (uintptr_t)__builtin_frame_address(0U); + uint64_t cntpct = read_cntpct_el0(); + + /* Generate 32-bit pattern: saving the 2 least significant bytes + * in random_lo and random_hi + */ + uint16_t random_lo = (uint16_t)( + (((uint64_t)return_addr) << 13) ^ frame_addr ^ cntpct + ); + + uint16_t random_hi = (uint16_t)( + (((uint64_t)frame_addr) << 15) ^ return_addr ^ cntpct + ); + + return (((uint32_t)random_hi) << 16) | random_lo; +} + +u_register_t plat_get_stack_protector_canary(void) +{ + return plat_generate_random_number(); /* a 32-bit pattern is returned */ +} diff --git a/plat/arm/board/corstone700/common/corstone700_topology.c b/plat/arm/board/corstone700/common/corstone700_topology.c new file mode 100644 index 0000000..904f5ab --- /dev/null +++ b/plat/arm/board/corstone700/common/corstone700_topology.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +/* The Corstone700 power domain tree descriptor */ +static unsigned char corstone700_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT + + 2]; +/******************************************************************************* + * This function dynamically constructs the topology according to + * CLUSTER_COUNT and returns it. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + int i; + + /* + * The highest level is the system level. The next level is constituted + * by clusters and then cores in clusters. + */ + corstone700_power_domain_tree_desc[0] = 1; + corstone700_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT; + + for (i = 0; i < PLAT_ARM_CLUSTER_COUNT; i++) + corstone700_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT; + + return corstone700_power_domain_tree_desc; +} + +/****************************************************************************** + * This function implements a part of the critical interface between the PSCI + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is + * returned in case the MPIDR is invalid. + *****************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + return plat_arm_calc_core_pos(mpidr); +} diff --git a/plat/arm/board/corstone700/common/drivers/mhu/mhu.c b/plat/arm/board/corstone700/common/drivers/mhu/mhu.c new file mode 100644 index 0000000..2231d11 --- /dev/null +++ b/plat/arm/board/corstone700/common/drivers/mhu/mhu.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include +#include +#include + +#include "mhu.h" +#include +#include + +ARM_INSTANTIATE_LOCK; + +#pragma weak plat_arm_pwrc_setup + +/* + * Slot 31 is reserved because the MHU hardware uses this register bit to + * indicate a non-secure access attempt. The total number of available slots is + * therefore 31 [30:0]. + */ +#define MHU_MAX_SLOT_ID 30 + +void mhu_secure_message_start(uintptr_t address, unsigned int slot_id) +{ + unsigned int intr_stat_check; + uint64_t timeout_cnt; + volatile uint8_t expiration; + + assert(slot_id <= MHU_MAX_SLOT_ID); + arm_lock_get(); + + /* + * Make sure any previous command has finished + * and polling timeout not expired + */ + + timeout_cnt = timeout_init_us(MHU_POLL_INTR_STAT_TIMEOUT); + + do { + intr_stat_check = (mmio_read_32(address + CPU_INTR_S_STAT) & + (1 << slot_id)); + + expiration = timeout_elapsed(timeout_cnt); + + } while ((intr_stat_check != 0U) && (expiration == 0U)); + + /* + * Note: No risk of timer overflows while waiting + * for the timeout expiration. + * According to Armv8 TRM: System counter roll-over + * time of not less than 40 years + */ +} + +void mhu_secure_message_send(uintptr_t address, + unsigned int slot_id, + unsigned int message) +{ + unsigned char access_ready; + uint64_t timeout_cnt; + volatile uint8_t expiration; + + assert(slot_id <= MHU_MAX_SLOT_ID); + assert((mmio_read_32(address + CPU_INTR_S_STAT) & + (1 << slot_id)) == 0U); + + MHU_V2_ACCESS_REQUEST(address); + + timeout_cnt = timeout_init_us(MHU_POLL_INTR_STAT_TIMEOUT); + + do { + access_ready = MHU_V2_IS_ACCESS_READY(address); + expiration = timeout_elapsed(timeout_cnt); + + } while ((access_ready == 0U) && (expiration == 0U)); + + /* + * Note: No risk of timer overflows while waiting + * for the timeout expiration. + * According to Armv8 TRM: System counter roll-over + * time of not less than 40 years + */ + + mmio_write_32(address + CPU_INTR_S_SET, message); +} + +void mhu_secure_message_end(uintptr_t address, unsigned int slot_id) +{ + assert(slot_id <= MHU_MAX_SLOT_ID); + /* + * Clear any response we got by writing one in the relevant slot bit to + * the CLEAR register + */ + MHU_V2_CLEAR_REQUEST(address); + + arm_lock_release(); +} + +void __init mhu_secure_init(void) +{ + arm_lock_init(); + + /* + * The STAT register resets to zero. Ensure it is in the expected state, + * as a stale or garbage value would make us think it's a message we've + * already sent. + */ + + assert(mmio_read_32(PLAT_SDK700_MHU0_SEND + CPU_INTR_S_STAT) == 0); +} diff --git a/plat/arm/board/corstone700/common/drivers/mhu/mhu.h b/plat/arm/board/corstone700/common/drivers/mhu/mhu.h new file mode 100644 index 0000000..3808746 --- /dev/null +++ b/plat/arm/board/corstone700/common/drivers/mhu/mhu.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MHU_H +#define MHU_H + +#define MHU_POLL_INTR_STAT_TIMEOUT 50000 /*timeout value in us*/ + +/* CPU MHU secure channel registers */ +#define CPU_INTR_S_STAT 0x00 +#define CPU_INTR_S_SET 0x0C + +/* MHUv2 Control Registers Offsets */ +#define MHU_V2_MSG_CFG_OFFSET 0xF80 +#define MHU_V2_ACCESS_REQ_OFFSET 0xF88 +#define MHU_V2_ACCESS_READY_OFFSET 0xF8C + +#define MHU_V2_ACCESS_REQUEST(addr) \ + mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x1) + +#define MHU_V2_CLEAR_REQUEST(addr) \ + mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x0) + +#define MHU_V2_IS_ACCESS_READY(addr) \ + (mmio_read_32((addr) + MHU_V2_ACCESS_READY_OFFSET) & 0x1) + +void mhu_secure_message_start(uintptr_t address, unsigned int slot_id); +void mhu_secure_message_send(uintptr_t address, + unsigned int slot_id, + unsigned int message); +void mhu_secure_message_end(uintptr_t address, unsigned int slot_id); +void mhu_secure_init(void); + +#endif /* MHU_H */ diff --git a/plat/arm/board/corstone700/common/include/platform_def.h b/plat/arm/board/corstone700/common/include/platform_def.h new file mode 100644 index 0000000..c92086c --- /dev/null +++ b/plat/arm/board/corstone700/common/include/platform_def.h @@ -0,0 +1,261 @@ +/* + * Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include +#include +#include +#include +#include +#include + +/* PL011 UART related constants */ +#ifdef V2M_IOFPGA_UART0_CLK_IN_HZ +#undef V2M_IOFPGA_UART0_CLK_IN_HZ +#endif + +#ifdef V2M_IOFPGA_UART1_CLK_IN_HZ +#undef V2M_IOFPGA_UART1_CLK_IN_HZ +#endif + +#define V2M_IOFPGA_UART0_CLK_IN_HZ 32000000 +#define V2M_IOFPGA_UART1_CLK_IN_HZ 32000000 + +/* Core/Cluster/Thread counts for Corstone700 */ +#define CORSTONE700_CLUSTER_COUNT U(1) +#define CORSTONE700_MAX_CPUS_PER_CLUSTER U(4) +#define CORSTONE700_MAX_PE_PER_CPU U(1) + +#define PLAT_ARM_CLUSTER_COUNT CORSTONE700_CLUSTER_COUNT + +#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ + CORSTONE700_MAX_CPUS_PER_CLUSTER * \ + CORSTONE700_MAX_PE_PER_CPU) + + +/* UART related constants */ +#define PLAT_ARM_BOOT_UART_BASE 0x1a510000 +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ +#define PLAT_ARM_RUN_UART_BASE 0x1a520000 +#define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ +#define ARM_CONSOLE_BAUDRATE 115200 +#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ + +/* Memory related constants */ +#define ARM_DRAM1_BASE UL(0x80000000) +#define ARM_DRAM1_SIZE UL(0x80000000) +#define ARM_DRAM1_END (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - 1) +#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE +#define ARM_NS_DRAM1_SIZE ARM_DRAM1_SIZE +#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ + ARM_NS_DRAM1_SIZE - 1) +#define ARM_TRUSTED_SRAM_BASE UL(0x02000000) +#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE +#define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ +#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ + +/* The remaining Trusted SRAM is used to load the BL images */ +#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ + ARM_SHARED_RAM_SIZE) +#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ + ARM_SHARED_RAM_SIZE) + +#define ARM_NS_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE + UL(0x00100000) +#define ARM_NS_SHARED_RAM_SIZE 0x00300000 + +/* + * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding + * the page reserved for fw_configs) to BL32 + */ +#define BL32_BASE (ARM_BL_RAM_BASE + PAGE_SIZE) +#define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) +#define ARM_CACHE_WRITEBACK_SHIFT 6 + +/* + * To enable FW_CONFIG to be loaded by BL1, define the corresponding base + * and limit. Leave enough space for BL2 meminfo. + */ +#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) +#define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE / 2U)) + +/* + * The max number of regions like RO(code), coherent and data required by + * different BL stages which need to be mapped in the MMU. + */ +#define ARM_BL_REGIONS 2 +#define PLAT_ARM_MMAP_ENTRIES 8 +#define MAX_XLAT_TABLES 5 +#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ + ARM_BL_REGIONS) + +/* GIC related constants */ +#define PLAT_ARM_GICD_BASE 0x1C010000 +#define PLAT_ARM_GICC_BASE 0x1C02F000 + +/* MHUv2 Secure Channel receiver and sender */ +#define PLAT_SDK700_MHU0_SEND 0x1B800000 +#define PLAT_SDK700_MHU0_RECV 0x1B810000 + +/* Timer/watchdog related constants */ +#define ARM_SYS_CNTCTL_BASE UL(0x1a200000) +#define ARM_SYS_CNTREAD_BASE UL(0x1a210000) +#define ARM_SYS_TIMCTL_BASE UL(0x1a220000) + +#ifdef TARGET_PLATFORM_FVP +#define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 50MHz */ +#else +#define SYS_COUNTER_FREQ_IN_TICKS UL(32000000) /* 32MHz */ +#endif + +#define CORSTONE700_IRQ_TZ_WDOG 32 +#define CORSTONE700_IRQ_SEC_SYS_TIMER 34 + +#define PLAT_MAX_PWR_LVL 2 +/* + * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The + * power levels have a 1:1 mapping with the MPIDR affinity levels. + */ +#define ARM_PWR_LVL0 MPIDR_AFFLVL0 +#define ARM_PWR_LVL1 MPIDR_AFFLVL1 +#define ARM_PWR_LVL2 MPIDR_AFFLVL2 + +/* + * Macros for local power states in ARM platforms encoded by State-ID field + * within the power-state parameter. + */ +/* Local power state for power domains in Run state. */ +#define ARM_LOCAL_STATE_RUN U(0) +/* Local power state for retention. Valid only for CPU power domains */ +#define ARM_LOCAL_STATE_RET U(1) +/* Local power state for OFF/power-down. Valid for CPU and cluster + * power domains + */ +#define ARM_LOCAL_STATE_OFF U(2) + +#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE +#define PLAT_ARM_NSTIMER_FRAME_ID U(1) + +#define PLAT_ARM_NS_IMAGE_BASE (ARM_NS_SHARED_RAM_BASE) + +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) + +/* + * This macro defines the deepest retention state possible. A higher state + * ID will represent an invalid or a power down state. + */ +#define PLAT_MAX_RET_STATE 1 + +/* + * This macro defines the deepest power down states possible. Any state ID + * higher than this is invalid. + */ +#define PLAT_MAX_OFF_STATE 2 + +#define PLATFORM_STACK_SIZE UL(0x440) + +#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ + ARM_SHARED_RAM_BASE, \ + ARM_SHARED_RAM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define ARM_MAP_NS_SHARED_RAM MAP_REGION_FLAT( \ + ARM_NS_SHARED_RAM_BASE, \ + ARM_NS_SHARED_RAM_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ + ARM_NS_DRAM1_BASE, \ + ARM_NS_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define ARM_MAP_BL_RO MAP_REGION_FLAT( \ + BL_CODE_BASE, \ + BL_CODE_END \ + - BL_CODE_BASE, \ + MT_CODE | MT_SECURE), \ + MAP_REGION_FLAT( \ + BL_RO_DATA_BASE, \ + BL_RO_DATA_END \ + - BL_RO_DATA_BASE, \ + MT_RO_DATA | MT_SECURE) +#if USE_COHERENT_MEM +#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ + BL_COHERENT_RAM_BASE, \ + BL_COHERENT_RAM_END \ + - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif + +#define CORSTONE700_DEVICE_BASE (0x1A000000) +#define CORSTONE700_DEVICE_SIZE (0x26000000) +#define CORSTONE700_MAP_DEVICE MAP_REGION_FLAT( \ + CORSTONE700_DEVICE_BASE,\ + CORSTONE700_DEVICE_SIZE,\ + MT_DEVICE | MT_RW | MT_SECURE) + +#define ARM_IRQ_SEC_PHY_TIMER 29 + +#define ARM_IRQ_SEC_SGI_0 8 +#define ARM_IRQ_SEC_SGI_1 9 +#define ARM_IRQ_SEC_SGI_2 10 +#define ARM_IRQ_SEC_SGI_3 11 +#define ARM_IRQ_SEC_SGI_4 12 +#define ARM_IRQ_SEC_SGI_5 13 +#define ARM_IRQ_SEC_SGI_6 14 +#define ARM_IRQ_SEC_SGI_7 15 + +/* + * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define ARM_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE) + +#define ARM_G0_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE) + +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + ARM_G1S_IRQ_PROPS(grp), \ + INTR_PROP_DESC(CORSTONE700_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(CORSTONE700_IRQ_SEC_SYS_TIMER, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL) + +#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/arm/board/corstone700/corstone700_helpers.S b/plat/arm/board/corstone700/corstone700_helpers.S deleted file mode 100644 index c713f4f..0000000 --- a/plat/arm/board/corstone700/corstone700_helpers.S +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - - .globl plat_secondary_cold_boot_setup - .globl plat_get_my_entrypoint - .globl plat_is_my_cpu_primary - .globl plat_arm_calc_core_pos - - /* -------------------------------------------------------------------- - * void plat_secondary_cold_boot_setup (void); - * - * For AArch32, cold-booting secondary CPUs is not yet - * implemented and they panic. - * -------------------------------------------------------------------- - */ -func plat_secondary_cold_boot_setup -cb_panic: - b cb_panic -endfunc plat_secondary_cold_boot_setup - - /* --------------------------------------------------------------------- - * unsigned long plat_get_my_entrypoint (void); - * - * Main job of this routine is to distinguish between a cold and warm - * boot. On Corstone700, this information can be queried from the power - * controller. The Power Control SYS Status Register (PSYSR) indicates - * the wake-up reason for the CPU. - * - * For a cold boot, return 0. - * For a warm boot, Not yet supported. - * - * TODO: PSYSR is a common register and should be - * accessed using locks. Since it is not possible - * to use locks immediately after a cold reset - * we are relying on the fact that after a cold - * reset all cpus will read the same WK field - * --------------------------------------------------------------------- - */ -func plat_get_my_entrypoint - /* TODO support warm boot */ - /* Cold reset */ - mov r0, #0 - bx lr -endfunc plat_get_my_entrypoint - - /* ----------------------------------------------------- - * unsigned int plat_is_my_cpu_primary (void); - * - * Find out whether the current CPU is the primary - * CPU. - * ----------------------------------------------------- - */ -func plat_is_my_cpu_primary - ldcopr r0, MPIDR - ldr r1, =MPIDR_AFFINITY_MASK - and r0, r1 - cmp r0, #0 - moveq r0, #1 - movne r0, #0 - bx lr -endfunc plat_is_my_cpu_primary - - /* --------------------------------------------------------------------- - * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) - * - * Function to calculate the core position on Corstone700. - * - * (ClusterId * MAX_CPUS_PER_CLUSTER * MAX_PE_PER_CPU) + - * (CPUId * MAX_PE_PER_CPU) + - * ThreadId - * - * which can be simplified as: - * - * ((ClusterId * MAX_CPUS_PER_CLUSTER + CPUId) * MAX_PE_PER_CPU) - * + ThreadId - * --------------------------------------------------------------------- - */ -func plat_arm_calc_core_pos - mov r3, r0 - - /* Extract individual affinity fields from MPIDR */ - ubfx r0, r3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS - ubfx r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS - ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS - - /* Compute linear position */ - mov r3, #CORSTONE700_MAX_CPUS_PER_CLUSTER - mla r1, r2, r3, r1 - mov r3, #CORSTONE700_MAX_PE_PER_CPU - mla r0, r1, r3, r0 - - bx lr -endfunc plat_arm_calc_core_pos diff --git a/plat/arm/board/corstone700/corstone700_plat.c b/plat/arm/board/corstone700/corstone700_plat.c deleted file mode 100644 index e2ade70..0000000 --- a/plat/arm/board/corstone700/corstone700_plat.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include -#include -#include - -/* - * Table of regions to map using the MMU. - * Replace or extend the below regions as required - */ - -const mmap_region_t plat_arm_mmap[] = { - ARM_MAP_SHARED_RAM, - ARM_MAP_NS_DRAM1, - CORSTONE700_MAP_DEVICE, - {0} -}; - -/* Corstone700 only has one always-on power domain and there - * is no power control present - */ -void __init plat_arm_pwrc_setup(void) -{ - mhu_secure_init(); -} - -unsigned int plat_get_syscnt_freq2(void) -{ - return CORSTONE700_TIMER_BASE_FREQUENCY; -} diff --git a/plat/arm/board/corstone700/corstone700_pm.c b/plat/arm/board/corstone700/corstone700_pm.c deleted file mode 100644 index 4884ea5..0000000 --- a/plat/arm/board/corstone700/corstone700_pm.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -/******************************************************************************* - * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard - * platform layer will take care of registering the handlers with PSCI. - ******************************************************************************/ -plat_psci_ops_t plat_arm_psci_pm_ops = { - /* dummy struct */ - .validate_ns_entrypoint = NULL -}; - -const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) -{ - return ops; -} diff --git a/plat/arm/board/corstone700/corstone700_security.c b/plat/arm/board/corstone700/corstone700_security.c deleted file mode 100644 index 39b2fc9..0000000 --- a/plat/arm/board/corstone700/corstone700_security.c +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* - * We assume that all security programming is done by the primary core. - */ -void plat_arm_security_setup(void) -{ - /* - * If the platform had additional peripheral specific security - * configurations, those would be configured here. - */ -} diff --git a/plat/arm/board/corstone700/corstone700_stack_protector.c b/plat/arm/board/corstone700/corstone700_stack_protector.c deleted file mode 100644 index 6fd09da..0000000 --- a/plat/arm/board/corstone700/corstone700_stack_protector.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include - -static uint32_t plat_generate_random_number(void) -{ - uintptr_t return_addr = (uintptr_t)__builtin_return_address(0U); - uintptr_t frame_addr = (uintptr_t)__builtin_frame_address(0U); - uint64_t cntpct = read_cntpct_el0(); - - /* Generate 32-bit pattern: saving the 2 least significant bytes - * in random_lo and random_hi - */ - uint16_t random_lo = (uint16_t)( - (((uint64_t)return_addr) << 13) ^ frame_addr ^ cntpct - ); - - uint16_t random_hi = (uint16_t)( - (((uint64_t)frame_addr) << 15) ^ return_addr ^ cntpct - ); - - return (((uint32_t)random_hi) << 16) | random_lo; -} - -u_register_t plat_get_stack_protector_canary(void) -{ - return plat_generate_random_number(); /* a 32-bit pattern is returned */ -} diff --git a/plat/arm/board/corstone700/corstone700_topology.c b/plat/arm/board/corstone700/corstone700_topology.c deleted file mode 100644 index 904f5ab..0000000 --- a/plat/arm/board/corstone700/corstone700_topology.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -/* The Corstone700 power domain tree descriptor */ -static unsigned char corstone700_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT - + 2]; -/******************************************************************************* - * This function dynamically constructs the topology according to - * CLUSTER_COUNT and returns it. - ******************************************************************************/ -const unsigned char *plat_get_power_domain_tree_desc(void) -{ - int i; - - /* - * The highest level is the system level. The next level is constituted - * by clusters and then cores in clusters. - */ - corstone700_power_domain_tree_desc[0] = 1; - corstone700_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT; - - for (i = 0; i < PLAT_ARM_CLUSTER_COUNT; i++) - corstone700_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT; - - return corstone700_power_domain_tree_desc; -} - -/****************************************************************************** - * This function implements a part of the critical interface between the PSCI - * generic layer and the platform that allows the former to query the platform - * to convert an MPIDR to a unique linear index. An error code (-1) is - * returned in case the MPIDR is invalid. - *****************************************************************************/ -int plat_core_pos_by_mpidr(u_register_t mpidr) -{ - return plat_arm_calc_core_pos(mpidr); -} diff --git a/plat/arm/board/corstone700/drivers/mhu/mhu.c b/plat/arm/board/corstone700/drivers/mhu/mhu.c deleted file mode 100644 index 2231d11..0000000 --- a/plat/arm/board/corstone700/drivers/mhu/mhu.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) 2019-2020, ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include -#include -#include -#include - -#include "mhu.h" -#include -#include - -ARM_INSTANTIATE_LOCK; - -#pragma weak plat_arm_pwrc_setup - -/* - * Slot 31 is reserved because the MHU hardware uses this register bit to - * indicate a non-secure access attempt. The total number of available slots is - * therefore 31 [30:0]. - */ -#define MHU_MAX_SLOT_ID 30 - -void mhu_secure_message_start(uintptr_t address, unsigned int slot_id) -{ - unsigned int intr_stat_check; - uint64_t timeout_cnt; - volatile uint8_t expiration; - - assert(slot_id <= MHU_MAX_SLOT_ID); - arm_lock_get(); - - /* - * Make sure any previous command has finished - * and polling timeout not expired - */ - - timeout_cnt = timeout_init_us(MHU_POLL_INTR_STAT_TIMEOUT); - - do { - intr_stat_check = (mmio_read_32(address + CPU_INTR_S_STAT) & - (1 << slot_id)); - - expiration = timeout_elapsed(timeout_cnt); - - } while ((intr_stat_check != 0U) && (expiration == 0U)); - - /* - * Note: No risk of timer overflows while waiting - * for the timeout expiration. - * According to Armv8 TRM: System counter roll-over - * time of not less than 40 years - */ -} - -void mhu_secure_message_send(uintptr_t address, - unsigned int slot_id, - unsigned int message) -{ - unsigned char access_ready; - uint64_t timeout_cnt; - volatile uint8_t expiration; - - assert(slot_id <= MHU_MAX_SLOT_ID); - assert((mmio_read_32(address + CPU_INTR_S_STAT) & - (1 << slot_id)) == 0U); - - MHU_V2_ACCESS_REQUEST(address); - - timeout_cnt = timeout_init_us(MHU_POLL_INTR_STAT_TIMEOUT); - - do { - access_ready = MHU_V2_IS_ACCESS_READY(address); - expiration = timeout_elapsed(timeout_cnt); - - } while ((access_ready == 0U) && (expiration == 0U)); - - /* - * Note: No risk of timer overflows while waiting - * for the timeout expiration. - * According to Armv8 TRM: System counter roll-over - * time of not less than 40 years - */ - - mmio_write_32(address + CPU_INTR_S_SET, message); -} - -void mhu_secure_message_end(uintptr_t address, unsigned int slot_id) -{ - assert(slot_id <= MHU_MAX_SLOT_ID); - /* - * Clear any response we got by writing one in the relevant slot bit to - * the CLEAR register - */ - MHU_V2_CLEAR_REQUEST(address); - - arm_lock_release(); -} - -void __init mhu_secure_init(void) -{ - arm_lock_init(); - - /* - * The STAT register resets to zero. Ensure it is in the expected state, - * as a stale or garbage value would make us think it's a message we've - * already sent. - */ - - assert(mmio_read_32(PLAT_SDK700_MHU0_SEND + CPU_INTR_S_STAT) == 0); -} diff --git a/plat/arm/board/corstone700/drivers/mhu/mhu.h b/plat/arm/board/corstone700/drivers/mhu/mhu.h deleted file mode 100644 index 3808746..0000000 --- a/plat/arm/board/corstone700/drivers/mhu/mhu.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2019-2020, ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef MHU_H -#define MHU_H - -#define MHU_POLL_INTR_STAT_TIMEOUT 50000 /*timeout value in us*/ - -/* CPU MHU secure channel registers */ -#define CPU_INTR_S_STAT 0x00 -#define CPU_INTR_S_SET 0x0C - -/* MHUv2 Control Registers Offsets */ -#define MHU_V2_MSG_CFG_OFFSET 0xF80 -#define MHU_V2_ACCESS_REQ_OFFSET 0xF88 -#define MHU_V2_ACCESS_READY_OFFSET 0xF8C - -#define MHU_V2_ACCESS_REQUEST(addr) \ - mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x1) - -#define MHU_V2_CLEAR_REQUEST(addr) \ - mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x0) - -#define MHU_V2_IS_ACCESS_READY(addr) \ - (mmio_read_32((addr) + MHU_V2_ACCESS_READY_OFFSET) & 0x1) - -void mhu_secure_message_start(uintptr_t address, unsigned int slot_id); -void mhu_secure_message_send(uintptr_t address, - unsigned int slot_id, - unsigned int message); -void mhu_secure_message_end(uintptr_t address, unsigned int slot_id); -void mhu_secure_init(void); - -#endif /* MHU_H */ diff --git a/plat/arm/board/corstone700/include/platform_def.h b/plat/arm/board/corstone700/include/platform_def.h deleted file mode 100644 index 7799cec..0000000 --- a/plat/arm/board/corstone700/include/platform_def.h +++ /dev/null @@ -1,247 +0,0 @@ -/* - * Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef PLATFORM_DEF_H -#define PLATFORM_DEF_H - -#include -#include -#include -#include -#include -#include - -/* PL011 UART related constants */ -#ifdef V2M_IOFPGA_UART0_CLK_IN_HZ -#undef V2M_IOFPGA_UART0_CLK_IN_HZ -#endif - -#ifdef V2M_IOFPGA_UART1_CLK_IN_HZ -#undef V2M_IOFPGA_UART1_CLK_IN_HZ -#endif - -#define V2M_IOFPGA_UART0_CLK_IN_HZ 32000000 -#define V2M_IOFPGA_UART1_CLK_IN_HZ 32000000 - -/* Core/Cluster/Thread counts for Corstone700 */ -#define CORSTONE700_CLUSTER_COUNT U(1) -#define CORSTONE700_MAX_CPUS_PER_CLUSTER U(4) -#define CORSTONE700_MAX_PE_PER_CPU U(1) - -#define PLAT_ARM_CLUSTER_COUNT CORSTONE700_CLUSTER_COUNT - -#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ - CORSTONE700_MAX_CPUS_PER_CLUSTER * \ - CORSTONE700_MAX_PE_PER_CPU) - - -/* UART related constants */ -#define PLAT_ARM_BOOT_UART_BASE 0x1a510000 -#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ -#define PLAT_ARM_RUN_UART_BASE 0x1a520000 -#define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ -#define ARM_CONSOLE_BAUDRATE 115200 -#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE -#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ - -/* Memory related constants */ -#define ARM_DRAM1_BASE UL(0x80000000) -#define ARM_DRAM1_SIZE UL(0x80000000) -#define ARM_DRAM1_END (ARM_DRAM1_BASE + \ - ARM_DRAM1_SIZE - 1) -#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE -#define ARM_NS_DRAM1_SIZE ARM_DRAM1_SIZE -#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ - ARM_NS_DRAM1_SIZE - 1) -#define ARM_TRUSTED_SRAM_BASE UL(0x02000000) -#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE -#define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ -#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ - -/* The remaining Trusted SRAM is used to load the BL images */ -#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ - ARM_SHARED_RAM_SIZE) -#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ - ARM_SHARED_RAM_SIZE) - -/* - * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding - * the page reserved for fw_configs) to BL32 - */ -#define BL32_BASE (ARM_BL_RAM_BASE + PAGE_SIZE) -#define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) - -/* - * Some data must be aligned on the biggest cache line size in the platform. - * This is known only to the platform as it might have a combination of - * integrated and external caches. - */ -#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) -#define ARM_CACHE_WRITEBACK_SHIFT 6 - -/* - * To enable FW_CONFIG to be loaded by BL1, define the corresponding base - * and limit. Leave enough space for BL2 meminfo. - */ -#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) -#define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE / 2U)) - -/* - * The max number of regions like RO(code), coherent and data required by - * different BL stages which need to be mapped in the MMU. - */ -#define ARM_BL_REGIONS 2 -#define PLAT_ARM_MMAP_ENTRIES 8 -#define MAX_XLAT_TABLES 5 -#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ - ARM_BL_REGIONS) - -/* GIC related constants */ -#define PLAT_ARM_GICD_BASE 0x1C010000 -#define PLAT_ARM_GICC_BASE 0x1C02F000 - -/* MHUv2 Secure Channel receiver and sender */ -#define PLAT_SDK700_MHU0_SEND 0x1B800000 -#define PLAT_SDK700_MHU0_RECV 0x1B810000 - -/* Timer/watchdog related constants */ -#define ARM_SYS_CNTCTL_BASE UL(0x1a200000) -#define ARM_SYS_CNTREAD_BASE UL(0x1a210000) -#define ARM_SYS_TIMCTL_BASE UL(0x1a220000) -#define CORSTONE700_TIMER_BASE_FREQUENCY UL(24000000) -#define CORSTONE700_IRQ_TZ_WDOG 32 -#define CORSTONE700_IRQ_SEC_SYS_TIMER 34 - -#define PLAT_MAX_PWR_LVL 2 -/* - * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The - * power levels have a 1:1 mapping with the MPIDR affinity levels. - */ -#define ARM_PWR_LVL0 MPIDR_AFFLVL0 -#define ARM_PWR_LVL1 MPIDR_AFFLVL1 -#define ARM_PWR_LVL2 MPIDR_AFFLVL2 - -/* - * Macros for local power states in ARM platforms encoded by State-ID field - * within the power-state parameter. - */ -/* Local power state for power domains in Run state. */ -#define ARM_LOCAL_STATE_RUN U(0) -/* Local power state for retention. Valid only for CPU power domains */ -#define ARM_LOCAL_STATE_RET U(1) -/* Local power state for OFF/power-down. Valid for CPU and cluster - * power domains - */ -#define ARM_LOCAL_STATE_OFF U(2) - -#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE -#define PLAT_ARM_NSTIMER_FRAME_ID U(1) - -#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + UL(0x8000000)) - -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) - -/* - * This macro defines the deepest retention state possible. A higher state - * ID will represent an invalid or a power down state. - */ -#define PLAT_MAX_RET_STATE 1 - -/* - * This macro defines the deepest power down states possible. Any state ID - * higher than this is invalid. - */ -#define PLAT_MAX_OFF_STATE 2 - -#define PLATFORM_STACK_SIZE UL(0x440) - -#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ - ARM_SHARED_RAM_BASE, \ - ARM_SHARED_RAM_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ - ARM_NS_DRAM1_BASE, \ - ARM_NS_DRAM1_SIZE, \ - MT_MEMORY | MT_RW | MT_NS) - -#define ARM_MAP_BL_RO MAP_REGION_FLAT( \ - BL_CODE_BASE, \ - BL_CODE_END \ - - BL_CODE_BASE, \ - MT_CODE | MT_SECURE), \ - MAP_REGION_FLAT( \ - BL_RO_DATA_BASE, \ - BL_RO_DATA_END \ - - BL_RO_DATA_BASE, \ - MT_RO_DATA | MT_SECURE) -#if USE_COHERENT_MEM -#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ - BL_COHERENT_RAM_BASE, \ - BL_COHERENT_RAM_END \ - - BL_COHERENT_RAM_BASE, \ - MT_DEVICE | MT_RW | MT_SECURE) -#endif - -#define CORSTONE700_DEVICE_BASE (0x1A000000) -#define CORSTONE700_DEVICE_SIZE (0x26000000) -#define CORSTONE700_MAP_DEVICE MAP_REGION_FLAT( \ - CORSTONE700_DEVICE_BASE,\ - CORSTONE700_DEVICE_SIZE,\ - MT_DEVICE | MT_RW | MT_SECURE) - -#define ARM_IRQ_SEC_PHY_TIMER 29 - -#define ARM_IRQ_SEC_SGI_0 8 -#define ARM_IRQ_SEC_SGI_1 9 -#define ARM_IRQ_SEC_SGI_2 10 -#define ARM_IRQ_SEC_SGI_3 11 -#define ARM_IRQ_SEC_SGI_4 12 -#define ARM_IRQ_SEC_SGI_5 13 -#define ARM_IRQ_SEC_SGI_6 14 -#define ARM_IRQ_SEC_SGI_7 15 - -/* - * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 - * terminology. On a GICv2 system or mode, the lists will be merged and treated - * as Group 0 interrupts. - */ -#define ARM_G1S_IRQ_PROPS(grp) \ - INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ - (grp), GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ - (grp), GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ - (grp), GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ - (grp), GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ - (grp), GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ - (grp), GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ - (grp), GIC_INTR_CFG_EDGE) - -#define ARM_G0_IRQ_PROPS(grp) \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ - GIC_INTR_CFG_EDGE) - -/* - * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 - * terminology. On a GICv2 system or mode, the lists will be merged and treated - * as Group 0 interrupts. - */ -#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ - ARM_G1S_IRQ_PROPS(grp), \ - INTR_PROP_DESC(CORSTONE700_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \ - (grp), GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(CORSTONE700_IRQ_SEC_SYS_TIMER, \ - GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL) - -#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) - -#endif /* PLATFORM_DEF_H */ diff --git a/plat/arm/board/corstone700/platform.mk b/plat/arm/board/corstone700/platform.mk index a4d4f22..3398fba 100644 --- a/plat/arm/board/corstone700/platform.mk +++ b/plat/arm/board/corstone700/platform.mk @@ -4,6 +4,11 @@ # SPDX-License-Identifier: BSD-3-Clause # +# Making sure the corstone700 platform type is specified +ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),) + $(error TARGET_PLATFORM must be fpga or fvp) +endif + CORSTONE700_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S BL32_SOURCES += plat/arm/common/aarch32/arm_helpers.S \ @@ -12,11 +17,11 @@ lib/xlat_tables/aarch32/xlat_tables.c \ lib/xlat_tables/xlat_tables_common.c \ ${CORSTONE700_CPU_LIBS} \ - plat/arm/board/corstone700/drivers/mhu/mhu.c + plat/arm/board/corstone700/common/drivers/mhu/mhu.c -PLAT_INCLUDES := -Iplat/arm/board/corstone700/include \ +PLAT_INCLUDES := -Iplat/arm/board/corstone700/common/include \ -Iinclude/plat/arm/common \ - -Iplat/arm/board/corstone700/drivers/mhu + -Iplat/arm/board/corstone700/common/drivers/mhu NEED_BL32 := yes @@ -30,13 +35,14 @@ override NEED_BL1 := no override NEED_BL2 := no override NEED_BL2U := no +override NEED_BL33 := yes #TFA for Corstone700 starts from BL32 override RESET_TO_SP_MIN := 1 #Device tree -CORSTONE700_HW_CONFIG_DTS := fdts/corstone700.dts -CORSTONE700_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb +CORSTONE700_HW_CONFIG_DTS := fdts/corstone700_${TARGET_PLATFORM}.dts +CORSTONE700_HW_CONFIG := ${BUILD_PLAT}/fdts/corstone700_${TARGET_PLATFORM}.dtb FDT_SOURCES += ${CORSTONE700_HW_CONFIG_DTS} $(eval CORSTONE700_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(CORSTONE700_HW_CONFIG_DTS))) @@ -49,4 +55,8 @@ $(error "ARM_PRELOADED_DTB_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used.") endif $(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) + +# Adding TARGET_PLATFORM as a GCC define (-D option) +$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM}))) + include plat/arm/board/common/board_common.mk diff --git a/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk b/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk index acee6c3..75dc0f1 100644 --- a/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk +++ b/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk @@ -7,17 +7,17 @@ # SP_MIN source files specific to FVP platform BL32_SOURCES += drivers/cfi/v2m/v2m_flash.c \ lib/utils/mem_region.c \ - plat/arm/board/corstone700/corstone700_helpers.S \ - plat/arm/board/corstone700/corstone700_topology.c \ - plat/arm/board/corstone700/corstone700_security.c \ - plat/arm/board/corstone700/corstone700_plat.c \ - plat/arm/board/corstone700/corstone700_pm.c \ + plat/arm/board/corstone700/common/corstone700_helpers.S \ + plat/arm/board/corstone700/common/corstone700_topology.c \ + plat/arm/board/corstone700/common/corstone700_security.c \ + plat/arm/board/corstone700/common/corstone700_plat.c \ + plat/arm/board/corstone700/common/corstone700_pm.c \ plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c \ ${CORSTONE700_GIC_SOURCES} ifneq (${ENABLE_STACK_PROTECTOR},0) ifneq (${ENABLE_STACK_PROTECTOR},none) - BL32_SOURCES += plat/arm/board/corstone700/corstone700_stack_protector.c + BL32_SOURCES += plat/arm/board/corstone700/common/corstone700_stack_protector.c endif endif