diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst index 02f8c5f..858996c 100644 --- a/docs/getting_started/user-guide.rst +++ b/docs/getting_started/user-guide.rst @@ -1720,8 +1720,8 @@ - ``FVP_Base_Cortex-A76x4`` - ``FVP_Base_Cortex-A76AEx4`` - ``FVP_Base_Cortex-A76AEx8`` +- ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36) - ``FVP_Base_Neoverse-N1x4`` -- ``FVP_Base_Deimos`` - ``FVP_CSS_SGI-575`` (Version 11.3 build 42) - ``FVP_CSS_SGM-775`` (Version 11.3 build 42) - ``FVP_RD_E1Edge`` (Version 11.3 build 42) diff --git a/docs/index.rst b/docs/index.rst index 7ac0584..2023ceb 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -176,8 +176,8 @@ - ``FVP_Base_Cortex-A76x4`` - ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model) - ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model) +- ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36) - ``FVP_Base_Neoverse-N1x4`` (Tested with internal model) -- ``FVP_Base_Deimos`` - ``FVP_CSS_SGI-575`` (Version 11.3 build 42) - ``FVP_CSS_SGM-775`` (Version 11.3 build 42) - ``FVP_RD_E1Edge`` (Version 11.3 build 42) diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h new file mode 100644 index 0000000..0467ef3 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a77.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A77_H +#define CORTEX_A77_H + +#include + +/* Cortex-A77 MIDR */ +#define CORTEX_A77_MIDR U(0x410FD0D0) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +#endif /* CORTEX_A77_H */ diff --git a/include/lib/cpus/aarch64/cortex_deimos.h b/include/lib/cpus/aarch64/cortex_deimos.h deleted file mode 100644 index 9d024b6..0000000 --- a/include/lib/cpus/aarch64/cortex_deimos.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CORTEX_DEIMOS_H -#define CORTEX_DEIMOS_H - -#include - -#define CORTEX_DEIMOS_MIDR U(0x410FD0D0) - -/******************************************************************************* - * CPU Extended Control register specific definitions. - ******************************************************************************/ -#define CORTEX_DEIMOS_CPUECTLR_EL1 S3_0_C15_C1_4 - -/******************************************************************************* - * CPU Power Control register specific definitions. - ******************************************************************************/ -#define CORTEX_DEIMOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_DEIMOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) - -#endif /* CORTEX_DEIMOS_H */ diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S new file mode 100644 index 0000000..f3fd5e1 --- /dev/null +++ b/lib/cpus/aarch64/cortex_a77.S @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + + /* --------------------------------------------- + * HW will do the cache maintenance while powering down + * --------------------------------------------- + */ +func cortex_a77_core_pwr_dwn + /* --------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------- + */ + mrs x0, CORTEX_A77_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_A77_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_a77_core_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for Cortex-A77. Must follow AAPCS. + */ +func cortex_a77_errata_report + ret +endfunc cortex_a77_errata_report +#endif + + + /* --------------------------------------------- + * This function provides Cortex-A77 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a77_regs, "aS" +cortex_a77_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a77_cpu_reg_dump + adr x6, cortex_a77_regs + mrs x8, CORTEX_A77_CPUECTLR_EL1 + ret +endfunc cortex_a77_cpu_reg_dump + +declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \ + CPU_NO_RESET_FUNC, \ + cortex_a77_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_deimos.S b/lib/cpus/aarch64/cortex_deimos.S deleted file mode 100644 index df4c128..0000000 --- a/lib/cpus/aarch64/cortex_deimos.S +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include - -/* Hardware handled coherency */ -#if HW_ASSISTED_COHERENCY == 0 -#error "Deimos must be compiled with HW_ASSISTED_COHERENCY enabled" -#endif - -/* 64-bit only core */ -#if CTX_INCLUDE_AARCH32_REGS == 1 -#error "Cortex-Deimos supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" -#endif - - /* --------------------------------------------- - * HW will do the cache maintenance while powering down - * --------------------------------------------- - */ -func cortex_deimos_core_pwr_dwn - /* --------------------------------------------- - * Enable CPU power down bit in power control register - * --------------------------------------------- - */ - mrs x0, CORTEX_DEIMOS_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_DEIMOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_DEIMOS_CPUPWRCTLR_EL1, x0 - isb - ret -endfunc cortex_deimos_core_pwr_dwn - -#if REPORT_ERRATA -/* - * Errata printing function for Cortex Deimos. Must follow AAPCS. - */ -func cortex_deimos_errata_report - ret -endfunc cortex_deimos_errata_report -#endif - - - /* --------------------------------------------- - * This function provides Cortex-Deimos specific - * register information for crash reporting. - * It needs to return with x6 pointing to - * a list of register names in ascii and - * x8 - x15 having values of registers to be - * reported. - * --------------------------------------------- - */ -.section .rodata.cortex_deimos_regs, "aS" -cortex_deimos_regs: /* The ascii list of register names to be reported */ - .asciz "cpuectlr_el1", "" - -func cortex_deimos_cpu_reg_dump - adr x6, cortex_deimos_regs - mrs x8, CORTEX_DEIMOS_CPUECTLR_EL1 - ret -endfunc cortex_deimos_cpu_reg_dump - -declare_cpu_ops cortex_deimos, CORTEX_DEIMOS_MIDR, \ - CPU_NO_RESET_FUNC, \ - cortex_deimos_core_pwr_dwn diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 3cbdfbc..bd6812b 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -109,9 +109,9 @@ ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ lib/cpus/aarch64/cortex_a76ae.S \ + lib/cpus/aarch64/cortex_a77.S \ lib/cpus/aarch64/neoverse_n1.S \ lib/cpus/aarch64/neoverse_e1.S \ - lib/cpus/aarch64/cortex_deimos.S \ lib/cpus/aarch64/neoverse_zeus.S # AArch64/AArch32 else diff --git a/readme.rst b/readme.rst index 84c8020..6c93a4c 100644 --- a/readme.rst +++ b/readme.rst @@ -198,8 +198,8 @@ - ``FVP_Base_Cortex-A76x4`` - ``FVP_Base_Cortex-A76AEx4`` - ``FVP_Base_Cortex-A76AEx8`` +- ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36) - ``FVP_Base_Neoverse-N1x4`` -- ``FVP_Base_Deimos`` - ``FVP_CSS_SGI-575`` (Version 11.3 build 42) - ``FVP_CSS_SGM-775`` (Version 11.3 build 42) - ``FVP_RD_E1Edge`` (Version 11.3 build 42)