diff --git a/drivers/st/ddr/stm32mp1_ddr.c b/drivers/st/ddr/stm32mp1_ddr.c index e109e87..9a50546 100644 --- a/drivers/st/ddr/stm32mp1_ddr.c +++ b/drivers/st/ddr/stm32mp1_ddr.c @@ -707,7 +707,7 @@ } VERBOSE("name = %s\n", config->info.name); - VERBOSE("speed = %d MHz\n", config->info.speed); + VERBOSE("speed = %d kHz\n", config->info.speed); VERBOSE("size = 0x%x\n", config->info.size); /* DDR INIT SEQUENCE */ diff --git a/drivers/st/ddr/stm32mp1_ram.c b/drivers/st/ddr/stm32mp1_ram.c index 127b6c7..ddfc4a7 100644 --- a/drivers/st/ddr/stm32mp1_ram.c +++ b/drivers/st/ddr/stm32mp1_ram.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ @@ -25,7 +25,7 @@ static struct ddr_info ddr_priv_data; -int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint16_t mem_speed) +int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed) { unsigned long ddrphy_clk, ddr_clk, mem_speed_hz; @@ -33,10 +33,10 @@ ddrphy_clk = stm32mp1_clk_get_rate(DDRPHYC); - VERBOSE("DDR: mem_speed (%d MHz), RCC %ld MHz\n", - mem_speed, ddrphy_clk / 1000U / 1000U); + VERBOSE("DDR: mem_speed (%d kHz), RCC %ld kHz\n", + mem_speed, ddrphy_clk / 1000U); - mem_speed_hz = (uint32_t)mem_speed * 1000U * 1000U; + mem_speed_hz = mem_speed * 1000U; /* Max 10% frequency delta */ if (ddrphy_clk > mem_speed_hz) { @@ -44,9 +44,9 @@ } else { ddr_clk = mem_speed_hz - ddrphy_clk; } - if (ddr_clk > mem_speed_hz) { - ERROR("DDR expected freq %d MHz, current is %ld MHz\n", - mem_speed, ddrphy_clk / 1000U / 1000U); + if (ddr_clk > (mem_speed_hz / 10)) { + ERROR("DDR expected freq %d kHz, current is %ld kHz\n", + mem_speed, ddrphy_clk / 1000U); return -1; } return 0; @@ -208,11 +208,16 @@ return -EINVAL; } - config.info.speed = - (uint16_t)fdt_read_uint32_default(node, "st,mem-speed", - STM32MP1_DDR_SPEED_DFLT); - config.info.size = fdt_read_uint32_default(node, "st,mem-size", - STM32MP1_DDR_SIZE_DFLT); + config.info.speed = fdt_read_uint32_default(node, "st,mem-speed", 0); + if (!config.info.speed) { + VERBOSE("%s: no st,mem-speed\n", __func__); + return -EINVAL; + } + config.info.size = fdt_read_uint32_default(node, "st,mem-size", 0); + if (!config.info.size) { + VERBOSE("%s: no st,mem-size\n", __func__); + return -EINVAL; + } config.info.name = fdt_getprop(fdt, node, "st,mem-name", &len); if (config.info.name == NULL) { VERBOSE("%s: no st,mem-name\n", __func__); @@ -222,7 +227,7 @@ for (idx = 0; idx < ARRAY_SIZE(param); idx++) { ret = fdt_read_uint32_array(node, param[idx].name, - (void *)((uint32_t)&config + + (void *)((uintptr_t)&config + param[idx].offset), param[idx].size); diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c index 05f5ae1..7445d88 100644 --- a/drivers/st/mmc/stm32_sdmmc2.c +++ b/drivers/st/mmc/stm32_sdmmc2.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, STMicroelectronics - All Rights Reserved + * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -667,15 +667,15 @@ cuint++; sdmmc2_params.reset_id = fdt32_to_cpu(*cuint); - if ((fdt_getprop(fdt, sdmmc_node, "st,pin-ckin", NULL)) != NULL) { + if ((fdt_getprop(fdt, sdmmc_node, "st,use-ckin", NULL)) != NULL) { sdmmc2_params.pin_ckin = SDMMC_CLKCR_SELCLKRX_0; } - if ((fdt_getprop(fdt, sdmmc_node, "st,dirpol", NULL)) != NULL) { + if ((fdt_getprop(fdt, sdmmc_node, "st,sig-dir", NULL)) != NULL) { sdmmc2_params.dirpol = SDMMC_POWER_DIRPOL; } - if ((fdt_getprop(fdt, sdmmc_node, "st,negedge", NULL)) != NULL) { + if ((fdt_getprop(fdt, sdmmc_node, "st,neg-edge", NULL)) != NULL) { sdmmc2_params.negedge = SDMMC_CLKCR_NEGEDGE; } diff --git a/fdts/stm32mp15-ddr.dtsi b/fdts/stm32mp15-ddr.dtsi index be4e2c3..1a5c51c 100644 --- a/fdts/stm32mp15-ddr.dtsi +++ b/fdts/stm32mp15-ddr.dtsi @@ -5,7 +5,7 @@ / { soc { - ddr: ddr@0x5A003000{ + ddr: ddr@5A003000{ compatible = "st,stm32mp1-ddr"; diff --git a/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi index 58a4cdc..82e7104 100644 --- a/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi +++ b/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi @@ -3,7 +3,7 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ -/* STM32MP157C ED1 and ED2 BOARD configuration +/* STM32MP157C ED1 BOARD configuration * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology. * Reference used NT5CC256M16DP-DI from NANYA * @@ -15,10 +15,11 @@ * timing mode optimized * Scheduling/QoS options : type = 2 * address mapping : RBC + * Tc > + 85C : N */ -#define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.39" -#define DDR_MEM_SPEED 533 +#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.41" +#define DDR_MEM_SPEED 533000 #define DDR_MEM_SIZE 0x40000000 #define DDR_MSTR 0x00040401 @@ -62,7 +63,7 @@ #define DDR_ADDRMAP11 0x00000000 #define DDR_ODTCFG 0x06000600 #define DDR_ODTMAP 0x00000001 -#define DDR_SCHED 0x00001201 +#define DDR_SCHED 0x00000C01 #define DDR_SCHED1 0x00000000 #define DDR_PERFHPR1 0x01000001 #define DDR_PERFLPR1 0x08000200 @@ -74,15 +75,15 @@ #define DDR_PCCFG 0x00000010 #define DDR_PCFGR_0 0x00010000 #define DDR_PCFGW_0 0x00000000 -#define DDR_PCFGQOS0_0 0x02100B03 +#define DDR_PCFGQOS0_0 0x02100C03 #define DDR_PCFGQOS1_0 0x00800100 -#define DDR_PCFGWQOS0_0 0x01100B03 +#define DDR_PCFGWQOS0_0 0x01100C03 #define DDR_PCFGWQOS1_0 0x01000200 #define DDR_PCFGR_1 0x00010000 #define DDR_PCFGW_1 0x00000000 -#define DDR_PCFGQOS0_1 0x02100B03 -#define DDR_PCFGQOS1_1 0x00800000 -#define DDR_PCFGWQOS0_1 0x01100B03 +#define DDR_PCFGQOS0_1 0x02100C03 +#define DDR_PCFGQOS1_1 0x00800040 +#define DDR_PCFGWQOS0_1 0x01100C03 #define DDR_PCFGWQOS1_1 0x01000200 #define DDR_PGCR 0x01442E02 #define DDR_PTR0 0x0022AA5B diff --git a/fdts/stm32mp157-pinctrl.dtsi b/fdts/stm32mp157-pinctrl.dtsi index 21bd34e..9dcd7b5 100644 --- a/fdts/stm32mp157-pinctrl.dtsi +++ b/fdts/stm32mp157-pinctrl.dtsi @@ -3,13 +3,14 @@ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved * Author: Ludovic Barre for STMicroelectronics. */ - #include + / { soc { - pinctrl: pin-controller { + pinctrl: pin-controller@50002000 { #address-cells = <1>; #size-cells = <1>; + compatible = "st,stm32mp157-pinctrl"; ranges = <0 0x50002000 0xa400>; pins-are-numbered; @@ -134,7 +135,132 @@ status = "disabled"; }; - uart4_pins_a: uart4@0 { + qspi_bk1_pins_a: qspi-bk1-0 { + pins1 { + pinmux = , /* QSPI_BK1_IO0 */ + , /* QSPI_BK1_IO1 */ + , /* QSPI_BK1_IO2 */ + ; /* QSPI_BK1_IO3 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* QSPI_BK1_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_bk2_pins_a: qspi-bk2-0 { + pins1 { + pinmux = , /* QSPI_BK2_IO0 */ + , /* QSPI_BK2_IO1 */ + , /* QSPI_BK2_IO2 */ + ; /* QSPI_BK2_IO3 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* QSPI_BK2_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_clk_pins_a: qspi-clk-0 { + pins { + pinmux = ; /* QSPI_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_dir_pins_a: sdmmc1-dir-0 { + pins1 { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + ; /* SDMMC1_CDIR */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2{ + pinmux = ; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc1_dir_pins_b: sdmmc1-dir-1 { + pins1 { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + ; /* SDMMC1_CDIR */ + slew-rate = <3>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_d47_pins_a: sdmmc2-d47-0 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + uart4_pins_a: uart4-0 { pins1 { pinmux = ; /* UART4_TX */ bias-disable; @@ -147,7 +273,7 @@ }; }; - usart3_pins_a: usart3@0 { + usart3_pins_a: usart3-0 { pins1 { pinmux = , /* USART3_TX */ ; /* USART3_RTS */ @@ -161,66 +287,12 @@ bias-disable; }; }; - - sdmmc1_b4_pins_a: sdmmc1-b4@0 { - pins { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - , /* SDMMC1_CK */ - ; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc1_dir_pins_a: sdmmc1-dir@0 { - pins1 { - pinmux = , /* SDMMC1_D0DIR */ - , /* SDMMC1_D123DIR */ - ; /* SDMMC1_CDIR */ - slew-rate = <3>; - drive-push-pull; - bias-pull-up; - }; - pins2{ - pinmux = ; /* SDMMC1_CKIN */ - bias-pull-up; - }; - }; - - sdmmc2_b4_pins_a: sdmmc2-b4@0 { - pins { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC2_D1 */ - , /* SDMMC2_D2 */ - , /* SDMMC2_D3 */ - , /* SDMMC2_CK */ - ; /* SDMMC2_CMD */ - slew-rate = <3>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc2_d47_pins_a: sdmmc2-d47@0 { - pins { - pinmux = , /* SDMMC2_D4 */ - , /* SDMMC2_D5 */ - , /* SDMMC2_D6 */ - ; /* SDMMC2_D7 */ - slew-rate = <3>; - drive-push-pull; - bias-pull-up; - }; - }; }; - pinctrl_z: pin-controller-z { + pinctrl_z: pin-controller-z@54004000 { #address-cells = <1>; #size-cells = <1>; + compatible = "st,stm32mp157-z-pinctrl"; ranges = <0 0x54004000 0x400>; pins-are-numbered; @@ -236,7 +308,7 @@ status = "disabled"; }; - i2c4_pins_a: i2c4@0 { + i2c4_pins_a: i2c4-0 { pins { pinmux = , /* I2C4_SCL */ ; /* I2C4_SDA */ diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts index 0c00b13..a97e805 100644 --- a/fdts/stm32mp157c-ed1.dts +++ b/fdts/stm32mp157c-ed1.dts @@ -3,20 +3,26 @@ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved * Author: Ludovic Barre for STMicroelectronics. */ - /dts-v1/; #include "stm32mp157c.dtsi" #include "stm32mp157caa-pinctrl.dtsi" / { - model = "STMicroelectronics STM32MP157C-ED1 pmic eval daughter"; + model = "STMicroelectronics STM32MP157C eval daughter"; compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; chosen { - bootargs = "earlyprintk console=ttyS3,115200 root=/dev/ram"; - stdout-path = "serial3:115200n8"; + stdout-path = "serial0:115200n8"; }; + + aliases { + serial0 = &uart4; + }; +}; + +&clk_hse { + st,digbypass; }; &i2c4 { @@ -29,34 +35,85 @@ pmic: stpmic@33 { compatible = "st,stpmic1"; reg = <0x33>; + interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; status = "okay"; - st,main_control_register = <0x04>; - st,vin_control_register = <0xc0>; - st,usb_control_register = <0x30>; + st,main-control-register = <0x04>; + st,vin-control-register = <0xc0>; + st,usb-control-register = <0x30>; regulators { compatible = "st,stpmic1-regulators"; + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + v3v3: buck4 { regulator-name = "v3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-boot-on; + regulator-always-on; regulator-over-current-protection; - regulator-initial-mode = <8>; + regulator-initial-mode = <0>; + }; - regulator-state-standby { - regulator-suspend-microvolt = <3300000>; - regulator-unchanged-in-suspend; - regulator-mode = <8>; - }; - regulator-state-mem { - regulator-off-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + v2v8: ldo2 { + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; vdd_sd: ldo5 { @@ -64,24 +121,24 @@ regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; regulator-boot-on; + }; - regulator-state-standby { - regulator-suspend-microvolt = <2900000>; - regulator-unchanged-in-suspend; - }; - regulator-state-mem { - regulator-off-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; }; }; }; }; &iwdg2 { - instance = <2>; timeout-sec = <32>; status = "okay"; }; @@ -90,14 +147,19 @@ status = "okay"; }; +&rtc { + status = "okay"; +}; + &sdmmc1 { pinctrl-names = "default"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; broken-cd; - st,dirpol; - st,negedge; - st,pin-ckin; + st,sig-dir; + st,neg-edge; + st,use-ckin; bus-width = <4>; + vmmc-supply = <&vdd_sd>; sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; @@ -112,16 +174,17 @@ non-removable; no-sd; no-sdio; - st,dirpol; - st,negedge; + st,neg-edge; bus-width = <8>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; status = "okay"; }; &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; - resets = <&rcc UART4_R>; status = "okay"; }; @@ -157,6 +220,7 @@ /* CLOCK init */ &rcc { + secure-status = "disabled"; st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P @@ -186,7 +250,7 @@ CLK_FMC_ACLK CLK_QSPI_ACLK CLK_ETH_DISABLED - CLK_SDMMC12_PLL3R + CLK_SDMMC12_PLL4P CLK_DSI_DSIPLL CLK_STGEN_HSE CLK_USBPHY_HSE @@ -195,7 +259,7 @@ CLK_SPI45_HSI CLK_SPI6_HSI CLK_I2C46_HSI - CLK_SDMMC3_PLL3R + CLK_SDMMC3_PLL4P CLK_USBO_USBPHY CLK_ADC_CKPER CLK_CEC_LSE @@ -206,17 +270,17 @@ CLK_UART35_HSI CLK_UART6_HSI CLK_UART78_HSI - CLK_SPDIF_PLL3Q + CLK_SPDIF_PLL4P CLK_FDCAN_PLL4Q CLK_SAI1_PLL3Q CLK_SAI2_PLL3Q CLK_SAI3_PLL3Q CLK_SAI4_PLL3Q - CLK_RNG1_CSI - CLK_RNG2_CSI + CLK_RNG1_LSI + CLK_RNG2_LSI CLK_LPTIM1_PCLK1 CLK_LPTIM23_PCLK3 - CLK_LPTIM45_PCLK3 + CLK_LPTIM45_LSE >; /* VCO = 1300.0 MHz => P = 650 (CPU) */ @@ -231,15 +295,15 @@ frac = < 0x1400 >; }; - /* VCO = 786.4 MHz => P = 197, Q = 49, R = 98 */ + /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ pll3: st,pll@2 { - cfg = < 2 97 3 15 7 PQR(1,1,1) >; - frac = < 0x9ba >; + cfg = < 1 33 1 16 36 PQR(1,1,1) >; + frac = < 0x1a04 >; }; - /* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */ + /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ pll4: st,pll@3 { - cfg = < 5 126 8 8 8 PQR(1,1,1) >; + cfg = < 3 98 5 7 7 PQR(1,1,1) >; }; }; diff --git a/fdts/stm32mp157c-ev1.dts b/fdts/stm32mp157c-ev1.dts index 98a9d35..cfde8ed 100644 --- a/fdts/stm32mp157c-ev1.dts +++ b/fdts/stm32mp157c-ev1.dts @@ -3,23 +3,65 @@ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved * Author: Ludovic Barre for STMicroelectronics. */ - /dts-v1/; + #include "stm32mp157c-ed1.dts" / { - model = "STMicroelectronics STM32MP157C-EV1 pmic eval daughter on eval mother"; + model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157"; chosen { - bootargs = "earlyprintk console=ttyS3,115200 root=/dev/ram"; - stdout-path = "serial3:115200n8"; + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial1 = &usart3; + }; +}; + +&fmc { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + nand: nand@0 { + reg = <0>; + nand-on-flash-bbt; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: mx66l51235l@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + flash1: mx66l51235l@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; }; }; &usart3 { pinctrl-names = "default"; pinctrl-0 = <&usart3_pins_a>; - resets = <&rcc USART3_R>; status = "disabled"; }; diff --git a/fdts/stm32mp157c.dtsi b/fdts/stm32mp157c.dtsi index 8b13c0e..0ec7ecb 100644 --- a/fdts/stm32mp157c.dtsi +++ b/fdts/stm32mp157c.dtsi @@ -3,7 +3,7 @@ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved * Author: Ludovic Barre for STMicroelectronics. */ - +#include #include #include @@ -11,15 +11,12 @@ #address-cells = <1>; #size-cells = <1>; - aliases { - serial0 = &usart1; - serial1 = &usart2; - serial2 = &usart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &usart6; - serial6 = &uart7; - serial7 = &uart8; + intc: interrupt-controller@a0021000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xa0021000 0x1000>, + <0xa0022000 0x2000>; }; clocks { @@ -56,7 +53,7 @@ clk_i2s_ckin: i2s_ckin { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <64000000>; + clock-frequency = <0>; }; clk_dsi_phy: ck_dsi_phy { @@ -64,31 +61,28 @@ compatible = "fixed-clock"; clock-frequency = <0>; }; - - clk_usbo_48m: ck_usbo_48m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <48000000>; - }; }; soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; + interrupt-parent = <&intc>; ranges; usart2: serial@4000e000 { - compatible = "st,stm32h7-usart"; + compatible = "st,stm32h7-uart"; reg = <0x4000e000 0x400>; clocks = <&rcc USART2_K>; + resets = <&rcc USART2_R>; status = "disabled"; }; usart3: serial@4000f000 { - compatible = "st,stm32h7-usart"; + compatible = "st,stm32h7-uart"; reg = <0x4000f000 0x400>; clocks = <&rcc USART3_K>; + resets = <&rcc USART3_R>; status = "disabled"; }; @@ -96,6 +90,7 @@ compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; clocks = <&rcc UART4_K>; + resets = <&rcc UART4_R>; status = "disabled"; }; @@ -103,6 +98,7 @@ compatible = "st,stm32h7-uart"; reg = <0x40011000 0x400>; clocks = <&rcc UART5_K>; + resets = <&rcc UART5_R>; status = "disabled"; }; @@ -111,6 +107,7 @@ compatible = "st,stm32h7-uart"; reg = <0x40018000 0x400>; clocks = <&rcc UART7_K>; + resets = <&rcc UART7_R>; status = "disabled"; }; @@ -118,21 +115,23 @@ compatible = "st,stm32h7-uart"; reg = <0x40019000 0x400>; clocks = <&rcc UART8_K>; + resets = <&rcc UART8_R>; status = "disabled"; }; usart6: serial@44003000 { - compatible = "st,stm32h7-usart"; + compatible = "st,stm32h7-uart"; reg = <0x44003000 0x400>; clocks = <&rcc USART6_K>; + resets = <&rcc USART6_R>; status = "disabled"; }; sdmmc3: sdmmc@48004000 { compatible = "st,stm32-sdmmc2"; reg = <0x48004000 0x400>, <0x48005000 0x400>; - reg-names = "sdmmc", "delay"; clocks = <&rcc SDMMC3_K>; + clock-names = "apb_pclk"; resets = <&rcc SDMMC3_R>; cap-sd-highspeed; cap-mmc-highspeed; @@ -141,17 +140,34 @@ }; rcc: rcc@50000000 { - compatible = "syscon", "st,stm32mp1-rcc"; + compatible = "st,stm32mp1-rcc", "syscon"; + reg = <0x50000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; - reg = <0x50000000 0x1000>; + interrupts = ; }; - rcc_reboot: rcc-reboot@50000000 { - compatible = "syscon-reboot"; - regmap = <&rcc>; - offset = <0x404>; - mask = <0x1>; + pwr: pwr@50001000 { + compatible = "st,stm32mp1-pwr", "syscon", "simple-mfd"; + reg = <0x50001000 0x400>; + }; + + exti: interrupt-controller@5000d000 { + compatible = "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000d000 0x400>; + + /* exti_pwr is an extra interrupt controller used for + * EXTI 55 to 60. It's mapped on pwr interrupt + * controller. + */ + exti_pwr: exti-pwr { + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&pwr>; + st,irq-number = <6>; + }; }; rng1: rng@54003000 { @@ -162,13 +178,15 @@ status = "disabled"; }; - fmc_nand: fmc_nand@58002000 { - compatible = "st,stm32mp1-fmc"; + fmc: nand-controller@58002000 { + compatible = "st,stm32mp15-fmc2"; reg = <0x58002000 0x1000>, - <0x80000000 0x40000>, - <0x81000000 0x40000>, - <0x88000000 0x40000>, - <0x89000000 0x40000>; + <0x80000000 0x1000>, + <0x88010000 0x1000>, + <0x88020000 0x1000>, + <0x81000000 0x1000>, + <0x89010000 0x1000>, + <0x89020000 0x1000>; clocks = <&rcc FMC_K>; resets = <&rcc FMC_R>; status = "disabled"; @@ -177,15 +195,17 @@ qspi: qspi@58003000 { compatible = "st,stm32f469-qspi"; reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; clocks = <&rcc QSPI_K>; + resets = <&rcc QSPI_R>; status = "disabled"; }; sdmmc1: sdmmc@58005000 { compatible = "st,stm32-sdmmc2"; reg = <0x58005000 0x1000>, <0x58006000 0x1000>; - reg-names = "sdmmc", "delay"; clocks = <&rcc SDMMC1_K>; + clock-names = "apb_pclk"; resets = <&rcc SDMMC1_R>; cap-sd-highspeed; cap-mmc-highspeed; @@ -196,8 +216,8 @@ sdmmc2: sdmmc@58007000 { compatible = "st,stm32-sdmmc2"; reg = <0x58007000 0x1000>, <0x58008000 0x1000>; - reg-names = "sdmmc", "delay"; clocks = <&rcc SDMMC2_K>; + clock-names = "apb_pclk"; resets = <&rcc SDMMC2_R>; cap-sd-highspeed; cap-mmc-highspeed; @@ -205,7 +225,7 @@ status = "disabled"; }; - iwdg2: iwdg@5a002000 { + iwdg2: watchdog@5a002000 { compatible = "st,stm32mp1-iwdg"; reg = <0x5a002000 0x400>; clocks = <&rcc IWDG2>, <&rcc CK_LSI>; @@ -214,15 +234,34 @@ }; usart1: serial@5c000000 { - compatible = "st,stm32h7-usart"; + compatible = "st,stm32h7-uart"; reg = <0x5c000000 0x400>; + interrupt-names = "event", "wakeup"; + interrupts-extended = <&intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <&exti 26 1>; clocks = <&rcc USART1_K>; + resets = <&rcc USART1_R>; + status = "disabled"; + }; + + spi6: spi@5c001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x5c001000 0x400>; + interrupts = ; + clocks = <&rcc SPI6_K>; + resets = <&rcc SPI6_R>; status = "disabled"; }; i2c4: i2c@5c002000 { compatible = "st,stm32f7-i2c"; reg = <0x5c002000 0x400>; + interrupt-names = "event", "error", "wakeup"; + interrupts-extended = <&intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <&exti 24 1>; clocks = <&rcc I2C4_K>; resets = <&rcc I2C4_R>; #address-cells = <1>; @@ -235,6 +274,36 @@ reg = <0x5c004000 0x400>; clocks = <&rcc RTCAPB>, <&rcc RTC>; clock-names = "pclk", "rtc_ck"; + interrupts-extended = <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <&exti 19 1>; + status = "disabled"; + }; + + bsec: nvmem@5c005000 { + compatible = "st,stm32mp15-bsec"; + reg = <0x5c005000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ts_cal1: calib@5c { + reg = <0x5c 0x2>; + }; + ts_cal2: calib@5e { + reg = <0x5e 0x2>; + }; + }; + + i2c6: i2c@5c009000 { + compatible = "st,stm32f7-i2c"; + reg = <0x5c009000 0x400>; + interrupt-names = "event", "error", "wakeup"; + interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&exti 54 1>; + clocks = <&rcc I2C6_K>; + resets = <&rcc I2C6_R>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; }; }; diff --git a/fdts/stm32mp157caa-pinctrl.dtsi b/fdts/stm32mp157caa-pinctrl.dtsi index 774561a..9b9cd08 100644 --- a/fdts/stm32mp157caa-pinctrl.dtsi +++ b/fdts/stm32mp157caa-pinctrl.dtsi @@ -7,8 +7,8 @@ #include "stm32mp157-pinctrl.dtsi" / { soc { - pinctrl: pin-controller { - compatible = "st,stm32mp157caa-pinctrl"; + pinctrl: pin-controller@50002000 { + st,package = ; gpioa: gpio@50002000 { status = "okay"; @@ -77,8 +77,8 @@ }; }; - pinctrl_z: pin-controller-z { - compatible = "st,stm32mp157caa-z-pinctrl"; + pinctrl_z: pin-controller-z@54004000 { + st,package = ; gpioz: gpio@54004000 { status = "okay"; diff --git a/include/drivers/st/stm32mp1_ddr.h b/include/drivers/st/stm32mp1_ddr.h index 363e302..4ab37d6 100644 --- a/include/drivers/st/stm32mp1_ddr.h +++ b/include/drivers/st/stm32mp1_ddr.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ @@ -153,7 +153,7 @@ struct stm32mp1_ddr_info { const char *name; - uint16_t speed; /* in MHZ */ + uint32_t speed; /* in kHZ */ uint32_t size; /* Memory size in byte = col * row * width */ }; @@ -168,7 +168,7 @@ struct stm32mp1_ddrphy_cal p_cal; }; -int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint16_t mem_speed); +int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed); void stm32mp1_ddr_init(struct ddr_info *priv, struct stm32mp1_ddr_config *config); #endif /* STM32MP1_DDR_H */ diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h new file mode 100644 index 0000000..aa9158c --- /dev/null +++ b/include/dt-bindings/interrupt-controller/arm-gic.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ +/* + * This header provides constants for the ARM GIC. + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H + +/* interrupt specifier cell 0 */ + +#define GIC_SPI 0 +#define GIC_PPI 1 + +#define IRQ_TYPE_NONE 0 +#define IRQ_TYPE_EDGE_RISING 1 +#define IRQ_TYPE_EDGE_FALLING 2 +#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) +#define IRQ_TYPE_LEVEL_HIGH 4 +#define IRQ_TYPE_LEVEL_LOW 8 + +#endif diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h index e2f1f1b..7f6e4b9 100644 --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h @@ -32,4 +32,10 @@ #define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode)) +/* package information */ +#define STM32MP157CAA 0x1 +#define STM32MP157CAB 0x2 +#define STM32MP157CAC 0x4 +#define STM32MP157CAD 0x8 + #endif /* _DT_BINDINGS_STM32_PINFUNC_H */