diff --git a/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h b/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h new file mode 100644 index 0000000..28be8e3 --- /dev/null +++ b/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __XLAT_TABLES_AARCH32_H__ +#define __XLAT_TABLES_AARCH32_H__ + +#include +#include +#include + +#if !defined(PAGE_SIZE) +#error "PAGE_SIZE is not defined." +#endif + +/* + * In AArch32 state, the MMU only supports 4KB page granularity, which means + * that the first translation table level is either 1 or 2. Both of them are + * allowed to have block and table descriptors. See section G4.5.6 of the + * ARMv8-A Architecture Reference Manual (DDI 0487A.k) for more information. + * + * The define below specifies the first table level that allows block + * descriptors. + */ +#if PAGE_SIZE != (4 * 1024) +#error "Invalid granule size. AArch32 supports 4KB pages only." +#endif + +#define MIN_LVL_BLOCK_DESC 1 + +#define XLAT_TABLE_LEVEL_MIN U(1) + +/* + * Define the architectural limits of the virtual address space in AArch32 + * state. + * + * TTBCR.TxSZ is calculated as 32 minus the width of said address space. The + * value of TTBCR.TxSZ must be in the range 0 to 7 [1], which means that the + * virtual address space width must be in the range 32 to 25 bits. + * + * [1] See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more + * information, Section G4.6.5 + */ +#define MIN_VIRT_ADDR_SPACE_SIZE (1 << (32 - TTBCR_TxSZ_MAX)) +#define MAX_VIRT_ADDR_SPACE_SIZE (ULL(1) << (32 - TTBCR_TxSZ_MIN)) + +/* + * Here we calculate the initial lookup level from the value of the given + * virtual address space size. For a 4 KB page size, + * - level 1 supports virtual address spaces of widths 32 to 31 bits; + * - level 2 from 30 to 25. + * + * Wider or narrower address spaces are not supported. As a result, level 3 + * cannot be used as the initial lookup level with 4 KB granularity. + * See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more + * information, Section G4.6.5 + * + * For example, for a 31-bit address space (i.e. virt_addr_space_size == + * 1 << 31), TTBCR.TxSZ will be programmed to (32 - 31) = 1. According to Table + * G4-5 in the ARM ARM, the initial lookup level for an address space like that + * is 1. + * + * Note that this macro assumes that the given virtual address space size is + * valid. Therefore, the caller is expected to check it is the case using the + * CHECK_VIRT_ADDR_SPACE_SIZE() macro first. + */ +#define GET_XLAT_TABLE_LEVEL_BASE(virt_addr_space_size) \ + (((virt_addr_space_size) > (1 << L1_XLAT_ADDRESS_SHIFT)) ? 1 : 2) + +#endif /* __XLAT_TABLES_AARCH32_H__ */ diff --git a/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h b/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h new file mode 100644 index 0000000..9cad035 --- /dev/null +++ b/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __XLAT_TABLES_AARCH64_H__ +#define __XLAT_TABLES_AARCH64_H__ + +#include +#include +#include + +#if !defined(PAGE_SIZE) +#error "PAGE_SIZE is not defined." +#endif + +/* + * In AArch64 state, the MMU may support 4 KB, 16 KB and 64 KB page + * granularity. For 4KB granularity, a level 0 table descriptor doesn't support + * block translation. For 16KB, the same thing happens to levels 0 and 1. For + * 64KB, same for level 1. See section D4.3.1 of the ARMv8-A Architecture + * Reference Manual (DDI 0487A.k) for more information. + * + * The define below specifies the first table level that allows block + * descriptors. + */ +#if PAGE_SIZE == (4 * 1024) +# define MIN_LVL_BLOCK_DESC 1 +#elif PAGE_SIZE == (16 * 1024) || PAGE_SIZE == (64 * 1024) +# define MIN_LVL_BLOCK_DESC 2 +#endif + +#define XLAT_TABLE_LEVEL_MIN U(0) + +/* + * Define the architectural limits of the virtual address space in AArch64 + * state. + * + * TCR.TxSZ is calculated as 64 minus the width of said address space. + * The value of TCR.TxSZ must be in the range 16 to 39 [1], which means that + * the virtual address space width must be in the range 48 to 25 bits. + * + * [1] See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more + * information: + * Page 1730: 'Input address size', 'For all translation stages'. + */ +#define MIN_VIRT_ADDR_SPACE_SIZE (1 << (64 - TCR_TxSZ_MAX)) +#define MAX_VIRT_ADDR_SPACE_SIZE (ULL(1) << (64 - TCR_TxSZ_MIN)) + +/* + * Here we calculate the initial lookup level from the value of the given + * virtual address space size. For a 4 KB page size, + * - level 0 supports virtual address spaces of widths 48 to 40 bits; + * - level 1 from 39 to 31; + * - level 2 from 30 to 25. + * + * Wider or narrower address spaces are not supported. As a result, level 3 + * cannot be used as initial lookup level with 4 KB granularity. See section + * D4.2.5 in the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more + * information. + * + * For example, for a 35-bit address space (i.e. virt_addr_space_size == + * 1 << 35), TCR.TxSZ will be programmed to (64 - 35) = 29. According to Table + * D4-11 in the ARM ARM, the initial lookup level for an address space like that + * is 1. + * + * Note that this macro assumes that the given virtual address space size is + * valid. Therefore, the caller is expected to check it is the case using the + * CHECK_VIRT_ADDR_SPACE_SIZE() macro first. + */ +#define GET_XLAT_TABLE_LEVEL_BASE(virt_addr_space_size) \ + (((virt_addr_space_size) > (ULL(1) << L0_XLAT_ADDRESS_SHIFT)) \ + ? 0 \ + : (((virt_addr_space_size) > (1 << L1_XLAT_ADDRESS_SHIFT)) ? 1 : 2)) + +#endif /* __XLAT_TABLES_AARCH64_H__ */ diff --git a/include/lib/xlat_tables/xlat_tables_arch.h b/include/lib/xlat_tables/xlat_tables_arch.h new file mode 100644 index 0000000..165b161 --- /dev/null +++ b/include/lib/xlat_tables/xlat_tables_arch.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __XLAT_TABLES_ARCH_H__ +#define __XLAT_TABLES_ARCH_H__ + +#ifdef AARCH32 +#include "aarch32/xlat_tables_aarch32.h" +#else +#include "aarch64/xlat_tables_aarch64.h" +#endif + +/* + * Evaluates to 1 if the given virtual address space size is valid, or 0 if it's + * not. + * + * A valid size is one that is a power of 2 and is within the architectural + * limits. Not that these limits are different for AArch32 and AArch64. + */ +#define CHECK_VIRT_ADDR_SPACE_SIZE(size) \ + (((size) >= MIN_VIRT_ADDR_SPACE_SIZE) && \ + ((size) <= MAX_VIRT_ADDR_SPACE_SIZE) && \ + IS_POWER_OF_TWO(size)) + +/* + * Evaluates to 1 if the given physical address space size is a power of 2, + * or 0 if it's not. + */ +#define CHECK_PHY_ADDR_SPACE_SIZE(size) \ + (IS_POWER_OF_TWO(size)) + +/* + * Compute the number of entries required at the initial lookup level to address + * the whole virtual address space. + */ +#define GET_NUM_BASE_LEVEL_ENTRIES(addr_space_size) \ + ((addr_space_size) >> \ + XLAT_ADDR_SHIFT(GET_XLAT_TABLE_LEVEL_BASE(addr_space_size))) + +#endif /* __XLAT_TABLES_ARCH_H__ */ diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h index 4b993a0..779532e 100644 --- a/include/lib/xlat_tables/xlat_tables_defs.h +++ b/include/lib/xlat_tables/xlat_tables_defs.h @@ -59,12 +59,6 @@ #define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */ #define XLAT_TABLE_SIZE (U(1) << XLAT_TABLE_SIZE_SHIFT) -#ifdef AARCH32 -#define XLAT_TABLE_LEVEL_MIN U(1) -#else -#define XLAT_TABLE_LEVEL_MIN U(0) -#endif /* AARCH32 */ - #define XLAT_TABLE_LEVEL_MAX U(3) /* Values for number of entries in each MMU translation table */ diff --git a/lib/xlat_tables/aarch32/xlat_tables.c b/lib/xlat_tables/aarch32/xlat_tables.c index 9c15624..71db2d5 100644 --- a/lib/xlat_tables/aarch32/xlat_tables.c +++ b/lib/xlat_tables/aarch32/xlat_tables.c @@ -7,56 +7,17 @@ #include #include #include -#include #include #include +#include #include #include "../xlat_tables_private.h" -/* - * Each platform can define the size of the virtual address space, which is - * defined in PLAT_VIRT_ADDR_SPACE_SIZE. TTBCR.TxSZ is calculated as 32 minus - * the width of said address space. The value of TTBCR.TxSZ must be in the - * range 0 to 7 [1], which means that the virtual address space width must be - * in the range 32 to 25 bits. - * - * Here we calculate the initial lookup level from the value of - * PLAT_VIRT_ADDR_SPACE_SIZE. For a 4 KB page size, level 1 supports virtual - * address spaces of widths 32 to 31 bits, and level 2 from 30 to 25. Wider or - * narrower address spaces are not supported. As a result, level 3 cannot be - * used as initial lookup level with 4 KB granularity [1]. - * - * For example, for a 31-bit address space (i.e. PLAT_VIRT_ADDR_SPACE_SIZE == - * 1 << 31), TTBCR.TxSZ will be programmed to (32 - 31) = 1. According to Table - * G4-5 in the ARM ARM, the initial lookup level for an address space like that - * is 1. - * - * See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more - * information: - * [1] Section G4.6.5 - */ +#define XLAT_TABLE_LEVEL_BASE \ + GET_XLAT_TABLE_LEVEL_BASE(PLAT_VIRT_ADDR_SPACE_SIZE) -#if PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << (32 - TTBCR_TxSZ_MIN)) - -# error "PLAT_VIRT_ADDR_SPACE_SIZE is too big." - -#elif PLAT_VIRT_ADDR_SPACE_SIZE > (1 << L1_XLAT_ADDRESS_SHIFT) - -# define XLAT_TABLE_LEVEL_BASE 1 -# define NUM_BASE_LEVEL_ENTRIES \ - (PLAT_VIRT_ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT) - -#elif PLAT_VIRT_ADDR_SPACE_SIZE >= (1 << (32 - TTBCR_TxSZ_MAX)) - -# define XLAT_TABLE_LEVEL_BASE 2 -# define NUM_BASE_LEVEL_ENTRIES \ - (PLAT_VIRT_ADDR_SPACE_SIZE >> L2_XLAT_ADDRESS_SHIFT) - -#else - -# error "PLAT_VIRT_ADDR_SPACE_SIZE is too small." - -#endif +#define NUM_BASE_LEVEL_ENTRIES \ + GET_NUM_BASE_LEVEL_ENTRIES(PLAT_VIRT_ADDR_SPACE_SIZE) static uint64_t base_xlation_table[NUM_BASE_LEVEL_ENTRIES] __aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t)); diff --git a/lib/xlat_tables/aarch64/xlat_tables.c b/lib/xlat_tables/aarch64/xlat_tables.c index 309cb9b..4125651 100644 --- a/lib/xlat_tables/aarch64/xlat_tables.c +++ b/lib/xlat_tables/aarch64/xlat_tables.c @@ -8,66 +8,19 @@ #include #include #include -#include #include #include #include #include #include +#include #include "../xlat_tables_private.h" -/* - * Each platform can define the size of the virtual address space, which is - * defined in PLAT_VIRT_ADDR_SPACE_SIZE. TCR.TxSZ is calculated as 64 minus the - * width of said address space. The value of TCR.TxSZ must be in the range 16 - * to 39 [1], which means that the virtual address space width must be in the - * range 48 to 25 bits. - * - * Here we calculate the initial lookup level from the value of - * PLAT_VIRT_ADDR_SPACE_SIZE. For a 4 KB page size, level 0 supports virtual - * address spaces of widths 48 to 40 bits, level 1 from 39 to 31, and level 2 - * from 30 to 25. Wider or narrower address spaces are not supported. As a - * result, level 3 cannot be used as initial lookup level with 4 KB - * granularity. [2] - * - * For example, for a 35-bit address space (i.e. PLAT_VIRT_ADDR_SPACE_SIZE == - * 1 << 35), TCR.TxSZ will be programmed to (64 - 35) = 29. According to Table - * D4-11 in the ARM ARM, the initial lookup level for an address space like - * that is 1. - * - * See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more - * information: - * [1] Page 1730: 'Input address size', 'For all translation stages'. - * [2] Section D4.2.5 - */ +#define XLAT_TABLE_LEVEL_BASE \ + GET_XLAT_TABLE_LEVEL_BASE(PLAT_VIRT_ADDR_SPACE_SIZE) -#if PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << (64 - TCR_TxSZ_MIN)) - -# error "PLAT_VIRT_ADDR_SPACE_SIZE is too big." - -#elif PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << L0_XLAT_ADDRESS_SHIFT) - -# define XLAT_TABLE_LEVEL_BASE 0 -# define NUM_BASE_LEVEL_ENTRIES \ - (PLAT_VIRT_ADDR_SPACE_SIZE >> L0_XLAT_ADDRESS_SHIFT) - -#elif PLAT_VIRT_ADDR_SPACE_SIZE > (1 << L1_XLAT_ADDRESS_SHIFT) - -# define XLAT_TABLE_LEVEL_BASE 1 -# define NUM_BASE_LEVEL_ENTRIES \ - (PLAT_VIRT_ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT) - -#elif PLAT_VIRT_ADDR_SPACE_SIZE >= (1 << (64 - TCR_TxSZ_MAX)) - -# define XLAT_TABLE_LEVEL_BASE 2 -# define NUM_BASE_LEVEL_ENTRIES \ - (PLAT_VIRT_ADDR_SPACE_SIZE >> L2_XLAT_ADDRESS_SHIFT) - -#else - -# error "PLAT_VIRT_ADDR_SPACE_SIZE is too small." - -#endif +#define NUM_BASE_LEVEL_ENTRIES \ + GET_NUM_BASE_LEVEL_ENTRIES(PLAT_VIRT_ADDR_SPACE_SIZE) static uint64_t base_xlation_table[NUM_BASE_LEVEL_ENTRIES] __aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t)); diff --git a/lib/xlat_tables/xlat_tables_private.h b/lib/xlat_tables/xlat_tables_private.h index b5c3ac8..50d6bd5 100644 --- a/lib/xlat_tables/xlat_tables_private.h +++ b/lib/xlat_tables/xlat_tables_private.h @@ -9,7 +9,7 @@ #include #include -#include +#include /* * If the platform hasn't defined a physical and a virtual address space size @@ -28,41 +28,14 @@ # endif #endif -/* The virtual and physical address space sizes must be powers of two. */ -CASSERT(IS_POWER_OF_TWO(PLAT_VIRT_ADDR_SPACE_SIZE), +CASSERT(CHECK_VIRT_ADDR_SPACE_SIZE(PLAT_VIRT_ADDR_SPACE_SIZE), assert_valid_virt_addr_space_size); -CASSERT(IS_POWER_OF_TWO(PLAT_PHY_ADDR_SPACE_SIZE), + +CASSERT(CHECK_PHY_ADDR_SPACE_SIZE(PLAT_PHY_ADDR_SPACE_SIZE), assert_valid_phy_addr_space_size); -/* - * In AArch32 state, the MMU only supports 4KB page granularity, which means - * that the first translation table level is either 1 or 2. Both of them are - * allowed to have block and table descriptors. See section G4.5.6 of the - * ARMv8-A Architecture Reference Manual (DDI 0487A.k) for more information. - * - * In AArch64 state, the MMU may support 4 KB, 16 KB and 64 KB page - * granularity. For 4KB granularity, a level 0 table descriptor doesn't support - * block translation. For 16KB, the same thing happens to levels 0 and 1. For - * 64KB, same for level 1. See section D4.3.1 of the ARMv8-A Architecture - * Reference Manual (DDI 0487A.k) for more information. - * - * The define below specifies the first table level that allows block - * descriptors. - */ - -#ifdef AARCH32 - -# define XLAT_BLOCK_LEVEL_MIN 1 - -#else /* if AArch64 */ - -# if PAGE_SIZE == (4*1024) /* 4KB */ -# define XLAT_BLOCK_LEVEL_MIN 1 -# else /* 16KB or 64KB */ -# define XLAT_BLOCK_LEVEL_MIN 2 -# endif - -#endif /* AARCH32 */ +/* Alias to retain compatibility with the old #define name */ +#define XLAT_BLOCK_LEVEL_MIN MIN_LVL_BLOCK_DESC void print_mmap(void); diff --git a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.h b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.h deleted file mode 100644 index f75ab79..0000000 --- a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __XLAT_TABLES_ARCH_H__ -#define __XLAT_TABLES_ARCH_H__ - -#include -#include -#include -#include "../xlat_tables_private.h" - -/* - * In AArch32 state, the MMU only supports 4KB page granularity, which means - * that the first translation table level is either 1 or 2. Both of them are - * allowed to have block and table descriptors. See section G4.5.6 of the - * ARMv8-A Architecture Reference Manual (DDI 0487A.k) for more information. - * - * The define below specifies the first table level that allows block - * descriptors. - */ - -#define MIN_LVL_BLOCK_DESC 1 - -/* - * Each platform can define the size of the virtual address space, which is - * defined in PLAT_VIRT_ADDR_SPACE_SIZE. TTBCR.TxSZ is calculated as 32 minus - * the width of said address space. The value of TTBCR.TxSZ must be in the - * range 0 to 7 [1], which means that the virtual address space width must be - * in the range 32 to 25 bits. - * - * Here we calculate the initial lookup level from the value of - * PLAT_VIRT_ADDR_SPACE_SIZE. For a 4 KB page size, level 1 supports virtual - * address spaces of widths 32 to 31 bits, and level 2 from 30 to 25. Wider or - * narrower address spaces are not supported. As a result, level 3 cannot be - * used as initial lookup level with 4 KB granularity [1]. - * - * For example, for a 31-bit address space (i.e. PLAT_VIRT_ADDR_SPACE_SIZE == - * 1 << 31), TTBCR.TxSZ will be programmed to (32 - 31) = 1. According to Table - * G4-5 in the ARM ARM, the initial lookup level for an address space like that - * is 1. - * - * See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more - * information: - * [1] Section G4.6.5 - */ - -#if PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << (32 - TTBCR_TxSZ_MIN)) - -# error "PLAT_VIRT_ADDR_SPACE_SIZE is too big." - -#elif PLAT_VIRT_ADDR_SPACE_SIZE > (1 << L1_XLAT_ADDRESS_SHIFT) - -# define XLAT_TABLE_LEVEL_BASE 1 -# define NUM_BASE_LEVEL_ENTRIES \ - (PLAT_VIRT_ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT) - -#elif PLAT_VIRT_ADDR_SPACE_SIZE >= (1 << (32 - TTBCR_TxSZ_MAX)) - -# define XLAT_TABLE_LEVEL_BASE 2 -# define NUM_BASE_LEVEL_ENTRIES \ - (PLAT_VIRT_ADDR_SPACE_SIZE >> L2_XLAT_ADDRESS_SHIFT) - -#else - -# error "PLAT_VIRT_ADDR_SPACE_SIZE is too small." - -#endif - -#endif /* __XLAT_TABLES_ARCH_H__ */ diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.h b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.h deleted file mode 100644 index caccb73..0000000 --- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __XLAT_TABLES_ARCH_H__ -#define __XLAT_TABLES_ARCH_H__ - -#include -#include -#include -#include "../xlat_tables_private.h" - -/* - * In AArch64 state, the MMU may support 4 KB, 16 KB and 64 KB page - * granularity. For 4KB granularity, a level 0 table descriptor doesn't support - * block translation. For 16KB, the same thing happens to levels 0 and 1. For - * 64KB, same for level 1. See section D4.3.1 of the ARMv8-A Architecture - * Reference Manual (DDI 0487A.k) for more information. - * - * The define below specifies the first table level that allows block - * descriptors. - */ - -#if PAGE_SIZE == (4*1024) /* 4KB */ -# define MIN_LVL_BLOCK_DESC 1 -#else /* 16KB or 64KB */ -# define MIN_LVL_BLOCK_DESC 2 -#endif - -/* - * Each platform can define the size of the virtual address space, which is - * defined in PLAT_VIRT_ADDR_SPACE_SIZE. TCR.TxSZ is calculated as 64 minus the - * width of said address space. The value of TCR.TxSZ must be in the range 16 - * to 39 [1], which means that the virtual address space width must be in the - * range 48 to 25 bits. - * - * Here we calculate the initial lookup level from the value of - * PLAT_VIRT_ADDR_SPACE_SIZE. For a 4 KB page size, level 0 supports virtual - * address spaces of widths 48 to 40 bits, level 1 from 39 to 31, and level 2 - * from 30 to 25. Wider or narrower address spaces are not supported. As a - * result, level 3 cannot be used as initial lookup level with 4 KB - * granularity. [2] - * - * For example, for a 35-bit address space (i.e. PLAT_VIRT_ADDR_SPACE_SIZE == - * 1 << 35), TCR.TxSZ will be programmed to (64 - 35) = 29. According to Table - * D4-11 in the ARM ARM, the initial lookup level for an address space like - * that is 1. - * - * See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more - * information: - * [1] Page 1730: 'Input address size', 'For all translation stages'. - * [2] Section D4.2.5 - */ - -#if PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << (64 - TCR_TxSZ_MIN)) - -# error "PLAT_VIRT_ADDR_SPACE_SIZE is too big." - -#elif PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << L0_XLAT_ADDRESS_SHIFT) - -# define XLAT_TABLE_LEVEL_BASE 0 -# define NUM_BASE_LEVEL_ENTRIES \ - (PLAT_VIRT_ADDR_SPACE_SIZE >> L0_XLAT_ADDRESS_SHIFT) - -#elif PLAT_VIRT_ADDR_SPACE_SIZE > (1 << L1_XLAT_ADDRESS_SHIFT) - -# define XLAT_TABLE_LEVEL_BASE 1 -# define NUM_BASE_LEVEL_ENTRIES \ - (PLAT_VIRT_ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT) - -#elif PLAT_VIRT_ADDR_SPACE_SIZE >= (1 << (64 - TCR_TxSZ_MAX)) - -# define XLAT_TABLE_LEVEL_BASE 2 -# define NUM_BASE_LEVEL_ENTRIES \ - (PLAT_VIRT_ADDR_SPACE_SIZE >> L2_XLAT_ADDRESS_SHIFT) - -#else - -# error "PLAT_VIRT_ADDR_SPACE_SIZE is too small." - -#endif - -#endif /* __XLAT_TABLES_ARCH_H__ */ diff --git a/lib/xlat_tables_v2/xlat_tables_common.c b/lib/xlat_tables_v2/xlat_tables_common.c index f20bf93..fce6017 100644 --- a/lib/xlat_tables_v2/xlat_tables_common.c +++ b/lib/xlat_tables_v2/xlat_tables_common.c @@ -15,15 +15,42 @@ #include #include #include +#include #include -#ifdef AARCH32 -# include "aarch32/xlat_tables_arch.h" -#else -# include "aarch64/xlat_tables_arch.h" -#endif + #include "xlat_tables_private.h" /* + * Each platform can define the size of its physical and virtual address spaces. + * If the platform hasn't defined one or both of them, default to + * ADDR_SPACE_SIZE. The latter is deprecated, though. + */ +#if ERROR_DEPRECATED +# ifdef ADDR_SPACE_SIZE +# error "ADDR_SPACE_SIZE is deprecated. Use PLAT_xxx_ADDR_SPACE_SIZE instead." +# endif +#elif defined(ADDR_SPACE_SIZE) +# ifndef PLAT_PHY_ADDR_SPACE_SIZE +# define PLAT_PHY_ADDR_SPACE_SIZE ADDR_SPACE_SIZE +# endif +# ifndef PLAT_VIRT_ADDR_SPACE_SIZE +# define PLAT_VIRT_ADDR_SPACE_SIZE ADDR_SPACE_SIZE +# endif +#endif + +CASSERT(CHECK_VIRT_ADDR_SPACE_SIZE(PLAT_VIRT_ADDR_SPACE_SIZE), + assert_invalid_virtual_addr_space_size); + +CASSERT(CHECK_PHY_ADDR_SPACE_SIZE(PLAT_PHY_ADDR_SPACE_SIZE), + assert_invalid_physical_addr_space_size); + +#define NUM_BASE_LEVEL_ENTRIES \ + GET_NUM_BASE_LEVEL_ENTRIES(PLAT_VIRT_ADDR_SPACE_SIZE) + +#define XLAT_TABLE_LEVEL_BASE \ + GET_XLAT_TABLE_LEVEL_BASE(PLAT_VIRT_ADDR_SPACE_SIZE) + +/* * Private variables used by the TF */ static mmap_region_t tf_mmap[MAX_MMAP_REGIONS + 1]; diff --git a/lib/xlat_tables_v2/xlat_tables_internal.c b/lib/xlat_tables_v2/xlat_tables_internal.c index 91e02d3..a3a98d1 100644 --- a/lib/xlat_tables_v2/xlat_tables_internal.c +++ b/lib/xlat_tables_v2/xlat_tables_internal.c @@ -15,12 +15,10 @@ #include #include #include +#include +#include #include -#ifdef AARCH32 -# include "aarch32/xlat_tables_arch.h" -#else -# include "aarch64/xlat_tables_arch.h" -#endif + #include "xlat_tables_private.h" #if PLAT_XLAT_TABLES_DYNAMIC diff --git a/lib/xlat_tables_v2/xlat_tables_private.h b/lib/xlat_tables_v2/xlat_tables_private.h index 83e0b6e..83aa5b1 100644 --- a/lib/xlat_tables_v2/xlat_tables_private.h +++ b/lib/xlat_tables_v2/xlat_tables_private.h @@ -7,32 +7,8 @@ #ifndef __XLAT_TABLES_PRIVATE_H__ #define __XLAT_TABLES_PRIVATE_H__ -#include #include -#include - -/* - * If the platform hasn't defined a physical and a virtual address space size - * default to ADDR_SPACE_SIZE. - */ -#if ERROR_DEPRECATED -# ifdef ADDR_SPACE_SIZE -# error "ADDR_SPACE_SIZE is deprecated. Use PLAT_xxx_ADDR_SPACE_SIZE instead." -# endif -#elif defined(ADDR_SPACE_SIZE) -# ifndef PLAT_PHY_ADDR_SPACE_SIZE -# define PLAT_PHY_ADDR_SPACE_SIZE ADDR_SPACE_SIZE -# endif -# ifndef PLAT_VIRT_ADDR_SPACE_SIZE -# define PLAT_VIRT_ADDR_SPACE_SIZE ADDR_SPACE_SIZE -# endif -#endif - -/* The virtual and physical address space sizes must be powers of two. */ -CASSERT(IS_POWER_OF_TWO(PLAT_VIRT_ADDR_SPACE_SIZE), - assert_valid_virt_addr_space_size); -CASSERT(IS_POWER_OF_TWO(PLAT_PHY_ADDR_SPACE_SIZE), - assert_valid_phy_addr_space_size); +#include /* Struct that holds all information about the translation tables. */ typedef struct {