diff --git a/include/lib/coreboot.h b/include/lib/coreboot.h index dda3173..0aa6579 100644 --- a/include/lib/coreboot.h +++ b/include/lib/coreboot.h @@ -39,7 +39,7 @@ CB_MEM_TABLE = 16, } coreboot_memory_t; -coreboot_memory_t coreboot_get_memory_type(uintptr_t address); +coreboot_memory_t coreboot_get_memory_type(uintptr_t start, size_t size); void coreboot_table_setup(void *base); #endif /* COREBOOT_H */ diff --git a/lib/coreboot/coreboot_table.c b/lib/coreboot/coreboot_table.c index c4cd1d7..fb31ef1 100644 --- a/lib/coreboot/coreboot_table.c +++ b/lib/coreboot/coreboot_table.c @@ -89,7 +89,7 @@ CONSOLE_FLAG_CRASH); } -coreboot_memory_t coreboot_get_memory_type(uintptr_t address) +coreboot_memory_t coreboot_get_memory_type(uintptr_t start, size_t size) { int i; @@ -98,9 +98,11 @@ if (range->type == CB_MEM_NONE) break; /* end of table reached */ - if (address >= range->start && - address - range->start < range->size) + if ((start >= range->start) && + (start - range->start < range->size) && + (size <= range->size - (start - range->start))) { return range->type; + } } return CB_MEM_NONE; diff --git a/plat/qti/common/inc/qti_board_def.h b/plat/qti/common/inc/qti_board_def.h index 4c84661..c95e4c0 100644 --- a/plat/qti/common/inc/qti_board_def.h +++ b/plat/qti/common/inc/qti_board_def.h @@ -12,6 +12,14 @@ * development platforms */ +/* + * Defines used to retrieve QTI SOC Version + */ +#define JEDEC_QTI_BKID U(0x0) +#define JEDEC_QTI_MFID U(0x70) +#define QTI_SOC_CONTINUATION_SHIFT U(24) +#define QTI_SOC_IDENTIFICATION_SHIFT U(16) + /* Size of cacheable stacks */ #define PLATFORM_STACK_SIZE 0x1000 diff --git a/plat/qti/common/src/qti_common.c b/plat/qti/common/src/qti_common.c index ff0fa30..9355eb7 100644 --- a/plat/qti/common/src/qti_common.c +++ b/plat/qti/common/src/qti_common.c @@ -11,7 +11,10 @@ #include #include +#include +#include #include +#include #include #include @@ -146,3 +149,46 @@ qti_align_mem_region(base_va, size, &base_va, &size); return mmap_remove_dynamic_region(base_va, size); } + +/* + * This function returns soc version which mainly consist of below fields + * + * soc_version[30:24] = JEP-106 continuation code for the SiP + * soc_version[23:16] = JEP-106 identification code with parity bit for the SiP + * soc_version[0:15] = Implementation defined SoC ID + */ +int32_t plat_get_soc_version(void) +{ + uint32_t soc_version = (QTI_SOC_VERSION & QTI_SOC_VERSION_MASK); + uint32_t jep106az_code = (JEDEC_QTI_BKID << QTI_SOC_CONTINUATION_SHIFT) + | (JEDEC_QTI_MFID << QTI_SOC_IDENTIFICATION_SHIFT); + return (int32_t)(jep106az_code | (soc_version)); +} + +/* + * This function returns soc revision in below format + * + * soc_revision[0:30] = SOC revision of specific SOC + */ +int32_t plat_get_soc_revision(void) +{ + return mmio_read_32(QTI_SOC_REVISION_REG) & QTI_SOC_REVISION_MASK; +} + +/***************************************************************************** + * plat_smccc_feature_available() - This function checks whether SMCCC feature + * is availabile for the platform or not. + * @fid: SMCCC function id + * + * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and + * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. + *****************************************************************************/ +int32_t plat_smccc_feature_available(u_register_t fid) +{ + switch (fid) { + case SMCCC_ARCH_SOC_ID: + return SMC_ARCH_CALL_SUCCESS; + default: + return SMC_ARCH_CALL_NOT_SUPPORTED; + } +} diff --git a/plat/qti/common/src/qti_syscall.c b/plat/qti/common/src/qti_syscall.c index 27c4895..a7601b6 100644 --- a/plat/qti/common/src/qti_syscall.c +++ b/plat/qti/common/src/qti_syscall.c @@ -27,7 +27,7 @@ */ #define QTI_SIP_SVC_CALL_COUNT_ID U(0x0200ff00) #define QTI_SIP_SVC_UID_ID U(0x0200ff01) -/* 0x8200ff02 is reserved */ +/* 0x8200ff02 is reserved*/ #define QTI_SIP_SVC_VERSION_ID U(0x0200ff03) /* @@ -97,37 +97,52 @@ || (src_vm_list_cnt >= QTI_VM_LAST) || (dst_vm_list_cnt == 0) || (dst_vm_list_cnt >= QTI_VM_LAST) || (u_num_mappings == 0) || u_num_mappings > QTI_VM_MAX_LIST_SIZE) { + ERROR("vm count is 0 or more then QTI_VM_LAST or empty list\n"); + ERROR("source_vm_list %p dest_vm_list %p mem_info %p src_vm_list_cnt %u dst_vm_list_cnt %u u_num_mappings %u\n", + source_vm_list, dest_vm_list, mem_info, + (unsigned int)src_vm_list_cnt, + (unsigned int)dst_vm_list_cnt, + (unsigned int)u_num_mappings); return false; } for (i = 0; i < u_num_mappings; i++) { if ((mem_info[i].mem_addr & (SIZE4K - 1)) + || (mem_info[i].mem_size == 0) || (mem_info[i].mem_size & (SIZE4K - 1))) { + ERROR("mem_info passed buffer 0x%x or size 0x%x is not 4k aligned\n", + (unsigned int)mem_info[i].mem_addr, + (unsigned int)mem_info[i].mem_size); return false; } if ((mem_info[i].mem_addr + mem_info[i].mem_size) < mem_info[i].mem_addr) { + ERROR("overflow in mem_addr 0x%x add mem_size 0x%x\n", + (unsigned int)mem_info[i].mem_addr, + (unsigned int)mem_info[i].mem_size); return false; } - if (coreboot_get_memory_type(mem_info[i].mem_addr) != - CB_MEM_RAM) { + coreboot_memory_t mem_type = coreboot_get_memory_type( + mem_info[i].mem_addr, + mem_info[i].mem_size); + if (mem_type != CB_MEM_RAM && mem_type != CB_MEM_RESERVED) { + ERROR("memory region not in CB MEM RAM or RESERVED area: region start 0x%x size 0x%x\n", + (unsigned int)mem_info[i].mem_addr, + (unsigned int)mem_info[i].mem_size); return false; } - - if (coreboot_get_memory_type - (mem_info[i].mem_addr + mem_info[i].mem_size) != - CB_MEM_RAM) { - return false; - } - } for (i = 0; i < src_vm_list_cnt; i++) { if (source_vm_list[i] >= QTI_VM_LAST) { + ERROR("source_vm_list[%d] 0x%x is more then QTI_VM_LAST\n", + i, (unsigned int)source_vm_list[i]); return false; } } for (i = 0; i < dst_vm_list_cnt; i++) { if (dest_vm_list[i].dst_vm >= QTI_VM_LAST) { + ERROR("dest_vm_list[%d] 0x%x is more then QTI_VM_LAST\n", + i, (unsigned int)dest_vm_list[i].dst_vm); return false; } } @@ -150,6 +165,7 @@ } /* Validate input arg count & retrieve arg3-6 from NS Buffer. */ if ((x1 != QTI_SIP_SVC_MEM_ASSIGN_PARAM_ID) || (x5 == 0x0)) { + ERROR("invalid mem_assign param id or no mapping info\n"); goto unmap_return; } @@ -160,6 +176,8 @@ SMC_32) ? (sizeof(uint32_t) * 4) : (sizeof(uint64_t) * 4); if (qti_mmap_add_dynamic_region(dyn_map_start, dyn_map_size, (MT_NS | MT_RO_DATA)) != 0) { + ERROR("map failed for params NS Buffer %x %x\n", + (unsigned int)dyn_map_start, (unsigned int)dyn_map_size); goto unmap_return; } /* Retrieve indirect args. */ @@ -174,6 +192,8 @@ } /* Un-Map NS Buffer. */ if (qti_mmap_remove_dynamic_region(dyn_map_start, dyn_map_size) != 0) { + ERROR("unmap failed for params NS Buffer %x %x\n", + (unsigned int)dyn_map_start, (unsigned int)dyn_map_size); goto unmap_return; } @@ -191,6 +211,8 @@ if (qti_mmap_add_dynamic_region(dyn_map_start, dyn_map_size, (MT_NS | MT_RO_DATA)) != 0) { + ERROR("map failed for params NS Buffer2 %x %x\n", + (unsigned int)dyn_map_start, (unsigned int)dyn_map_size); goto unmap_return; } memprot_info_t *mem_info_p = (memprot_info_t *) x2; @@ -205,6 +227,7 @@ source_vm_list_p, src_vm_list_cnt, dest_vm_list_p, dst_vm_list_cnt) != true) { + ERROR("Param validation failed\n"); goto unmap_return; } @@ -219,8 +242,7 @@ for (int i = 0; i < dst_vm_list_cnt; i++) { dest_vm_list[i].dst_vm = dest_vm_list_p[i].dst_vm; - dest_vm_list[i].dst_vm_perm = - dest_vm_list_p[i].dst_vm_perm; + dest_vm_list[i].dst_vm_perm = dest_vm_list_p[i].dst_vm_perm; dest_vm_list[i].ctx = dest_vm_list_p[i].ctx; dest_vm_list[i].ctx_size = dest_vm_list_p[i].ctx_size; } @@ -233,6 +255,8 @@ /* Un-Map NS Buffers. */ if (qti_mmap_remove_dynamic_region(dyn_map_start, dyn_map_size) != 0) { + ERROR("unmap failed for params NS Buffer %x %x\n", + (unsigned int)dyn_map_start, (unsigned int)dyn_map_size); goto unmap_return; } /* Invoke API lib api. */ diff --git a/plat/qti/qtiseclib/inc/sc7180/qtiseclib_defs_plat.h b/plat/qti/qtiseclib/inc/sc7180/qtiseclib_defs_plat.h index c695c19..3ecee20 100644 --- a/plat/qti/qtiseclib/inc/sc7180/qtiseclib_defs_plat.h +++ b/plat/qti/qtiseclib/inc/sc7180/qtiseclib_defs_plat.h @@ -13,12 +13,6 @@ #define BL31_BASE 0x80b00000 #define BL31_SIZE 0x00100000 -/*----------------------------------------------------------------------------*/ -/* AOP CMD DB address space for mapping */ -/*----------------------------------------------------------------------------*/ -#define QTI_AOP_CMD_DB_BASE 0x80820000 -#define QTI_AOP_CMD_DB_SIZE 0x00020000 - /* Chipset specific secure interrupt number/ID defs. */ #define QTISECLIB_INT_ID_SEC_WDOG_BARK (0x204) #define QTISECLIB_INT_ID_NON_SEC_WDOG_BITE (0x21) diff --git a/plat/qti/sc7180/inc/platform_def.h b/plat/qti/sc7180/inc/platform_def.h index 17e1310..b0798a6 100644 --- a/plat/qti/sc7180/inc/platform_def.h +++ b/plat/qti/sc7180/inc/platform_def.h @@ -178,5 +178,17 @@ /*----------------------------------------------------------------------------*/ #define QTI_PS_HOLD_REG 0x0C264000 /*----------------------------------------------------------------------------*/ +/* AOP CMD DB address space for mapping */ +/*----------------------------------------------------------------------------*/ +#define QTI_AOP_CMD_DB_BASE 0x80820000 +#define QTI_AOP_CMD_DB_SIZE 0x00020000 +/*----------------------------------------------------------------------------*/ +/* SOC hw version register */ +/*----------------------------------------------------------------------------*/ +#define QTI_SOC_VERSION U(0x7180) +#define QTI_SOC_VERSION_MASK U(0xFFFF) +#define QTI_SOC_REVISION_REG 0x1FC8000 +#define QTI_SOC_REVISION_MASK U(0xFFFF) +/*----------------------------------------------------------------------------*/ #endif /* PLATFORM_DEF_H */