diff --git a/Makefile b/Makefile index bd52c0b..34e695e 100644 --- a/Makefile +++ b/Makefile @@ -255,7 +255,7 @@ # General warnings WARNINGS := -Wall -Wmissing-include-dirs -Wunused \ -Wdisabled-optimization -Wvla -Wshadow \ - -Wno-unused-parameter + -Wno-unused-parameter -Wredundant-decls # Additional warnings # Level 1 @@ -274,7 +274,6 @@ WARNING3 += -Wconversion WARNING3 += -Wpacked WARNING3 += -Wpointer-arith -WARNING3 += -Wredundant-decls WARNING3 += -Wswitch-default ifeq (${W},1) diff --git a/plat/imx/imx8qm/imx8qm_bl31_setup.c b/plat/imx/imx8qm/imx8qm_bl31_setup.c index c76de64..9232cbc 100644 --- a/plat/imx/imx8qm/imx8qm_bl31_setup.c +++ b/plat/imx/imx8qm/imx8qm_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,12 +27,13 @@ #include #include -IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START); -IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END); -IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_START); -IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_END); +static const unsigned long BL31_COHERENT_RAM_START = BL_COHERENT_RAM_BASE; +static const unsigned long BL31_COHERENT_RAM_END = BL_COHERENT_RAM_END; +static const unsigned long BL31_RO_START = BL_CODE_BASE; +static const unsigned long BL31_RO_END = BL_CODE_END; +static const unsigned long BL31_RW_END = BL_END; + IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START); -IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END); static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; diff --git a/plat/imx/imx8qx/imx8qx_bl31_setup.c b/plat/imx/imx8qx/imx8qx_bl31_setup.c index bfe4052..58c82ce 100644 --- a/plat/imx/imx8qx/imx8qx_bl31_setup.c +++ b/plat/imx/imx8qx/imx8qx_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,12 +27,13 @@ #include #include -IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START); -IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END); -IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_START); -IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_END); +static const unsigned long BL31_COHERENT_RAM_START = BL_COHERENT_RAM_BASE; +static const unsigned long BL31_COHERENT_RAM_END = BL_COHERENT_RAM_END; +static const unsigned long BL31_RO_START = BL_CODE_BASE; +static const unsigned long BL31_RO_END = BL_CODE_END; +static const unsigned long BL31_RW_END = BL_END; + IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START); -IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END); static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; diff --git a/plat/intel/soc/common/include/socfpga_system_manager.h b/plat/intel/soc/common/include/socfpga_system_manager.h index f1637ae..68e30b8 100644 --- a/plat/intel/soc/common/include/socfpga_system_manager.h +++ b/plat/intel/soc/common/include/socfpga_system_manager.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2020, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -106,7 +106,6 @@ #define SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688 #define SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628 -void enable_nonsecure_access(void); void enable_ns_peripheral_access(void); void enable_ns_bridge_access(void); diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index 25fd84c..cbe3377 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -42,11 +42,12 @@ ******************************************************************************/ IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START); -IMPORT_SYM(uint64_t, __RW_END__, BL31_RW_END); -IMPORT_SYM(uint64_t, __RODATA_START__, BL31_RODATA_BASE); -IMPORT_SYM(uint64_t, __RODATA_END__, BL31_RODATA_END); -IMPORT_SYM(uint64_t, __TEXT_START__, TEXT_START); -IMPORT_SYM(uint64_t, __TEXT_END__, TEXT_END); + +static const uint64_t BL31_RW_END = BL_END; +static const uint64_t BL31_RODATA_BASE = BL_RO_DATA_BASE; +static const uint64_t BL31_RODATA_END = BL_RO_DATA_END; +static const uint64_t TEXT_START = BL_CODE_BASE; +static const uint64_t TEXT_END = BL_CODE_END; extern uint64_t tegra_bl31_phys_base; diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h index b6572ff..1fe3aad 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h @@ -53,7 +53,6 @@ int32_t nvg_is_sc7_allowed(void); int32_t nvg_online_core(uint32_t core); int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx); -int32_t nvg_roc_clean_cache_trbits(void); int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time); int32_t nvg_roc_clean_cache_trbits(void); void nvg_enable_strict_checking_mode(void); diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index 193d80e..578892e 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -39,12 +39,19 @@ #include "rcar_version.h" #include "rom_api.h" -IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE) -IMPORT_SYM(unsigned long, __RO_END__, BL2_RO_LIMIT) +#if RCAR_BL2_DCACHE == 1 +/* + * Following symbols are only used during plat_arch_setup() only + * when RCAR_BL2_DCACHE is enabled. + */ +static const uint64_t BL2_RO_BASE = BL_CODE_BASE; +static const uint64_t BL2_RO_LIMIT = BL_CODE_END; #if USE_COHERENT_MEM -IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL2_COHERENT_RAM_BASE) -IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL2_COHERENT_RAM_LIMIT) +static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; +static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; +#endif + #endif extern void plat_rcar_gic_driver_init(void); diff --git a/plat/renesas/rcar/bl31_plat_setup.c b/plat/renesas/rcar/bl31_plat_setup.c index bd83c41..7bc0d8e 100644 --- a/plat/renesas/rcar/bl31_plat_setup.c +++ b/plat/renesas/rcar/bl31_plat_setup.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,12 +22,12 @@ #include "rcar_private.h" #include "rcar_version.h" -IMPORT_SYM(uint64_t, __RO_START__, BL31_RO_BASE) -IMPORT_SYM(uint64_t, __RO_END__, BL31_RO_LIMIT) +static const uint64_t BL31_RO_BASE = BL_CODE_BASE; +static const uint64_t BL31_RO_LIMIT = BL_CODE_END; #if USE_COHERENT_MEM -IMPORT_SYM(uint64_t, __COHERENT_RAM_START__, BL31_COHERENT_RAM_BASE) -IMPORT_SYM(uint64_t, __COHERENT_RAM_END__, BL31_COHERENT_RAM_LIMIT) +static const uint64_t BL31_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; +static const uint64_t BL31_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; #endif extern void plat_rcar_gic_driver_init(void); diff --git a/plat/st/stm32mp1/include/stm32mp1_boot_device.h b/plat/st/stm32mp1/include/stm32mp1_boot_device.h deleted file mode 100644 index a745983..0000000 --- a/plat/st/stm32mp1/include/stm32mp1_boot_device.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2019, STMicroelectronics - All Rights Reserved - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef STM32MP1_BOOT_DEVICE_H -#define STM32MP1_BOOT_DEVICE_H - -#include -#include -#include - -int plat_get_raw_nand_data(struct rawnand_device *device); -int plat_get_spi_nand_data(struct spinand_device *device); -int plat_get_nor_data(struct nor_device *device); - -#endif /* STM32MP1_BOOT_DEVICE_H */ diff --git a/plat/st/stm32mp1/stm32mp1_boot_device.c b/plat/st/stm32mp1/stm32mp1_boot_device.c index 2d8eccf..997335d 100644 --- a/plat/st/stm32mp1/stm32mp1_boot_device.c +++ b/plat/st/stm32mp1/stm32mp1_boot_device.c @@ -7,6 +7,9 @@ #include #include +#include +#include +#include #include #include diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 11b01ab..5dc5206 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #endif