diff --git a/Makefile b/Makefile index 8d910a4..d605ae9 100644 --- a/Makefile +++ b/Makefile @@ -547,15 +547,15 @@ endif ifeq (${ARCH},aarch64) -BL1_CFLAGS += -DIMAGE_AT_EL3 +BL1_CPPFLAGS += -DIMAGE_AT_EL3 ifeq ($(BL2_AT_EL3),1) -BL2_CFLAGS += -DIMAGE_AT_EL3 +BL2_CPPFLAGS += -DIMAGE_AT_EL3 else -BL2_CFLAGS += -DIMAGE_AT_EL1 +BL2_CPPFLAGS += -DIMAGE_AT_EL1 endif -BL2U_CFLAGS += -DIMAGE_AT_EL1 -BL31_CFLAGS += -DIMAGE_AT_EL3 -BL32_CFLAGS += -DIMAGE_AT_EL1 +BL2U_CPPFLAGS += -DIMAGE_AT_EL1 +BL31_CPPFLAGS += -DIMAGE_AT_EL3 +BL32_CPPFLAGS += -DIMAGE_AT_EL1 endif # Include the CPU specific operations makefile, which provides default diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S index c83824d..92891ce 100644 --- a/include/lib/cpus/aarch64/cpu_macros.S +++ b/include/lib/cpus/aarch64/cpu_macros.S @@ -25,10 +25,6 @@ /* Word size for 64-bit CPUs */ #define CPU_WORD_SIZE 8 -#if defined(IMAGE_BL1) || defined(IMAGE_BL31) ||(defined(IMAGE_BL2) && BL2_AT_EL3) -#define IMAGE_AT_EL3 -#endif - /* * Whether errata status needs reporting. Errata status is printed in debug * builds for both BL1 and BL31 images. diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 15cd691..7843690 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -297,30 +297,30 @@ # Enable the dynamic translation tables library. ifeq (${ARCH},aarch32) ifeq (${RESET_TO_SP_MIN},1) - BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 + BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC endif else # AArch64 ifeq (${RESET_TO_BL31},1) - BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 + BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC endif ifeq (${SPD},trusty) - BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 + BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC endif endif ifeq (${ALLOW_RO_XLAT_TABLES}, 1) ifeq (${ARCH},aarch32) - BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES=1 + BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES else # AArch64 - BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES=1 + BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES ifeq (${SPD},tspd) - BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES=1 + BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES endif endif endif ifeq (${USE_DEBUGFS},1) - BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 + BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC endif # Add support for platform supplied linker script for BL31 build diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk index dfdefa1..a871e81 100644 --- a/plat/arm/board/juno/platform.mk +++ b/plat/arm/board/juno/platform.mk @@ -147,19 +147,19 @@ # Enable the dynamic translation tables library. ifeq (${ARCH},aarch32) ifeq (${RESET_TO_SP_MIN},1) - BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 + BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC endif else ifeq (${RESET_TO_BL31},1) - BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 + BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC endif endif ifeq (${ALLOW_RO_XLAT_TABLES}, 1) ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) - BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES=1 + BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES else - BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES=1 + BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES endif endif diff --git a/plat/arm/board/rdn1edge/platform.mk b/plat/arm/board/rdn1edge/platform.mk index 1daf85f..e436542 100644 --- a/plat/arm/board/rdn1edge/platform.mk +++ b/plat/arm/board/rdn1edge/platform.mk @@ -38,7 +38,7 @@ endif # Enable dynamic addition of MMAP regions in BL31 -BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 +BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC # Add the FDT_SOURCES and options for Dynamic Config FDT_SOURCES += ${RDN1EDGE_BASE}/fdts/${PLAT}_fw_config.dts diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk index 3f8a1f8..8819545 100644 --- a/plat/socionext/uniphier/platform.mk +++ b/plat/socionext/uniphier/platform.mk @@ -17,8 +17,8 @@ ALLOW_RO_XLAT_TABLES := 1 ifeq ($(ALLOW_RO_XLAT_TABLES),1) -BL31_CFLAGS += -DPLAT_RO_XLAT_TABLES=1 -BL32_CFLAGS += -DPLAT_RO_XLAT_TABLES=1 +BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES +BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES endif # Cortex-A53 revision r0p4-51rel0