diff --git a/include/common/runtime_svc.h b/include/common/runtime_svc.h index 6fe0a94..e32c287 100644 --- a/include/common/runtime_svc.h +++ b/include/common/runtime_svc.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __RUNTIME_SVC_H__ -#define __RUNTIME_SVC_H__ +#ifndef RUNTIME_SVC_H +#define RUNTIME_SVC_H #include /* to include exception types */ #include @@ -88,12 +88,12 @@ #define DECLARE_RT_SVC(_name, _start, _end, _type, _setup, _smch) \ static const rt_svc_desc_t __svc_desc_ ## _name \ __section("rt_svc_descs") __used = { \ - .start_oen = _start, \ - .end_oen = _end, \ - .call_type = _type, \ + .start_oen = (_start), \ + .end_oen = (_end), \ + .call_type = (_type), \ .name = #_name, \ - .init = _setup, \ - .handle = _smch \ + .init = (_setup), \ + .handle = (_smch) \ } #elif SMCCC_MAJOR_VERSION == 2 @@ -101,12 +101,12 @@ #define DECLARE_RT_SVC(_name, _start, _end, _type, _setup, _smch) \ static const rt_svc_desc_t __svc_desc_ ## _name \ __section("rt_svc_descs") __used = { \ - .start_oen = _start, \ - .end_oen = _end, \ + .start_oen = (_start), \ + .end_oen = (_end), \ .is_vendor = 0, \ .name = #_name, \ - .init = _setup, \ - .handle = _smch, \ + .init = (_setup), \ + .handle = (_smch), \ }; \ CASSERT((_type) == SMC_TYPE_FAST, rt_svc_type_check_ ## _name) @@ -198,4 +198,4 @@ extern uint8_t rt_svc_descs_indices[MAX_RT_SVCS]; #endif /*__ASSEMBLY__*/ -#endif /* __RUNTIME_SVC_H__ */ +#endif /* RUNTIME_SVC_H */ diff --git a/include/plat/arm/board/common/v2m_def.h b/include/plat/arm/board/common/v2m_def.h index ce436d2..02c3494 100644 --- a/include/plat/arm/board/common/v2m_def.h +++ b/include/plat/arm/board/common/v2m_def.h @@ -1,36 +1,36 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __V2M_DEF_H__ -#define __V2M_DEF_H__ +#ifndef V2M_DEF_H +#define V2M_DEF_H #include /* V2M motherboard system registers & offsets */ -#define V2M_SYSREGS_BASE 0x1c010000 -#define V2M_SYS_ID 0x0 -#define V2M_SYS_SWITCH 0x4 -#define V2M_SYS_LED 0x8 -#define V2M_SYS_NVFLAGS 0x38 -#define V2M_SYS_NVFLAGSSET 0x38 -#define V2M_SYS_NVFLAGSCLR 0x3c -#define V2M_SYS_CFGDATA 0xa0 -#define V2M_SYS_CFGCTRL 0xa4 -#define V2M_SYS_CFGSTATUS 0xa8 +#define V2M_SYSREGS_BASE UL(0x1c010000) +#define V2M_SYS_ID UL(0x0) +#define V2M_SYS_SWITCH UL(0x4) +#define V2M_SYS_LED UL(0x8) +#define V2M_SYS_NVFLAGS UL(0x38) +#define V2M_SYS_NVFLAGSSET UL(0x38) +#define V2M_SYS_NVFLAGSCLR UL(0x3c) +#define V2M_SYS_CFGDATA UL(0xa0) +#define V2M_SYS_CFGCTRL UL(0xa4) +#define V2M_SYS_CFGSTATUS UL(0xa8) -#define V2M_CFGCTRL_START (1 << 31) -#define V2M_CFGCTRL_RW (1 << 30) +#define V2M_CFGCTRL_START BIT_32(31) +#define V2M_CFGCTRL_RW BIT_32(30) #define V2M_CFGCTRL_FUNC_SHIFT 20 -#define V2M_CFGCTRL_FUNC(fn) (fn << V2M_CFGCTRL_FUNC_SHIFT) -#define V2M_FUNC_CLK_GEN 0x01 -#define V2M_FUNC_TEMP 0x04 -#define V2M_FUNC_DB_RESET 0x05 -#define V2M_FUNC_SCC_CFG 0x06 -#define V2M_FUNC_SHUTDOWN 0x08 -#define V2M_FUNC_REBOOT 0x09 +#define V2M_CFGCTRL_FUNC(fn) ((fn) << V2M_CFGCTRL_FUNC_SHIFT) +#define V2M_FUNC_CLK_GEN U(0x01) +#define V2M_FUNC_TEMP U(0x04) +#define V2M_FUNC_DB_RESET U(0x05) +#define V2M_FUNC_SCC_CFG U(0x06) +#define V2M_FUNC_SHUTDOWN U(0x08) +#define V2M_FUNC_REBOOT U(0x09) /* NVFLAGS in the V2M motherboard which is preserved after a watchdog reset */ #define V2M_SYS_NVFLAGS_ADDR (V2M_SYSREGS_BASE + V2M_SYS_NVFLAGS) @@ -131,4 +131,4 @@ MT_DEVICE | MT_RW | MT_SECURE | MT_USER) -#endif /* __V2M_DEF_H__ */ +#endif /* V2M_DEF_H */ diff --git a/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.h b/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.h index 9ad32d7..324f3e2 100644 --- a/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.h +++ b/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.h @@ -4,36 +4,36 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __FVP_PWRC_H__ -#define __FVP_PWRC_H__ +#ifndef FVP_PWRC_H +#define FVP_PWRC_H /* FVP Power controller register offset etc */ -#define PPOFFR_OFF 0x0 -#define PPONR_OFF 0x4 -#define PCOFFR_OFF 0x8 -#define PWKUPR_OFF 0xc -#define PSYSR_OFF 0x10 +#define PPOFFR_OFF U(0x0) +#define PPONR_OFF U(0x4) +#define PCOFFR_OFF U(0x8) +#define PWKUPR_OFF U(0xc) +#define PSYSR_OFF U(0x10) -#define PWKUPR_WEN (1ULL << 31) +#define PWKUPR_WEN BIT_32(31) -#define PSYSR_AFF_L2 (1 << 31) -#define PSYSR_AFF_L1 (1 << 30) -#define PSYSR_AFF_L0 (1 << 29) -#define PSYSR_WEN (1 << 28) -#define PSYSR_PC (1 << 27) -#define PSYSR_PP (1 << 26) +#define PSYSR_AFF_L2 BIT_32(31) +#define PSYSR_AFF_L1 BIT_32(30) +#define PSYSR_AFF_L0 BIT_32(29) +#define PSYSR_WEN BIT_32(28) +#define PSYSR_PC BIT_32(27) +#define PSYSR_PP BIT_32(26) #define PSYSR_WK_SHIFT 24 #define PSYSR_WK_WIDTH 0x2 -#define PSYSR_WK_MASK ((1 << PSYSR_WK_WIDTH) - 1) -#define PSYSR_WK(x) (x >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK +#define PSYSR_WK_MASK ((1U << PSYSR_WK_WIDTH) - 1U) +#define PSYSR_WK(x) ((x) >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK -#define WKUP_COLD 0x0 -#define WKUP_RESET 0x1 -#define WKUP_PPONR 0x2 -#define WKUP_GICREQ 0x3 +#define WKUP_COLD U(0x0) +#define WKUP_RESET U(0x1) +#define WKUP_PPONR U(0x2) +#define WKUP_GICREQ U(0x3) -#define PSYSR_INVALID 0xffffffff +#define PSYSR_INVALID U(0xffffffff) #ifndef __ASSEMBLY__ @@ -50,4 +50,4 @@ #endif /*__ASSEMBLY__*/ -#endif /* __FVP_PWRC_H__ */ +#endif /* FVP_PWRC_H */ diff --git a/plat/arm/board/fvp/fvp_def.h b/plat/arm/board/fvp/fvp_def.h index 4e20c31..eb6f77f 100644 --- a/plat/arm/board/fvp/fvp_def.h +++ b/plat/arm/board/fvp/fvp_def.h @@ -97,7 +97,7 @@ #define ARCH_MODEL 0x1 /* FVP Power controller base address*/ -#define PWRC_BASE 0x1c100000 +#define PWRC_BASE UL(0x1c100000) /* FVP SP804 timer frequency is 35 MHz*/ #define SP804_TIMER_CLKMULT 1 diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c index 065ecc1..7b85043 100644 --- a/plat/arm/board/fvp/fvp_pm.c +++ b/plat/arm/board/fvp/fvp_pm.c @@ -153,7 +153,7 @@ */ do { psysr = fvp_pwrc_read_psysr(mpidr); - } while (psysr & PSYSR_AFF_L0); + } while ((psysr & PSYSR_AFF_L0) != 0U); fvp_pwrc_write_pponr(mpidr); return rc; @@ -312,7 +312,7 @@ * The format of 'power_level' is implementation-defined, but 0 must * mean a CPU. We also allow 1 to denote the cluster */ - if (power_level != ARM_PWR_LVL0 && power_level != ARM_PWR_LVL1) + if ((power_level != ARM_PWR_LVL0) && (power_level != ARM_PWR_LVL1)) return PSCI_E_INVALID_PARAMS; /* @@ -325,10 +325,10 @@ return PSCI_E_INVALID_PARAMS; if (power_level == ARM_PWR_LVL0) { - ret = (psysr & PSYSR_AFF_L0) ? HW_ON : HW_OFF; + ret = ((psysr & PSYSR_AFF_L0) != 0U) ? HW_ON : HW_OFF; } else { /* power_level == ARM_PWR_LVL1 */ - ret = (psysr & PSYSR_AFF_L1) ? HW_ON : HW_OFF; + ret = ((psysr & PSYSR_AFF_L1) != 0U) ? HW_ON : HW_OFF; } return ret; diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c index 85efc7d..6394bfb 100644 --- a/plat/arm/common/arm_pm.c +++ b/plat/arm/common/arm_pm.c @@ -29,7 +29,7 @@ unsigned int pwr_lvl = psci_get_pstate_pwrlvl(power_state); unsigned int i; - assert(req_state > 0U); + assert(req_state != NULL); if (pwr_lvl > PLAT_MAX_PWR_LVL) return PSCI_E_INVALID_PARAMS; @@ -72,7 +72,7 @@ unsigned int state_id; int i; - assert(req_state); + assert(req_state != NULL); /* * Currently we are using a linear search for finding the matching @@ -128,7 +128,7 @@ int arm_validate_psci_entrypoint(uintptr_t entrypoint) { - return arm_validate_ns_entrypoint(entrypoint) == 0 ? PSCI_E_SUCCESS : + return (arm_validate_ns_entrypoint(entrypoint) == 0) ? PSCI_E_SUCCESS : PSCI_E_INVALID_ADDRESS; }