diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c
index d160279..a27680c 100644
--- a/plat/intel/soc/agilex/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex/bl2_plat_setup.c
@@ -18,13 +18,13 @@
 #include "agilex_clock_manager.h"
 #include "agilex_memory_controller.h"
 #include "agilex_pinmux.h"
-#include "agilex_reset_manager.h"
 #include "agilex_system_manager.h"
 #include "ccu/ncore_ccu.h"
 #include "qspi/cadence_qspi.h"
 #include "socfpga_handoff.h"
 #include "socfpga_mailbox.h"
 #include "socfpga_private.h"
+#include "socfpga_reset_manager.h"
 #include "wdt/watchdog.h"
 
 
diff --git a/plat/intel/soc/agilex/include/agilex_reset_manager.h b/plat/intel/soc/agilex/include/agilex_reset_manager.h
deleted file mode 100644
index 9c9c884..0000000
--- a/plat/intel/soc/agilex/include/agilex_reset_manager.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef AGX_RESETMANAGER_H
-#define AGX_RESETMANAGER_H
-
-#define AGX_RSTMGR_HDSKEN				0xffd11010
-#define AGX_RSTMGR_PER0MODRST				0xffd11024
-#define AGX_RSTMGR_PER1MODRST				0xffd11028
-#define AGX_RSTMGR_BRGMODRST				0xffd1102c
-
-#define AGX_RSTMGR_PER0MODRST_EMAC0			0x00000001
-#define AGX_RSTMGR_PER0MODRST_EMAC1			0x00000002
-#define AGX_RSTMGR_PER0MODRST_EMAC2			0x00000004
-#define AGX_RSTMGR_PER0MODRST_USB0			0x00000008
-#define AGX_RSTMGR_PER0MODRST_USB1			0x00000010
-#define AGX_RSTMGR_PER0MODRST_NAND			0x00000020
-#define AGX_RSTMGR_PER0MODRST_SDMMC			0x00000080
-#define AGX_RSTMGR_PER0MODRST_EMAC0OCP			0x00000100
-#define AGX_RSTMGR_PER0MODRST_EMAC1OCP			0x00000200
-#define AGX_RSTMGR_PER0MODRST_EMAC2OCP			0x00000400
-#define AGX_RSTMGR_PER0MODRST_USB0OCP			0x00000800
-#define AGX_RSTMGR_PER0MODRST_USB1OCP			0x00001000
-#define AGX_RSTMGR_PER0MODRST_NANDOCP			0x00002000
-#define AGX_RSTMGR_PER0MODRST_SDMMCOCP			0x00008000
-#define AGX_RSTMGR_PER0MODRST_DMA			0x00010000
-#define AGX_RSTMGR_PER0MODRST_SPIM0			0x00020000
-#define AGX_RSTMGR_PER0MODRST_SPIM1			0x00040000
-#define AGX_RSTMGR_PER0MODRST_SPIS0			0x00080000
-#define AGX_RSTMGR_PER0MODRST_SPIS1			0x00100000
-#define AGX_RSTMGR_PER0MODRST_DMAOCP			0x00200000
-#define AGX_RSTMGR_PER0MODRST_EMACPTP			0x00400000
-#define AGX_RSTMGR_PER0MODRST_DMAIF0			0x01000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF1			0x02000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF2			0x04000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF3			0x08000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF4			0x10000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF5			0x20000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF6			0x40000000
-#define AGX_RSTMGR_PER0MODRST_DMAIF7			0x80000000
-
-#define AGX_RSTMGR_PER1MODRST_WATCHDOG0			0x1
-#define AGX_RSTMGR_PER1MODRST_WATCHDOG1			0x2
-#define AGX_RSTMGR_PER1MODRST_WATCHDOG2			0x4
-#define AGX_RSTMGR_PER1MODRST_WATCHDOG3			0x8
-#define AGX_RSTMGR_PER1MODRST_L4SYSTIMER0		0x00000010
-#define AGX_RSTMGR_PER1MODRST_L4SYSTIMER1		0x00000020
-#define AGX_RSTMGR_PER1MODRST_SPTIMER0			0x00000040
-#define AGX_RSTMGR_PER1MODRST_SPTIMER1			0x00000080
-#define AGX_RSTMGR_PER1MODRST_I2C0			0x00000100
-#define AGX_RSTMGR_PER1MODRST_I2C1			0x00000200
-#define AGX_RSTMGR_PER1MODRST_I2C2			0x00000400
-#define AGX_RSTMGR_PER1MODRST_I2C3			0x00000800
-#define AGX_RSTMGR_PER1MODRST_I2C4			0x00001000
-#define AGX_RSTMGR_PER1MODRST_UART0			0x00010000
-#define AGX_RSTMGR_PER1MODRST_UART1			0x00020000
-#define AGX_RSTMGR_PER1MODRST_GPIO0			0x01000000
-#define AGX_RSTMGR_PER1MODRST_GPIO1			0x02000000
-
-#define AGX_RSTMGR_HDSKEN_FPGAHSEN			0x00000004
-#define AGX_RSTMGR_HDSKEN_ETRSTALLEN			0x00000008
-#define AGX_RSTMGR_HDSKEN_L2FLUSHEN			0x00000100
-#define AGX_RSTMGR_HDSKEN_L3NOC_DBG			0x00010000
-#define AGX_RSTMGR_HDSKEN_DEBUG_L3NOC			0x00020000
-#define AGX_RSTMGR_HDSKEN_SDRSELFREFEN			0x00000001
-
-#define AGX_RSTMGR_BRGMODRST_SOC2FPGA			0x1
-#define AGX_RSTMGR_BRGMODRST_LWHPS2FPGA			0x2
-#define AGX_RSTMGR_BRGMODRST_FPGA2SOC			0x4
-#define AGX_RSTMGR_BRGMODRST_MPFE			0x40
-
-void deassert_peripheral_reset(void);
-void config_hps_hs_before_warm_reset(void);
-int socfpga_bridges_enable(void);
-int socfpga_bridges_disable(void);
-
-#endif
-
diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h
index a346cb5..3867503 100644
--- a/plat/intel/soc/agilex/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h
@@ -15,9 +15,7 @@
 
 /* Register Mapping */
 #define SOCFPGA_MMC_REG_BASE			0xff808000
-
-#define SOCFPGA_RSTMGR_OFST			0xffd11000
-#define SOCFPGA_RSTMGR_MPUMODRST_OFST		0xffd11020
+#define SOCFPGA_RSTMGR_REG_BASE			0xffd11000
 
 #endif /* PLAT_SOCFPGA_DEF_H */
 
diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk
index ef02a8d..c4904be 100644
--- a/plat/intel/soc/agilex/platform.mk
+++ b/plat/intel/soc/agilex/platform.mk
@@ -38,7 +38,6 @@
 		plat/intel/soc/agilex/soc/agilex_clock_manager.c	\
 		plat/intel/soc/agilex/soc/agilex_memory_controller.c	\
 		plat/intel/soc/agilex/soc/agilex_pinmux.c		\
-		plat/intel/soc/agilex/soc/agilex_reset_manager.c	\
 		plat/intel/soc/agilex/soc/agilex_system_manager.c	\
                 plat/intel/soc/common/bl2_plat_mem_params_desc.c	\
 		plat/intel/soc/common/socfpga_delay_timer.c		\
@@ -46,6 +45,7 @@
 		plat/intel/soc/common/socfpga_storage.c			\
 		plat/intel/soc/common/soc/socfpga_handoff.c		\
 		plat/intel/soc/common/soc/socfpga_mailbox.c		\
+		plat/intel/soc/common/soc/socfpga_reset_manager.c	\
 		plat/intel/soc/common/drivers/qspi/cadence_qspi.c	\
 		plat/intel/soc/common/drivers/wdt/watchdog.c		\
 		plat/intel/soc/common/drivers/ccu/ncore_ccu.c
diff --git a/plat/intel/soc/agilex/soc/agilex_reset_manager.c b/plat/intel/soc/agilex/soc/agilex_reset_manager.c
deleted file mode 100644
index 1224a90..0000000
--- a/plat/intel/soc/agilex/soc/agilex_reset_manager.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <errno.h>
-#include <lib/mmio.h>
-
-#include "agilex_reset_manager.h"
-#include "agilex_system_manager.h"
-#include "socfpga_mailbox.h"
-
-void deassert_peripheral_reset(void)
-{
-	mmio_clrbits_32(AGX_RSTMGR_PER1MODRST,
-			AGX_RSTMGR_PER1MODRST_WATCHDOG0 |
-			AGX_RSTMGR_PER1MODRST_WATCHDOG1 |
-			AGX_RSTMGR_PER1MODRST_WATCHDOG2 |
-			AGX_RSTMGR_PER1MODRST_WATCHDOG3 |
-			AGX_RSTMGR_PER1MODRST_L4SYSTIMER0 |
-			AGX_RSTMGR_PER1MODRST_L4SYSTIMER1 |
-			AGX_RSTMGR_PER1MODRST_SPTIMER0 |
-			AGX_RSTMGR_PER1MODRST_SPTIMER1 |
-			AGX_RSTMGR_PER1MODRST_I2C0 |
-			AGX_RSTMGR_PER1MODRST_I2C1 |
-			AGX_RSTMGR_PER1MODRST_I2C2 |
-			AGX_RSTMGR_PER1MODRST_I2C3 |
-			AGX_RSTMGR_PER1MODRST_I2C4 |
-			AGX_RSTMGR_PER1MODRST_UART0 |
-			AGX_RSTMGR_PER1MODRST_UART1 |
-			AGX_RSTMGR_PER1MODRST_GPIO0 |
-			AGX_RSTMGR_PER1MODRST_GPIO1);
-
-	mmio_clrbits_32(AGX_RSTMGR_PER0MODRST,
-			AGX_RSTMGR_PER0MODRST_EMAC0OCP |
-			AGX_RSTMGR_PER0MODRST_EMAC1OCP |
-			AGX_RSTMGR_PER0MODRST_EMAC2OCP |
-			AGX_RSTMGR_PER0MODRST_USB0OCP |
-			AGX_RSTMGR_PER0MODRST_USB1OCP |
-			AGX_RSTMGR_PER0MODRST_NANDOCP |
-			AGX_RSTMGR_PER0MODRST_SDMMCOCP |
-			AGX_RSTMGR_PER0MODRST_DMAOCP);
-
-	mmio_clrbits_32(AGX_RSTMGR_PER0MODRST,
-			AGX_RSTMGR_PER0MODRST_EMAC0 |
-			AGX_RSTMGR_PER0MODRST_EMAC1 |
-			AGX_RSTMGR_PER0MODRST_EMAC2 |
-			AGX_RSTMGR_PER0MODRST_USB0 |
-			AGX_RSTMGR_PER0MODRST_USB1 |
-			AGX_RSTMGR_PER0MODRST_NAND |
-			AGX_RSTMGR_PER0MODRST_SDMMC |
-			AGX_RSTMGR_PER0MODRST_DMA |
-			AGX_RSTMGR_PER0MODRST_SPIM0 |
-			AGX_RSTMGR_PER0MODRST_SPIM1 |
-			AGX_RSTMGR_PER0MODRST_SPIS0 |
-			AGX_RSTMGR_PER0MODRST_SPIS1 |
-			AGX_RSTMGR_PER0MODRST_EMACPTP |
-			AGX_RSTMGR_PER0MODRST_DMAIF0 |
-			AGX_RSTMGR_PER0MODRST_DMAIF1 |
-			AGX_RSTMGR_PER0MODRST_DMAIF2 |
-			AGX_RSTMGR_PER0MODRST_DMAIF3 |
-			AGX_RSTMGR_PER0MODRST_DMAIF4 |
-			AGX_RSTMGR_PER0MODRST_DMAIF5 |
-			AGX_RSTMGR_PER0MODRST_DMAIF6 |
-			AGX_RSTMGR_PER0MODRST_DMAIF7);
-
-	mmio_clrbits_32(AGX_RSTMGR_BRGMODRST,
-			AGX_RSTMGR_BRGMODRST_MPFE);
-}
-
-void config_hps_hs_before_warm_reset(void)
-{
-	uint32_t or_mask = 0;
-
-	or_mask |= AGX_RSTMGR_HDSKEN_SDRSELFREFEN;
-	or_mask |= AGX_RSTMGR_HDSKEN_FPGAHSEN;
-	or_mask |= AGX_RSTMGR_HDSKEN_ETRSTALLEN;
-	or_mask |= AGX_RSTMGR_HDSKEN_L2FLUSHEN;
-	or_mask |= AGX_RSTMGR_HDSKEN_L3NOC_DBG;
-	or_mask |= AGX_RSTMGR_HDSKEN_DEBUG_L3NOC;
-
-	mmio_setbits_32(AGX_RSTMGR_HDSKEN, or_mask);
-}
-
-static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match)
-{
-	int time_out = 1000;
-
-	while (time_out--) {
-		if ((mmio_read_32(addr) & mask) == match) {
-			return 0;
-		}
-	}
-	return -ETIMEDOUT;
-}
-
-int socfpga_bridges_enable(void)
-{
-	uint32_t status, poll_addr;
-
-	status = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS);
-
-	if (!status) {
-		/* Clear idle request */
-		mmio_setbits_32(AGX_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_CLR), ~0);
-
-		/* De-assert all bridges */
-		mmio_clrbits_32(AGX_RSTMGR_BRGMODRST, ~0);
-
-		/* Wait until idle ack becomes 0 */
-		poll_addr = AGX_SYSMGR_CORE(SYSMGR_NOC_IDLEACK);
-
-		return poll_idle_status(poll_addr, IDLE_DATA_MASK, 0);
-	}
-	return status;
-}
-
-int socfpga_bridges_disable(void)
-{
-	uint32_t poll_addr;
-
-	/* Set idle request */
-	mmio_write_32(AGX_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_SET), ~0);
-
-	/* Enable NOC timeout */
-	mmio_setbits_32(SYSMGR_NOC_TIMEOUT, 1);
-
-	/* Wait until each idle ack bit toggle to 1 */
-	poll_addr = AGX_SYSMGR_CORE(SYSMGR_NOC_IDLEACK);
-	if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK))
-		return -ETIMEDOUT;
-
-	/* Wait until each idle status bit toggle to 1 */
-	poll_addr = AGX_SYSMGR_CORE(SYSMGR_NOC_IDLESTATUS);
-	if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK))
-		return -ETIMEDOUT;
-
-	/* Assert all bridges */
-	mmio_setbits_32(AGX_RSTMGR_BRGMODRST,
-		~(AGX_RSTMGR_BRGMODRST_MPFE | AGX_RSTMGR_BRGMODRST_FPGA2SOC));
-
-	/* Disable NOC timeout */
-	mmio_clrbits_32(AGX_SYSMGR_CORE(SYSMGR_NOC_TIMEOUT), 1);
-
-	return 0;
-}
diff --git a/plat/intel/soc/common/include/socfpga_reset_manager.h b/plat/intel/soc/common/include/socfpga_reset_manager.h
index 3fbf242..637f8df 100644
--- a/plat/intel/soc/common/include/socfpga_reset_manager.h
+++ b/plat/intel/soc/common/include/socfpga_reset_manager.h
@@ -7,12 +7,102 @@
 #ifndef SOCFPGA_RESETMANAGER_H
 #define SOCFPGA_RESETMANAGER_H
 
-#define SOCFPGA_RSTMGR_STAT				0xffd11000
-#define SOCFPGA_RSTMGR_HDSKEN				0xffd11010
-#define SOCFPGA_RSTMGR_COLDMODRST			0xffd11034
-#define SOCFPGA_RSTMGR_HDSKTIMEOUT			0xffd11064
+#include "socfpga_plat_def.h"
 
-#define SOCFPGA_RSTMGR_HDSKEN_SET			0x0000010D
-#define SOCFPGA_RSTMGR_SDMWARMRST			0x00000002
+
+/* Register Mapping */
+
+#define SOCFPGA_RSTMGR_STAT			0x000
+#define SOCFPGA_RSTMGR_HDSKEN			0x010
+#define SOCFPGA_RSTMGR_MPUMODRST		0x020
+#define SOCFPGA_RSTMGR_PER0MODRST		0x024
+#define SOCFPGA_RSTMGR_PER1MODRST		0x028
+#define SOCFPGA_RSTMGR_BRGMODRST		0x02c
+#define SOCFPGA_RSTMGR_COLDMODRST		0x034
+#define SOCFPGA_RSTMGR_HDSKTIMEOUT		0x064
+
+/* Field Mapping */
+
+#define RSTMGR_PER0MODRST_EMAC0			0x00000001
+#define RSTMGR_PER0MODRST_EMAC1			0x00000002
+#define RSTMGR_PER0MODRST_EMAC2			0x00000004
+#define RSTMGR_PER0MODRST_USB0			0x00000008
+#define RSTMGR_PER0MODRST_USB1			0x00000010
+#define RSTMGR_PER0MODRST_NAND			0x00000020
+#define RSTMGR_PER0MODRST_SDMMC			0x00000080
+#define RSTMGR_PER0MODRST_EMAC0OCP		0x00000100
+#define RSTMGR_PER0MODRST_EMAC1OCP		0x00000200
+#define RSTMGR_PER0MODRST_EMAC2OCP		0x00000400
+#define RSTMGR_PER0MODRST_USB0OCP		0x00000800
+#define RSTMGR_PER0MODRST_USB1OCP		0x00001000
+#define RSTMGR_PER0MODRST_NANDOCP		0x00002000
+#define RSTMGR_PER0MODRST_SDMMCOCP		0x00008000
+#define RSTMGR_PER0MODRST_DMA			0x00010000
+#define RSTMGR_PER0MODRST_SPIM0			0x00020000
+#define RSTMGR_PER0MODRST_SPIM1			0x00040000
+#define RSTMGR_PER0MODRST_SPIS0			0x00080000
+#define RSTMGR_PER0MODRST_SPIS1			0x00100000
+#define RSTMGR_PER0MODRST_DMAOCP		0x00200000
+#define RSTMGR_PER0MODRST_EMACPTP		0x00400000
+#define RSTMGR_PER0MODRST_DMAIF0		0x01000000
+#define RSTMGR_PER0MODRST_DMAIF1		0x02000000
+#define RSTMGR_PER0MODRST_DMAIF2		0x04000000
+#define RSTMGR_PER0MODRST_DMAIF3		0x08000000
+#define RSTMGR_PER0MODRST_DMAIF4		0x10000000
+#define RSTMGR_PER0MODRST_DMAIF5		0x20000000
+#define RSTMGR_PER0MODRST_DMAIF6		0x40000000
+#define RSTMGR_PER0MODRST_DMAIF7		0x80000000
+
+#define RSTMGR_PER1MODRST_WATCHDOG0		0x00000001
+#define RSTMGR_PER1MODRST_WATCHDOG1		0x00000002
+#define RSTMGR_PER1MODRST_WATCHDOG2		0x00000004
+#define RSTMGR_PER1MODRST_WATCHDOG3		0x00000008
+#define RSTMGR_PER1MODRST_L4SYSTIMER0		0x00000010
+#define RSTMGR_PER1MODRST_L4SYSTIMER1		0x00000020
+#define RSTMGR_PER1MODRST_SPTIMER0		0x00000040
+#define RSTMGR_PER1MODRST_SPTIMER1		0x00000080
+#define RSTMGR_PER1MODRST_I2C0			0x00000100
+#define RSTMGR_PER1MODRST_I2C1			0x00000200
+#define RSTMGR_PER1MODRST_I2C2			0x00000400
+#define RSTMGR_PER1MODRST_I2C3			0x00000800
+#define RSTMGR_PER1MODRST_I2C4			0x00001000
+#define RSTMGR_PER1MODRST_UART0			0x00010000
+#define RSTMGR_PER1MODRST_UART1			0x00020000
+#define RSTMGR_PER1MODRST_GPIO0			0x01000000
+#define RSTMGR_PER1MODRST_GPIO1			0x02000000
+
+#define RSTMGR_HDSKEN_FPGAHSEN			0x00000004
+#define RSTMGR_HDSKEN_ETRSTALLEN		0x00000008
+#define RSTMGR_HDSKEN_L2FLUSHEN			0x00000100
+#define RSTMGR_HDSKEN_L3NOC_DBG			0x00010000
+#define RSTMGR_HDSKEN_DEBUG_L3NOC		0x00020000
+#define RSTMGR_HDSKEN_SDRSELFREFEN		0x00000001
+
+#define RSTMGR_BRGMODRST_SOC2FPGA		0x1
+#define RSTMGR_BRGMODRST_LWHPS2FPGA		0x2
+#define RSTMGR_BRGMODRST_FPGA2SOC		0x4
+#define RSTMGR_BRGMODRST_F2SSDRAM1		0x10
+#define RSTMGR_BRGMODRST_F2SSDRAM2		0x20
+#define RSTMGR_BRGMODRST_MPFE			0x40
+#define RSTMGR_BRGMODRST_DDRSCH			0x40
+
+/* Definitions */
+
+#define RSTMGR_L2_MODRST			0x0100
+#define RSTMGR_HDSKEN_SET			0x010D
+
+/* Macros */
+
+#define SOCFPGA_RSTMGR(_reg)		(SOCFPGA_RSTMGR_REG_BASE \
+						+ (SOCFPGA_RSTMGR_##_reg))
+#define RSTMGR_FIELD(_reg, _field)	(RSTMGR_##_reg##MODRST_##_field)
+
+/* Function Declarations */
+
+void deassert_peripheral_reset(void);
+void config_hps_hs_before_warm_reset(void);
+
+int socfpga_bridges_enable(void);
+int socfpga_bridges_disable(void);
 
 #endif /* SOCFPGA_RESETMANAGER_H */
diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c
new file mode 100644
index 0000000..58ab282
--- /dev/null
+++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <errno.h>
+#include <lib/mmio.h>
+
+#include "s10_system_manager.h"
+#include "socfpga_mailbox.h"
+#include "socfpga_reset_manager.h"
+
+
+void deassert_peripheral_reset(void)
+{
+	mmio_clrbits_32(SOCFPGA_RSTMGR(PER1MODRST),
+			RSTMGR_FIELD(PER1, WATCHDOG0) |
+			RSTMGR_FIELD(PER1, WATCHDOG1) |
+			RSTMGR_FIELD(PER1, WATCHDOG2) |
+			RSTMGR_FIELD(PER1, WATCHDOG3) |
+			RSTMGR_FIELD(PER1, L4SYSTIMER0) |
+			RSTMGR_FIELD(PER1, L4SYSTIMER1) |
+			RSTMGR_FIELD(PER1, SPTIMER0) |
+			RSTMGR_FIELD(PER1, SPTIMER1) |
+			RSTMGR_FIELD(PER1, I2C0) |
+			RSTMGR_FIELD(PER1, I2C1) |
+			RSTMGR_FIELD(PER1, I2C2) |
+			RSTMGR_FIELD(PER1, I2C3) |
+			RSTMGR_FIELD(PER1, I2C4) |
+			RSTMGR_FIELD(PER1, UART0) |
+			RSTMGR_FIELD(PER1, UART1) |
+			RSTMGR_FIELD(PER1, GPIO0) |
+			RSTMGR_FIELD(PER1, GPIO1));
+
+	mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST),
+			RSTMGR_FIELD(PER0, EMAC0OCP) |
+			RSTMGR_FIELD(PER0, EMAC1OCP) |
+			RSTMGR_FIELD(PER0, EMAC2OCP) |
+			RSTMGR_FIELD(PER0, USB0OCP) |
+			RSTMGR_FIELD(PER0, USB1OCP) |
+			RSTMGR_FIELD(PER0, NANDOCP) |
+			RSTMGR_FIELD(PER0, SDMMCOCP) |
+			RSTMGR_FIELD(PER0, DMAOCP));
+
+	mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST),
+			RSTMGR_FIELD(PER0, EMAC0) |
+			RSTMGR_FIELD(PER0, EMAC1) |
+			RSTMGR_FIELD(PER0, EMAC2) |
+			RSTMGR_FIELD(PER0, USB0) |
+			RSTMGR_FIELD(PER0, USB1) |
+			RSTMGR_FIELD(PER0, NAND) |
+			RSTMGR_FIELD(PER0, SDMMC) |
+			RSTMGR_FIELD(PER0, DMA) |
+			RSTMGR_FIELD(PER0, SPIM0) |
+			RSTMGR_FIELD(PER0, SPIM1) |
+			RSTMGR_FIELD(PER0, SPIS0) |
+			RSTMGR_FIELD(PER0, SPIS1) |
+			RSTMGR_FIELD(PER0, EMACPTP) |
+			RSTMGR_FIELD(PER0, DMAIF0) |
+			RSTMGR_FIELD(PER0, DMAIF1) |
+			RSTMGR_FIELD(PER0, DMAIF2) |
+			RSTMGR_FIELD(PER0, DMAIF3) |
+			RSTMGR_FIELD(PER0, DMAIF4) |
+			RSTMGR_FIELD(PER0, DMAIF5) |
+			RSTMGR_FIELD(PER0, DMAIF6) |
+			RSTMGR_FIELD(PER0, DMAIF7));
+
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
+	mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
+			RSTMGR_FIELD(BRG, MPFE));
+#endif
+}
+
+void config_hps_hs_before_warm_reset(void)
+{
+	uint32_t or_mask = 0;
+
+	or_mask |= RSTMGR_HDSKEN_SDRSELFREFEN;
+	or_mask |= RSTMGR_HDSKEN_FPGAHSEN;
+	or_mask |= RSTMGR_HDSKEN_ETRSTALLEN;
+	or_mask |= RSTMGR_HDSKEN_L2FLUSHEN;
+	or_mask |= RSTMGR_HDSKEN_L3NOC_DBG;
+	or_mask |= RSTMGR_HDSKEN_DEBUG_L3NOC;
+
+	mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), or_mask);
+}
+
+static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match)
+{
+	int time_out = 1000;
+
+	while (time_out--) {
+		if ((mmio_read_32(addr) & mask) == match) {
+			return 0;
+		}
+	}
+	return -ETIMEDOUT;
+}
+
+int socfpga_bridges_enable(void)
+{
+	uint32_t status, poll_addr;
+
+	status = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS);
+
+	if (!status) {
+		/* Clear idle request */
+		mmio_setbits_32(S10_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_CLR), ~0);
+
+		/* De-assert all bridges */
+		mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), ~0);
+
+		/* Wait until idle ack becomes 0 */
+		poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLEACK);
+
+		return poll_idle_status(poll_addr, IDLE_DATA_MASK, 0);
+	}
+	return status;
+}
+
+int socfpga_bridges_disable(void)
+{
+	uint32_t poll_addr;
+
+	/* Set idle request */
+	mmio_write_32(S10_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_SET), ~0);
+
+	/* Enable NOC timeout */
+	mmio_setbits_32(SYSMGR_NOC_TIMEOUT, 1);
+
+	/* Wait until each idle ack bit toggle to 1 */
+	poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLEACK);
+	if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK))
+		return -ETIMEDOUT;
+
+	/* Wait until each idle status bit toggle to 1 */
+	poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLESTATUS);
+	if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK))
+		return -ETIMEDOUT;
+
+	/* Assert all bridges */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
+	mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
+		~(RSTMGR_FIELD(BRG, DDRSCH) | RSTMGR_FIELD(BRG, FPGA2SOC)));
+#elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
+	mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
+		~(RSTMGR_FIELD(BRG, MPFE) | RSTMGR_FIELD(BRG, FPGA2SOC)));
+#endif
+
+	/* Disable NOC timeout */
+	mmio_clrbits_32(S10_SYSMGR_CORE(SYSMGR_NOC_TIMEOUT), 1);
+
+	return 0;
+}
diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c
index 1ba48ea..d8a6c19 100644
--- a/plat/intel/soc/common/socfpga_psci.c
+++ b/plat/intel/soc/common/socfpga_psci.c
@@ -47,7 +47,7 @@
 	mmio_write_64(PLAT_CPUID_RELEASE, cpu_id);
 
 	/* release core reset */
-	mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
+	mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
 	return PSCI_E_SUCCESS;
 }
 
@@ -78,7 +78,7 @@
 			__func__, i, target_state->pwr_domain_state[i]);
 
 	/* assert core reset */
-	mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
+	mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
 
 }
 
@@ -117,7 +117,7 @@
 			__func__, i, target_state->pwr_domain_state[i]);
 
 	/* release core reset */
-	mmio_clrbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
+	mmio_clrbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id);
 }
 
 /*******************************************************************************
@@ -148,13 +148,13 @@
 	mmio_write_32(L2_RESET_DONE_REG, L2_RESET_DONE_STATUS);
 
 	/* Increase timeout */
-	mmio_write_32(SOCFPGA_RSTMGR_HDSKTIMEOUT, 0xffffff);
+	mmio_write_32(SOCFPGA_RSTMGR(HDSKTIMEOUT), 0xffffff);
 
 	/* Enable handshakes */
-	mmio_setbits_32(SOCFPGA_RSTMGR_HDSKEN, SOCFPGA_RSTMGR_HDSKEN_SET);
+	mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_SET);
 
 	/* Reset L2 module */
-	mmio_setbits_32(SOCFPGA_RSTMGR_COLDMODRST, 0x100);
+	mmio_setbits_32(SOCFPGA_RSTMGR(COLDMODRST), 0x100);
 
 	while (1)
 		wfi();
diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c
index e53d7ec..2296838 100644
--- a/plat/intel/soc/stratix10/bl2_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl2_plat_setup.c
@@ -19,10 +19,10 @@
 #include "socfpga_handoff.h"
 #include "socfpga_mailbox.h"
 #include "socfpga_private.h"
+#include "socfpga_reset_manager.h"
 #include "s10_clock_manager.h"
 #include "s10_memory_controller.h"
 #include "s10_pinmux.h"
-#include "s10_reset_manager.h"
 #include "s10_system_manager.h"
 #include "wdt/watchdog.h"
 
diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c
index 29bd176..48dad01 100644
--- a/plat/intel/soc/stratix10/bl31_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl31_plat_setup.c
@@ -17,12 +17,13 @@
 #include <platform_def.h>
 
 #include "socfpga_private.h"
-#include "s10_reset_manager.h"
+#include "socfpga_reset_manager.h"
 #include "s10_memory_controller.h"
 #include "s10_pinmux.h"
 #include "s10_clock_manager.h"
 #include "s10_system_manager.h"
 
+
 static entry_point_info_t bl32_image_ep_info;
 static entry_point_info_t bl33_image_ep_info;
 
diff --git a/plat/intel/soc/stratix10/include/s10_reset_manager.h b/plat/intel/soc/stratix10/include/s10_reset_manager.h
deleted file mode 100644
index 40e7bac..0000000
--- a/plat/intel/soc/stratix10/include/s10_reset_manager.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __S10_RESETMANAGER_H__
-#define __S10_RESETMANAGER_H__
-
-#define S10_RSTMGR_PER0MODRST				0xffd11024
-#define S10_RSTMGR_PER1MODRST				0xffd11028
-#define S10_RSTMGR_HDSKEN				0xffd11010
-#define S10_RSTMGR_BRGMODRST                            0xffd1102c
-
-
-#define S10_RSTMGR_PER0MODRST_EMAC0			0x00000001
-#define S10_RSTMGR_PER0MODRST_EMAC1			0x00000002
-#define S10_RSTMGR_PER0MODRST_EMAC2			0x00000004
-#define S10_RSTMGR_PER0MODRST_EMAC0OCP		0x00000100
-#define S10_RSTMGR_PER0MODRST_EMAC1OCP		0x00000200
-#define S10_RSTMGR_PER0MODRST_DMAOCP		0x00200000
-#define S10_RSTMGR_PER0MODRST_DMA			0x00010000
-#define S10_RSTMGR_PER0MODRST_EMAC0			0x00000001
-#define S10_RSTMGR_PER0MODRST_EMAC1			0x00000002
-#define S10_RSTMGR_PER0MODRST_EMAC2OCP		0x00000400
-#define S10_RSTMGR_PER0MODRST_EMAC2			0x00000004
-#define S10_RSTMGR_PER0MODRST_EMACPTP		0x00400000
-#define S10_RSTMGR_PER0MODRST_NANDOCP		0x00002000
-#define S10_RSTMGR_PER0MODRST_NAND			0x00000020
-#define S10_RSTMGR_PER0MODRST_SDMMCOCP		0x00008000
-#define S10_RSTMGR_PER0MODRST_SDMMC			0x00000080
-#define S10_RSTMGR_PER0MODRST_SPIM0			0x00020000
-#define S10_RSTMGR_PER0MODRST_SPIM1			0x00040000
-#define S10_RSTMGR_PER0MODRST_SPIS0			0x00080000
-#define S10_RSTMGR_PER0MODRST_SPIS1			0x00100000
-#define S10_RSTMGR_PER0MODRST_USB0OCP		0x00000800
-#define S10_RSTMGR_PER0MODRST_USB0			0x00000008
-#define S10_RSTMGR_PER0MODRST_USB1OCP		0x00001000
-#define S10_RSTMGR_PER0MODRST_USB1			0x00000010
-
-#define S10_RSTMGR_PER1MODRST_WATCHDOG0		0x1
-#define S10_RSTMGR_PER1MODRST_WATCHDOG1		0x2
-#define S10_RSTMGR_PER1MODRST_WATCHDOG2		0x4
-#define S10_RSTMGR_PER1MODRST_WATCHDOG3		0x8
-#define S10_RSTMGR_PER1MODRST_GPIO0			0x01000000
-#define S10_RSTMGR_PER1MODRST_GPIO0			0x01000000
-#define S10_RSTMGR_PER1MODRST_GPIO1			0x02000000
-#define S10_RSTMGR_PER1MODRST_GPIO1			0x02000000
-#define S10_RSTMGR_PER1MODRST_I2C0			0x00000100
-#define S10_RSTMGR_PER1MODRST_I2C0			0x00000100
-#define S10_RSTMGR_PER1MODRST_I2C1			0x00000200
-#define S10_RSTMGR_PER1MODRST_I2C1			0x00000200
-#define S10_RSTMGR_PER1MODRST_I2C2			0x00000400
-#define S10_RSTMGR_PER1MODRST_I2C2			0x00000400
-#define S10_RSTMGR_PER1MODRST_I2C3			0x00000800
-#define S10_RSTMGR_PER1MODRST_I2C3			0x00000800
-#define S10_RSTMGR_PER1MODRST_I2C4			0x00001000
-#define S10_RSTMGR_PER1MODRST_I2C4			0x00001000
-#define S10_RSTMGR_PER1MODRST_L4SYSTIMER0	0x00000010
-#define S10_RSTMGR_PER1MODRST_L4SYSTIMER1	0x00000020
-#define S10_RSTMGR_PER1MODRST_SPTIMER0		0x00000040
-#define S10_RSTMGR_PER1MODRST_SPTIMER0		0x00000040
-#define S10_RSTMGR_PER1MODRST_SPTIMER1		0x00000080
-#define S10_RSTMGR_PER1MODRST_SPTIMER1		0x00000080
-#define S10_RSTMGR_PER1MODRST_UART0			0x00010000
-#define S10_RSTMGR_PER1MODRST_UART0			0x00010000
-#define S10_RSTMGR_PER1MODRST_UART1			0x00020000
-#define S10_RSTMGR_PER1MODRST_UART1			0x00020000
-#define S10_RSTMGR_HDSKEN_DEBUG_L3NOC		0x00020000
-#define S10_RSTMGR_HDSKEN_ETRSTALLEN		0x00000008
-#define S10_RSTMGR_HDSKEN_FPGAHSEN			0x00000004
-#define S10_RSTMGR_HDSKEN_L2FLUSHEN			0x00000100
-#define S10_RSTMGR_HDSKEN_L3NOC_DBG			0x00010000
-
-#define S10_RSTMGR_HDSKEN_SDRSELFREFEN		0x00000001
-#define S10_RSTMGR_PER0MODRST_DMAIF0		0x01000000
-#define S10_RSTMGR_PER0MODRST_DMAIF1		0x02000000
-#define S10_RSTMGR_PER0MODRST_DMAIF2		0x04000000
-#define S10_RSTMGR_PER0MODRST_DMAIF3		0x08000000
-#define S10_RSTMGR_PER0MODRST_DMAIF4		0x10000000
-#define S10_RSTMGR_PER0MODRST_DMAIF5		0x20000000
-#define S10_RSTMGR_PER0MODRST_DMAIF6		0x40000000
-#define S10_RSTMGR_PER0MODRST_DMAIF7		0x80000000
-
-#define BRGMODRST_DDRSCH_MASK			0x40
-#define BRGMODRST_F2SSDRAM2_MASK		0x20
-#define BRGMODRST_F2SSDRAM1_MASK		0x10
-#define BRGMODRST_F2SSDRAM_MASK			0x08
-#define BRGMODRST_FPGA2SOC_MASK			0x04
-#define BRGMODRST_LWHPS2FPGA_MASK		0x02
-#define BRGMODRST_SOC2FPGA_MASK			0x01
-
-void deassert_peripheral_reset(void);
-void config_hps_hs_before_warm_reset(void);
-int socfpga_bridges_enable(void);
-int socfpga_bridges_disable(void);
-
-#endif
-
diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
index ab723f7..066585e 100644
--- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h
+++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
@@ -14,9 +14,7 @@
 
 /* Register Mapping */
 #define SOCFPGA_MMC_REG_BASE                    0xff808000
-
-#define SOCFPGA_RSTMGR_OFST                     0xffd11000
-#define SOCFPGA_RSTMGR_MPUMODRST_OFST           0xffd11020
+#define SOCFPGA_RSTMGR_REG_BASE			0xffd11000
 
 #endif /* PLATSOCFPGA_DEF_H */
 
diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk
index e7251c4..2b80a94 100644
--- a/plat/intel/soc/stratix10/platform.mk
+++ b/plat/intel/soc/stratix10/platform.mk
@@ -38,7 +38,6 @@
 		plat/intel/soc/stratix10/soc/s10_clock_manager.c	\
 		plat/intel/soc/stratix10/soc/s10_memory_controller.c	\
 		plat/intel/soc/stratix10/soc/s10_pinmux.c		\
-		plat/intel/soc/stratix10/soc/s10_reset_manager.c	\
 		plat/intel/soc/stratix10/soc/s10_system_manager.c	\
                 plat/intel/soc/common/bl2_plat_mem_params_desc.c	\
 		plat/intel/soc/common/socfpga_delay_timer.c		\
@@ -46,6 +45,7 @@
 		plat/intel/soc/common/socfpga_storage.c			\
 		plat/intel/soc/common/soc/socfpga_handoff.c		\
 		plat/intel/soc/common/soc/socfpga_mailbox.c		\
+		plat/intel/soc/common/soc/socfpga_reset_manager.c	\
 		plat/intel/soc/common/drivers/qspi/cadence_qspi.c	\
 		plat/intel/soc/common/drivers/wdt/watchdog.c
 
diff --git a/plat/intel/soc/stratix10/soc/s10_memory_controller.c b/plat/intel/soc/stratix10/soc/s10_memory_controller.c
index a0dafe1..ac756ab 100644
--- a/plat/intel/soc/stratix10/soc/s10_memory_controller.c
+++ b/plat/intel/soc/stratix10/soc/s10_memory_controller.c
@@ -15,7 +15,7 @@
 #include <string.h>
 
 #include "s10_memory_controller.h"
-#include "s10_reset_manager.h"
+#include "socfpga_reset_manager.h"
 
 #define ALT_CCU_NOC_DI_SET_MSK 0x10
 
@@ -185,7 +185,7 @@
 		return status;
 	}
 
-	mmio_clrbits_32(S10_RSTMGR_BRGMODRST, BRGMODRST_DDRSCH_MASK);
+	mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_FIELD(BRG, DDRSCH));
 
 	status = mem_calibration();
 	if (status) {
diff --git a/plat/intel/soc/stratix10/soc/s10_reset_manager.c b/plat/intel/soc/stratix10/soc/s10_reset_manager.c
deleted file mode 100644
index 5030e4f..0000000
--- a/plat/intel/soc/stratix10/soc/s10_reset_manager.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <arch_helpers.h>
-#include <assert.h>
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <drivers/arm/gicv2.h>
-#include <drivers/console.h>
-#include <errno.h>
-#include <lib/mmio.h>
-#include <plat/common/platform.h>
-#include <platform_def.h>
-
-#include "s10_reset_manager.h"
-#include "s10_system_manager.h"
-#include "socfpga_mailbox.h"
-
-void deassert_peripheral_reset(void)
-{
-	mmio_clrbits_32(S10_RSTMGR_PER1MODRST,
-			S10_RSTMGR_PER1MODRST_WATCHDOG0 |
-			S10_RSTMGR_PER1MODRST_WATCHDOG1 |
-			S10_RSTMGR_PER1MODRST_WATCHDOG2 |
-			S10_RSTMGR_PER1MODRST_WATCHDOG3 |
-			S10_RSTMGR_PER1MODRST_L4SYSTIMER0 |
-			S10_RSTMGR_PER1MODRST_L4SYSTIMER1 |
-			S10_RSTMGR_PER1MODRST_SPTIMER0 |
-			S10_RSTMGR_PER1MODRST_SPTIMER1 |
-			S10_RSTMGR_PER1MODRST_I2C0 |
-			S10_RSTMGR_PER1MODRST_I2C1 |
-			S10_RSTMGR_PER1MODRST_I2C2 |
-			S10_RSTMGR_PER1MODRST_I2C3 |
-			S10_RSTMGR_PER1MODRST_I2C4 |
-			S10_RSTMGR_PER1MODRST_UART0 |
-			S10_RSTMGR_PER1MODRST_UART1 |
-			S10_RSTMGR_PER1MODRST_GPIO0 |
-			S10_RSTMGR_PER1MODRST_GPIO1);
-
-	mmio_clrbits_32(S10_RSTMGR_PER0MODRST,
-			S10_RSTMGR_PER0MODRST_EMAC0OCP |
-			S10_RSTMGR_PER0MODRST_EMAC1OCP |
-			S10_RSTMGR_PER0MODRST_EMAC2OCP |
-			S10_RSTMGR_PER0MODRST_USB0OCP |
-			S10_RSTMGR_PER0MODRST_USB1OCP |
-			S10_RSTMGR_PER0MODRST_NANDOCP |
-			S10_RSTMGR_PER0MODRST_SDMMCOCP |
-			S10_RSTMGR_PER0MODRST_DMAOCP);
-
-	mmio_clrbits_32(S10_RSTMGR_PER0MODRST,
-			S10_RSTMGR_PER0MODRST_EMAC0 |
-			S10_RSTMGR_PER0MODRST_EMAC1 |
-			S10_RSTMGR_PER0MODRST_EMAC2 |
-			S10_RSTMGR_PER0MODRST_USB0 |
-			S10_RSTMGR_PER0MODRST_USB1 |
-			S10_RSTMGR_PER0MODRST_NAND |
-			S10_RSTMGR_PER0MODRST_SDMMC |
-			S10_RSTMGR_PER0MODRST_DMA |
-			S10_RSTMGR_PER0MODRST_SPIM0 |
-			S10_RSTMGR_PER0MODRST_SPIM1 |
-			S10_RSTMGR_PER0MODRST_SPIS0 |
-			S10_RSTMGR_PER0MODRST_SPIS1 |
-			S10_RSTMGR_PER0MODRST_EMACPTP |
-			S10_RSTMGR_PER0MODRST_DMAIF0 |
-			S10_RSTMGR_PER0MODRST_DMAIF1 |
-			S10_RSTMGR_PER0MODRST_DMAIF2 |
-			S10_RSTMGR_PER0MODRST_DMAIF3 |
-			S10_RSTMGR_PER0MODRST_DMAIF4 |
-			S10_RSTMGR_PER0MODRST_DMAIF5 |
-			S10_RSTMGR_PER0MODRST_DMAIF6 |
-			S10_RSTMGR_PER0MODRST_DMAIF7);
-
-}
-
-void config_hps_hs_before_warm_reset(void)
-{
-	uint32_t or_mask = 0;
-
-	or_mask |= S10_RSTMGR_HDSKEN_SDRSELFREFEN;
-	or_mask |= S10_RSTMGR_HDSKEN_FPGAHSEN;
-	or_mask |= S10_RSTMGR_HDSKEN_ETRSTALLEN;
-	or_mask |= S10_RSTMGR_HDSKEN_L2FLUSHEN;
-	or_mask |= S10_RSTMGR_HDSKEN_L3NOC_DBG;
-	or_mask |= S10_RSTMGR_HDSKEN_DEBUG_L3NOC;
-
-	mmio_setbits_32(S10_RSTMGR_HDSKEN, or_mask);
-}
-
-static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match)
-{
-	int time_out = 1000;
-
-	while (time_out--) {
-		if ((mmio_read_32(addr) & mask) == match) {
-			return 0;
-		}
-	}
-	return -ETIMEDOUT;
-}
-
-int socfpga_bridges_enable(void)
-{
-	uint32_t status, poll_addr;
-
-	status = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS);
-
-	if (!status) {
-		/* Clear idle request */
-		mmio_setbits_32(S10_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_CLR), ~0);
-
-		/* De-assert all bridges */
-		mmio_clrbits_32(S10_RSTMGR_BRGMODRST, ~0);
-
-		/* Wait until idle ack becomes 0 */
-		poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLEACK);
-
-		return poll_idle_status(poll_addr, IDLE_DATA_MASK, 0);
-	}
-	return status;
-}
-
-int socfpga_bridges_disable(void)
-{
-	uint32_t poll_addr;
-
-	/* Set idle request */
-	mmio_write_32(S10_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_SET), ~0);
-
-	/* Enable NOC timeout */
-	mmio_setbits_32(SYSMGR_NOC_TIMEOUT, 1);
-
-	/* Wait until each idle ack bit toggle to 1 */
-	poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLEACK);
-	if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK))
-		return -ETIMEDOUT;
-
-	/* Wait until each idle status bit toggle to 1 */
-	poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLESTATUS);
-	if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK))
-		return -ETIMEDOUT;
-
-	/* Assert all bridges */
-	mmio_setbits_32(S10_RSTMGR_BRGMODRST,
-		~(BRGMODRST_DDRSCH_MASK | BRGMODRST_FPGA2SOC_MASK));
-
-	/* Disable NOC timeout */
-	mmio_clrbits_32(S10_SYSMGR_CORE(SYSMGR_NOC_TIMEOUT), 1);
-
-	return 0;
-}