diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c
index 6c6c7af..8cb8020 100644
--- a/drivers/arm/gic/v3/gicv3_main.c
+++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -75,8 +75,12 @@
 	       plat_driver_data->g1s_interrupt_num == 0);
 
 	/* Check for system register support */
+#ifdef AARCH32
+	assert(read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT));
+#else
 	assert(read_id_aa64pfr0_el1() &
 			(ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT));
+#endif /* AARCH32 */
 
 	/* The GIC version should be 3.0 */
 	gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
diff --git a/drivers/arm/gic/v3/gicv3_private.h b/drivers/arm/gic/v3/gicv3_private.h
index 9aa8338..1344a88 100644
--- a/drivers/arm/gic/v3/gicv3_private.h
+++ b/drivers/arm/gic/v3/gicv3_private.h
@@ -79,9 +79,13 @@
  * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24]
  * are zeroes.
  */
+#ifdef AARCH32
+#define mpidr_from_gicr_typer(typer_val)	(((typer_val) >> 32) & 0xffffff)
+#else
 #define mpidr_from_gicr_typer(typer_val)				 \
-	((((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | \
-	 ((typer_val >> 32) & 0xffffff))
+	(((((typer_val) >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | \
+	 (((typer_val) >> 32) & 0xffffff))
+#endif
 
 /*******************************************************************************
  * Private GICv3 function prototypes for accessing entire registers.
diff --git a/drivers/arm/tzc/tzc400.c b/drivers/arm/tzc/tzc400.c
index e533587..ca088c3 100644
--- a/drivers/arm/tzc/tzc400.c
+++ b/drivers/arm/tzc/tzc400.c
@@ -206,7 +206,7 @@
 	 * Do address range check based on TZC configuration. A 64bit address is
 	 * the max and expected case.
 	 */
-	assert(((region_top <= (UINT64_MAX >> (64 - tzc400.addr_width))) &&
+	assert(((region_top <= _tzc_get_max_top_addr(tzc400.addr_width)) &&
 		(region_base < region_top)));
 
 	/* region_base and (region_top + 1) must be 4KB aligned */
diff --git a/drivers/arm/tzc/tzc_common_private.c b/drivers/arm/tzc/tzc_common_private.c
index dae6c3a..8b1ddf4 100644
--- a/drivers/arm/tzc/tzc_common_private.c
+++ b/drivers/arm/tzc/tzc_common_private.c
@@ -28,6 +28,8 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include <arch.h>
+#include <arch_helpers.h>
 #include <mmio.h>
 #include <tzc_common.h>
 
@@ -199,4 +201,35 @@
 
 	return id;
 }
+
+#ifdef AARCH32
+static unsigned long long _tzc_get_max_top_addr(int addr_width)
+{
+	/*
+	 * Assume at least 32 bit wide address and initialize the max.
+	 * This function doesn't use 64-bit integer arithmetic to avoid
+	 * having to implement additional compiler library functions.
+	 */
+	unsigned long long addr_mask = 0xFFFFFFFF;
+	uint32_t *addr_ptr = (uint32_t *)&addr_mask;
+
+	assert(addr_width >= 32);
+
+	/* This logic works only on little - endian platforms */
+	assert((read_sctlr() & SCTLR_EE_BIT) == 0);
+
+	/*
+	 * If required address width is greater than 32, populate the higher
+	 * 32 bits of the 64 bit field with the max address.
+	 */
+	if (addr_width > 32)
+		*(addr_ptr + 1) = ((1 << (addr_width - 32)) - 1);
+
+	return addr_mask;
+}
+#else
+#define _tzc_get_max_top_addr(addr_width)\
+	(UINT64_MAX >> (64 - (addr_width)))
+#endif /* AARCH32 */
+
 #endif
diff --git a/drivers/arm/tzc/tzc_dmc500.c b/drivers/arm/tzc/tzc_dmc500.c
index b2f0bf6..24e587c 100644
--- a/drivers/arm/tzc/tzc_dmc500.c
+++ b/drivers/arm/tzc/tzc_dmc500.c
@@ -211,7 +211,7 @@
 	 * Do address range check based on DMC-TZ configuration. A 43bit address
 	 * is the max and expected case.
 	 */
-	assert(((region_top <= (UINT64_MAX >> (64 - 43))) &&
+	assert(((region_top <= _tzc_get_max_top_addr(43)) &&
 		(region_base < region_top)));
 
 	/* region_base and (region_top + 1) must be 4KB aligned */