diff --git a/arch/system/gic/gic.h b/arch/system/gic/gic.h index 90a6615..9e9fb73 100644 --- a/arch/system/gic/gic.h +++ b/arch/system/gic/gic.h @@ -129,12 +129,18 @@ /* GICv3 Re-distributor interface registers & shifts */ #define GICR_PCPUBASE_SHIFT 0x11 +#define GICR_TYPER 0x08 #define GICR_WAKER 0x14 /* GICR_WAKER bit definitions */ #define WAKER_CA (1UL << 2) #define WAKER_PS (1UL << 1) +/* GICR_TYPER bit definitions */ +#define GICR_TYPER_AFF_SHIFT 32 +#define GICR_TYPER_AFF_MASK 0xffffffff +#define GICR_TYPER_LAST (1UL << 4) + /* GICv3 ICC_SRE register bit definitions*/ #define ICC_SRE_EN (1UL << 3) #define ICC_SRE_SRE (1UL << 0) diff --git a/arch/system/gic/gic_v3.c b/arch/system/gic/gic_v3.c new file mode 100644 index 0000000..2fef539 --- /dev/null +++ b/arch/system/gic/gic_v3.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr) +{ + uint32_t cpu_aff, gicr_aff; + uint64_t gicr_typer; + uintptr_t addr; + + /* Construct the affinity as used by GICv3. MPIDR and GIC affinity level + * mask is the same. + */ + cpu_aff = ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) << + GICV3_AFF0_SHIFT; + cpu_aff |= ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) << + GICV3_AFF1_SHIFT; + cpu_aff |= ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) << + GICV3_AFF2_SHIFT; + cpu_aff |= ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) << + GICV3_AFF3_SHIFT; + + addr = gicr_base; + do { + gicr_typer = gicr_read_typer(addr); + + gicr_aff = (gicr_typer >> GICR_TYPER_AFF_SHIFT) & + GICR_TYPER_AFF_MASK; + if (cpu_aff == gicr_aff) { + INFO("GICv3 - Found RDIST for MPIDR(0x%lx) at 0x%lx\n", + mpidr, addr); + return addr; + } + + /* TODO: + * For GICv4 we need to adjust the Base address based on + * GICR_TYPER.VLPIS + */ + addr += (1 << GICR_PCPUBASE_SHIFT); + + } while (!(gicr_typer & GICR_TYPER_LAST)); + + /* If we get here we did not find a match. */ + ERROR("GICv3 - Did not find RDIST for CPU with MPIDR 0x%lx\n", mpidr); + return (uintptr_t)NULL; +} diff --git a/arch/system/gic/gic_v3.h b/arch/system/gic/gic_v3.h index 9ff46f1..df7e7fd 100644 --- a/arch/system/gic/gic_v3.h +++ b/arch/system/gic/gic_v3.h @@ -31,19 +31,35 @@ #ifndef __GIC_V3_H__ #define __GIC_V3_H__ +#include #include +#define GICV3_AFFLVL_MASK 0xff +#define GICV3_AFF0_SHIFT 0 +#define GICV3_AFF1_SHIFT 8 +#define GICV3_AFF2_SHIFT 16 +#define GICV3_AFF3_SHIFT 24 +#define GICV3_AFFINITY_MASK 0xffffffff + +uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr); + /******************************************************************************* * GIC Redistributor interface accessors ******************************************************************************/ -static inline unsigned int gicr_read_waker(unsigned int base) +static inline uint32_t gicr_read_waker(uintptr_t base) { return mmio_read_32(base + GICR_WAKER); } -static inline void gicr_write_waker(unsigned int base, unsigned int val) +static inline void gicr_write_waker(uintptr_t base, uint32_t val) { mmio_write_32(base + GICR_WAKER, val); } +static inline uint64_t gicr_read_typer(uintptr_t base) +{ + return mmio_read_64(base + GICR_TYPER); +} + + #endif /* __GIC_V3_H__ */ diff --git a/bl31/bl31.mk b/bl31/bl31.mk index 3448623..228e530 100644 --- a/bl31/bl31.mk +++ b/bl31/bl31.mk @@ -40,11 +40,11 @@ BL31_ASM_OBJS := bl31_entrypoint.o runtime_exceptions.o psci_entry.o \ spinlock.o gic_v3_sysregs.o fvp_helpers.o -BL31_C_OBJS := bl31_main.o bl31_plat_setup.o bl31_arch_setup.o \ - exception_handlers.o bakery_lock.o cci400.o \ - fvp_common.o fvp_pm.o fvp_pwrc.o fvp_topology.o \ - runtime_svc.o fvp_gic.o gic_v2.o psci_setup.o \ - psci_common.o psci_afflvl_on.o psci_main.o \ +BL31_C_OBJS := bl31_main.o bl31_plat_setup.o bl31_arch_setup.o \ + exception_handlers.o bakery_lock.o cci400.o \ + fvp_common.o fvp_pm.o fvp_pwrc.o fvp_topology.o \ + runtime_svc.o fvp_gic.o gic_v2.o gic_v3.o psci_setup.o \ + psci_common.o psci_afflvl_on.o psci_main.o \ psci_afflvl_off.o psci_afflvl_suspend.o BL31_ENTRY_POINT := bl31_entrypoint diff --git a/docs/change-log.md b/docs/change-log.md index 1b9b0d2..7d6d8f6 100644 --- a/docs/change-log.md +++ b/docs/change-log.md @@ -94,6 +94,10 @@ floating point registers. Also added `-mgeneral-regs-only` flag to GCC settings to prevent generation of code using floating point registers. +* The GICv3 distributor can have more ports than CPUs are available in the + system. The GICv3 re-distributors are probed to work out which + re-distributor should be used with which CPU. + ARM Trusted Firmware - version 0.2 ================================== diff --git a/include/debug.h b/include/debug.h index e3c3c93..e8ba7e2 100644 --- a/include/debug.h +++ b/include/debug.h @@ -55,5 +55,15 @@ #define ERROR(...) printf("ERROR: " __VA_ARGS__) + +/* For the moment this Panic function is very basic, Report an error and + * spin. This can be expanded in the future to provide more information. + */ +static inline void panic(void) +{ + ERROR("PANIC\n"); + while (1); +} + #endif /* __ASSEMBLY__ */ #endif /* __DEBUG_H__ */ diff --git a/include/mmio.h b/include/mmio.h index b72daca..313448e 100644 --- a/include/mmio.h +++ b/include/mmio.h @@ -38,6 +38,9 @@ extern void mmio_write_32(uintptr_t addr, uint32_t value); extern uint32_t mmio_read_32(uintptr_t addr); +extern void mmio_write_64(uintptr_t addr, uint64_t value); +extern uint64_t mmio_read_64(uintptr_t addr); + #endif /*__ASSEMBLY__*/ #endif /* __MMIO_H__ */ diff --git a/lib/mmio.c b/lib/mmio.c index 36ff780..b654be7 100644 --- a/lib/mmio.c +++ b/lib/mmio.c @@ -35,7 +35,17 @@ *(volatile uint32_t*)addr = value; } -unsigned mmio_read_32(uintptr_t addr) +uint32_t mmio_read_32(uintptr_t addr) { return *(volatile uint32_t*)addr; } + +void mmio_write_64(uintptr_t addr, uint64_t value) +{ + *(volatile uint64_t*)addr = value; +} + +uint64_t mmio_read_64(uintptr_t addr) +{ + return *(volatile uint64_t*)addr; +} diff --git a/plat/fvp/fvp_gic.c b/plat/fvp/fvp_gic.c index b149b08..6dd13ec 100644 --- a/plat/fvp/fvp_gic.c +++ b/plat/fvp/fvp_gic.c @@ -28,9 +28,11 @@ * POSSIBILITY OF SUCH DAMAGE. */ +#include #include #include #include +#include /******************************************************************************* @@ -46,7 +48,8 @@ ******************************************************************************/ void gicv3_cpuif_setup(void) { - unsigned int scr_val, val, base; + unsigned int scr_val, val; + uintptr_t base; /* * When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep @@ -55,13 +58,15 @@ * to clear (GICv3 Architecture specification 5.4.23). * GICR_WAKER is NOT banked per CPU, compute the correct base address * per CPU. - * - * TODO: - * For GICv4 we also need to adjust the Base address based on - * GICR_TYPER.VLPIS */ - base = BASE_GICR_BASE + - (platform_get_core_pos(read_mpidr()) << GICR_PCPUBASE_SHIFT); + base = gicv3_get_rdist(BASE_GICR_BASE, read_mpidr()); + if (base == (uintptr_t)NULL) { + /* No re-distributor base address. This interface cannot be + * configured. + */ + panic(); + } + val = gicr_read_waker(base); val &= ~WAKER_PS; @@ -108,7 +113,8 @@ ******************************************************************************/ void gicv3_cpuif_deactivate(void) { - unsigned int val, base; + unsigned int val; + uintptr_t base; /* * When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and @@ -116,13 +122,15 @@ * (GICv3 Architecture specification 5.4.23). * GICR_WAKER is NOT banked per CPU, compute the correct base address * per CPU. - * - * TODO: - * For GICv4 we also need to adjust the Base address based on - * GICR_TYPER.VLPIS */ - base = BASE_GICR_BASE + - (platform_get_core_pos(read_mpidr()) << GICR_PCPUBASE_SHIFT); + base = gicv3_get_rdist(BASE_GICR_BASE, read_mpidr()); + if (base == (uintptr_t)NULL) { + /* No re-distributor base address. This interface cannot be + * configured. + */ + panic(); + } + val = gicr_read_waker(base); val |= WAKER_PS; gicr_write_waker(base, val);