diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c index eeaa24a..6a3f062 100644 --- a/bl1/aarch64/bl1_arch_setup.c +++ b/bl1/aarch64/bl1_arch_setup.c @@ -37,17 +37,8 @@ ******************************************************************************/ void bl1_arch_setup(void) { - /* - * Set the next EL to be AArch64, route external abort and SError - * interrupts to EL3 - */ - write_scr_el3(SCR_RES1_BITS | SCR_RW_BIT | SCR_EA_BIT); - - /* - * Enable SError and Debug exceptions - */ - enable_serror(); - enable_debug_exceptions(); + /* Set the next EL to be AArch64 */ + write_scr_el3(SCR_RES1_BITS | SCR_RW_BIT); } /******************************************************************************* diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S index dd7d78f..e7f92c7 100644 --- a/bl1/aarch64/bl1_entrypoint.S +++ b/bl1/aarch64/bl1_entrypoint.S @@ -76,6 +76,14 @@ */ adr x0, bl1_exceptions msr vbar_el3, x0 + isb + + /* --------------------------------------------- + * Enable the SError interrupt now that the + * exception vectors have been setup. + * --------------------------------------------- + */ + msr daifclr, #DAIF_ABT_BIT /* --------------------------------------------------------------------- * The initial state of the Architectural feature trap register diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S index 8ab9df8..13b34b7 100644 --- a/bl1/aarch64/bl1_exceptions.S +++ b/bl1/aarch64/bl1_exceptions.S @@ -112,6 +112,9 @@ */ .align 7 SynchronousExceptionA64: + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + /* ------------------------------------------------ * Only a single SMC exception from BL2 to ask * BL1 to pass EL3 control to BL31 is expected diff --git a/bl2/aarch64/bl2_entrypoint.S b/bl2/aarch64/bl2_entrypoint.S index d3b0f55..2f058da 100644 --- a/bl2/aarch64/bl2_entrypoint.S +++ b/bl2/aarch64/bl2_entrypoint.S @@ -53,6 +53,14 @@ */ adr x0, early_exceptions msr vbar_el1, x0 + isb + + /* --------------------------------------------- + * Enable the SError interrupt now that the + * exception vectors have been setup. + * --------------------------------------------- + */ + msr daifclr, #DAIF_ABT_BIT /* --------------------------------------------- * Enable the instruction cache, stack pointer diff --git a/bl31/aarch64/bl31_arch_setup.c b/bl31/aarch64/bl31_arch_setup.c index f67881e..a88b029 100644 --- a/bl31/aarch64/bl31_arch_setup.c +++ b/bl31/aarch64/bl31_arch_setup.c @@ -42,18 +42,8 @@ ******************************************************************************/ void bl31_arch_setup(void) { - /* - * Route external abort and SError interrupts to EL3 - * other SCR bits will be configured before exiting to a lower exception - * level - */ - write_scr_el3(SCR_RES1_BITS | SCR_EA_BIT); - - /* - * Enable SError and Debug exceptions - */ - enable_serror(); - enable_debug_exceptions(); + /* Set the RES1 bits in the SCR_EL3 */ + write_scr_el3(SCR_RES1_BITS); /* Program the counter frequency */ write_cntfrq_el0(plat_get_syscnt_freq()); diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index c3a09bf..a088c2e 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -98,6 +98,14 @@ */ adr x1, runtime_exceptions msr vbar_el3, x1 + isb + + /* --------------------------------------------- + * Enable the SError interrupt now that the + * exception vectors have been setup. + * --------------------------------------------- + */ + msr daifclr, #DAIF_ABT_BIT /* --------------------------------------------------------------------- * The initial state of the Architectural feature trap register diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index 996dedc..f5be9e0 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -44,6 +44,9 @@ * ----------------------------------------------------- */ .macro handle_sync_exception + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] mrs x30, esr_el3 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH @@ -70,6 +73,9 @@ * ----------------------------------------------------- */ .macro handle_interrupt_exception label + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] bl save_gp_registers diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index 1838d5a..8fae1b2 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -78,6 +78,14 @@ */ adr x0, tsp_exceptions msr vbar_el1, x0 + isb + + /* --------------------------------------------- + * Enable the SError interrupt now that the + * exception vectors have been setup. + * --------------------------------------------- + */ + msr daifclr, #DAIF_ABT_BIT /* --------------------------------------------- * Enable the instruction cache, stack pointer @@ -187,6 +195,10 @@ */ adr x0, tsp_exceptions msr vbar_el1, x0 + isb + + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT /* --------------------------------------------- * Enable the instruction cache, stack pointer diff --git a/bl32/tsp/aarch64/tsp_exceptions.S b/bl32/tsp/aarch64/tsp_exceptions.S index f84b5e0..4c0d436 100644 --- a/bl32/tsp/aarch64/tsp_exceptions.S +++ b/bl32/tsp/aarch64/tsp_exceptions.S @@ -120,6 +120,9 @@ .align 7 irq_sp_elx: + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + save_caller_regs_and_lr /* We just update some statistics in the handler */ bl tsp_irq_received @@ -132,6 +135,9 @@ .align 7 fiq_sp_elx: + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + save_caller_regs_and_lr bl tsp_fiq_handler cbz x0, fiq_sp_elx_done diff --git a/services/std_svc/psci/psci_entry.S b/services/std_svc/psci/psci_entry.S index e9ad130..68b917e 100644 --- a/services/std_svc/psci/psci_entry.S +++ b/services/std_svc/psci/psci_entry.S @@ -88,6 +88,13 @@ isb /* --------------------------------------------- + * Enable the SError interrupt now that the + * exception vectors have been setup. + * --------------------------------------------- + */ + msr daifclr, #DAIF_ABT_BIT + + /* --------------------------------------------- * Use SP_EL0 for the C runtime stack. * --------------------------------------------- */