diff --git a/include/lib/cpus/aarch64/cortex_ares.h b/include/lib/cpus/aarch64/cortex_ares.h deleted file mode 100644 index cfc36e4..0000000 --- a/include/lib/cpus/aarch64/cortex_ares.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CORTEX_ARES_H -#define CORTEX_ARES_H - -#include - -/* Cortex-ARES MIDR for revision 0 */ -#define CORTEX_ARES_MIDR U(0x410fd0c0) - -/******************************************************************************* - * CPU Extended Control register specific definitions. - ******************************************************************************/ -#define CORTEX_ARES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4 - -/* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */ -#define CORTEX_ARES_CORE_PWRDN_EN_MASK U(0x1) - -#define CORTEX_ARES_ACTLR_AMEN_BIT (U(1) << 4) - -#define CORTEX_ARES_AMU_NR_COUNTERS U(5) -#define CORTEX_ARES_AMU_GROUP0_MASK U(0x1f) - -/* Instruction patching registers */ -#define CPUPSELR_EL3 S3_6_C15_C8_0 -#define CPUPCR_EL3 S3_6_C15_C8_1 -#define CPUPOR_EL3 S3_6_C15_C8_2 -#define CPUPMR_EL3 S3_6_C15_C8_3 - -#endif /* CORTEX_ARES_H */ diff --git a/include/lib/cpus/aarch64/cortex_helios.h b/include/lib/cpus/aarch64/cortex_helios.h deleted file mode 100644 index 0c11a9a..0000000 --- a/include/lib/cpus/aarch64/cortex_helios.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CORTEX_HELIOS_H -#define CORTEX_HELIOS_H - -#include - -#define CORTEX_HELIOS_MIDR U(0x410FD060) - -/******************************************************************************* - * CPU Extended Control register specific definitions. - ******************************************************************************/ -#define CORTEX_HELIOS_ECTLR_EL1 S3_0_C15_C1_4 - -/******************************************************************************* - * CPU Auxiliary Control register specific definitions. - ******************************************************************************/ -#define CORTEX_HELIOS_CPUACTLR_EL1 S3_0_C15_C1_0 - -/******************************************************************************* - * CPU Power Control register specific definitions. - ******************************************************************************/ - -#define CORTEX_HELIOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) - -#endif /* CORTEX_HELIOS_H */ diff --git a/include/lib/cpus/aarch64/neoverse_e1.h b/include/lib/cpus/aarch64/neoverse_e1.h new file mode 100644 index 0000000..7084604 --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_e1.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_E1_H +#define NEOVERSE_E1_H + +#include + +#define NEOVERSE_E1_MIDR U(0x410FD060) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_E1_ECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_E1_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Power Control register specific definitions. + ******************************************************************************/ + +#define NEOVERSE_E1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +#endif /* NEOVERSE_E1_H */ diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h new file mode 100644 index 0000000..908993e --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_N1_H +#define NEOVERSE_N1_H + +#include + +/* Neoverse N1 MIDR for revision 0 */ +#define NEOVERSE_N1_MIDR U(0x410fd0c0) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 + +/* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */ +#define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1) + +#define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4) + +#define NEOVERSE_N1_AMU_NR_COUNTERS U(5) +#define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f) + +/* Instruction patching registers */ +#define CPUPSELR_EL3 S3_6_C15_C8_0 +#define CPUPCR_EL3 S3_6_C15_C8_1 +#define CPUPOR_EL3 S3_6_C15_C8_2 +#define CPUPMR_EL3 S3_6_C15_C8_3 + +#endif /* NEOVERSE_N1_H */ diff --git a/lib/cpus/aarch64/cortex_ares.S b/lib/cpus/aarch64/cortex_ares.S deleted file mode 100644 index 2788174..0000000 --- a/lib/cpus/aarch64/cortex_ares.S +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include - -/* -------------------------------------------------- - * Errata Workaround for Cortex-Ares Errata - * This applies to revision r0p0 and r1p0 of Cortex-Ares. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_ares_1043202_wa - /* Compare x0 against revision r1p0 */ - mov x17, x30 - bl check_errata_1043202 - cbz x0, 1f - - /* Apply instruction patching sequence */ - ldr x0, =0x0 - msr CPUPSELR_EL3, x0 - ldr x0, =0xF3BF8F2F - msr CPUPOR_EL3, x0 - ldr x0, =0xFFFFFFFF - msr CPUPMR_EL3, x0 - ldr x0, =0x800200071 - msr CPUPCR_EL3, x0 - isb -1: - ret x17 -endfunc errata_ares_1043202_wa - -func check_errata_1043202 - /* Applies to r0p0 and r1p0 */ - mov x1, #0x10 - b cpu_rev_var_ls -endfunc check_errata_1043202 - -func cortex_ares_reset_func - mov x19, x30 - bl cpu_get_rev_var - mov x18, x0 - -#if ERRATA_ARES_1043202 - mov x0, x18 - bl errata_ares_1043202_wa -#endif - -#if ENABLE_AMU - /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ - mrs x0, actlr_el3 - orr x0, x0, #CORTEX_ARES_ACTLR_AMEN_BIT - msr actlr_el3, x0 - isb - - /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ - mrs x0, actlr_el2 - orr x0, x0, #CORTEX_ARES_ACTLR_AMEN_BIT - msr actlr_el2, x0 - isb - - /* Enable group0 counters */ - mov x0, #CORTEX_ARES_AMU_GROUP0_MASK - msr CPUAMCNTENSET_EL0, x0 - isb -#endif - ret x19 -endfunc cortex_ares_reset_func - - /* --------------------------------------------- - * HW will do the cache maintenance while powering down - * --------------------------------------------- - */ -func cortex_ares_core_pwr_dwn - /* --------------------------------------------- - * Enable CPU power down bit in power control register - * --------------------------------------------- - */ - mrs x0, CORTEX_ARES_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_ARES_CORE_PWRDN_EN_MASK - msr CORTEX_ARES_CPUPWRCTLR_EL1, x0 - isb - ret -endfunc cortex_ares_core_pwr_dwn - -#if REPORT_ERRATA -/* - * Errata printing function for Cortex-Ares. Must follow AAPCS. - */ -func cortex_ares_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_ARES_1043202, cortex_ares, 1043202 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_ares_errata_report -#endif - - /* --------------------------------------------- - * This function provides cortex_ares specific - * register information for crash reporting. - * It needs to return with x6 pointing to - * a list of register names in ascii and - * x8 - x15 having values of registers to be - * reported. - * --------------------------------------------- - */ -.section .rodata.cortex_ares_regs, "aS" -cortex_ares_regs: /* The ascii list of register names to be reported */ - .asciz "cpuectlr_el1", "" - -func cortex_ares_cpu_reg_dump - adr x6, cortex_ares_regs - mrs x8, CORTEX_ARES_CPUECTLR_EL1 - ret -endfunc cortex_ares_cpu_reg_dump - -declare_cpu_ops cortex_ares, CORTEX_ARES_MIDR, \ - cortex_ares_reset_func, \ - cortex_ares_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_ares_pubsub.c b/lib/cpus/aarch64/cortex_ares_pubsub.c deleted file mode 100644 index 4a4f333..0000000 --- a/lib/cpus/aarch64/cortex_ares_pubsub.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -static void *cortex_ares_context_save(const void *arg) -{ - if (midr_match(CORTEX_ARES_MIDR) != 0) - cpuamu_context_save(CORTEX_ARES_AMU_NR_COUNTERS); - - return (void *)0; -} - -static void *cortex_ares_context_restore(const void *arg) -{ - if (midr_match(CORTEX_ARES_MIDR) != 0) - cpuamu_context_restore(CORTEX_ARES_AMU_NR_COUNTERS); - - return (void *)0; -} - -SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, cortex_ares_context_save); -SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_finish, cortex_ares_context_restore); diff --git a/lib/cpus/aarch64/cortex_helios.S b/lib/cpus/aarch64/cortex_helios.S deleted file mode 100644 index 7d3d7e4..0000000 --- a/lib/cpus/aarch64/cortex_helios.S +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include -#include -#include -#include -#include -#include -#include - -func cortex_helios_cpu_pwr_dwn - mrs x0, CORTEX_HELIOS_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_HELIOS_CPUPWRCTLR_EL1, x0 - isb - ret -endfunc cortex_helios_cpu_pwr_dwn - -#if REPORT_ERRATA -/* - * Errata printing function for Cortex Helios. Must follow AAPCS. - */ -func cortex_helios_errata_report - ret -endfunc cortex_helios_errata_report -#endif - - -.section .rodata.cortex_helios_regs, "aS" -cortex_helios_regs: /* The ascii list of register names to be reported */ - .asciz "cpuectlr_el1", "" - -func cortex_helios_cpu_reg_dump - adr x6, cortex_helios_regs - mrs x8, CORTEX_HELIOS_ECTLR_EL1 - ret -endfunc cortex_helios_cpu_reg_dump - -declare_cpu_ops cortex_helios, CORTEX_HELIOS_MIDR, \ - CPU_NO_RESET_FUNC, \ - cortex_helios_cpu_pwr_dwn diff --git a/lib/cpus/aarch64/neoverse_e1.S b/lib/cpus/aarch64/neoverse_e1.S new file mode 100644 index 0000000..8e40306 --- /dev/null +++ b/lib/cpus/aarch64/neoverse_e1.S @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include +#include +#include +#include +#include +#include + +func neoverse_e1_cpu_pwr_dwn + mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1 + orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr NEOVERSE_E1_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc neoverse_e1_cpu_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for Neoverse N1. Must follow AAPCS. + */ +func neoverse_e1_errata_report + ret +endfunc neoverse_e1_errata_report +#endif + + +.section .rodata.neoverse_e1_regs, "aS" +neoverse_e1_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func neoverse_e1_cpu_reg_dump + adr x6, neoverse_e1_regs + mrs x8, NEOVERSE_E1_ECTLR_EL1 + ret +endfunc neoverse_e1_cpu_reg_dump + +declare_cpu_ops neoverse_e1, NEOVERSE_E1_MIDR, \ + CPU_NO_RESET_FUNC, \ + neoverse_e1_cpu_pwr_dwn diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S new file mode 100644 index 0000000..c6a5c08 --- /dev/null +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +/* -------------------------------------------------- + * Errata Workaround for Neoverse N1 Errata + * This applies to revision r0p0 and r1p0 of Neoverse N1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_n1_1043202_wa + /* Compare x0 against revision r1p0 */ + mov x17, x30 + bl check_errata_1043202 + cbz x0, 1f + + /* Apply instruction patching sequence */ + ldr x0, =0x0 + msr CPUPSELR_EL3, x0 + ldr x0, =0xF3BF8F2F + msr CPUPOR_EL3, x0 + ldr x0, =0xFFFFFFFF + msr CPUPMR_EL3, x0 + ldr x0, =0x800200071 + msr CPUPCR_EL3, x0 + isb +1: + ret x17 +endfunc errata_n1_1043202_wa + +func check_errata_1043202 + /* Applies to r0p0 and r1p0 */ + mov x1, #0x10 + b cpu_rev_var_ls +endfunc check_errata_1043202 + +func neoverse_n1_reset_func + mov x19, x30 + bl cpu_get_rev_var + mov x18, x0 + +#if ERRATA_N1_1043202 + mov x0, x18 + bl errata_n1_1043202_wa +#endif + +#if ENABLE_AMU + /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ + mrs x0, actlr_el3 + orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT + msr actlr_el3, x0 + isb + + /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ + mrs x0, actlr_el2 + orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT + msr actlr_el2, x0 + isb + + /* Enable group0 counters */ + mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK + msr CPUAMCNTENSET_EL0, x0 + isb +#endif + ret x19 +endfunc neoverse_n1_reset_func + + /* --------------------------------------------- + * HW will do the cache maintenance while powering down + * --------------------------------------------- + */ +func neoverse_n1_core_pwr_dwn + /* --------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------- + */ + mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 + orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK + msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc neoverse_n1_core_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for Neoverse N1. Must follow AAPCS. + */ +func neoverse_n1_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 + + ldp x8, x30, [sp], #16 + ret +endfunc neoverse_n1_errata_report +#endif + + /* --------------------------------------------- + * This function provides neoverse_n1 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.neoverse_n1_regs, "aS" +neoverse_n1_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func neoverse_n1_cpu_reg_dump + adr x6, neoverse_n1_regs + mrs x8, NEOVERSE_N1_CPUECTLR_EL1 + ret +endfunc neoverse_n1_cpu_reg_dump + +declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \ + neoverse_n1_reset_func, \ + neoverse_n1_core_pwr_dwn diff --git a/lib/cpus/aarch64/neoverse_n1_pubsub.c b/lib/cpus/aarch64/neoverse_n1_pubsub.c new file mode 100644 index 0000000..b1b7bb8 --- /dev/null +++ b/lib/cpus/aarch64/neoverse_n1_pubsub.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +static void *neoverse_n1_context_save(const void *arg) +{ + if (midr_match(NEOVERSE_N1_MIDR) != 0) + cpuamu_context_save(NEOVERSE_N1_AMU_NR_COUNTERS); + + return (void *)0; +} + +static void *neoverse_n1_context_restore(const void *arg) +{ + if (midr_match(NEOVERSE_N1_MIDR) != 0) + cpuamu_context_restore(NEOVERSE_N1_AMU_NR_COUNTERS); + + return (void *)0; +} + +SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, neoverse_n1_context_save); +SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_finish, neoverse_n1_context_restore); diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 40a8ac7..7824df2 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -120,8 +120,8 @@ ERRATA_A72_859971 ?=0 # Flag to apply T32 CLREX workaround during reset. This erratum applies -# only to r0p0 and r1p0 of the Ares cpu. -ERRATA_ARES_1043202 ?=1 +# only to r0p0 and r1p0 of the Neoverse N1 cpu. +ERRATA_N1_1043202 ?=1 # Flag to apply DSU erratum 936184. This erratum applies to DSUs containing # the ACP interface and revision < r2p0. Applying the workaround results in @@ -188,9 +188,9 @@ $(eval $(call assert_boolean,ERRATA_A72_859971)) $(eval $(call add_define,ERRATA_A72_859971)) -# Process ERRATA_ARES_1043202 flag -$(eval $(call assert_boolean,ERRATA_ARES_1043202)) -$(eval $(call add_define,ERRATA_ARES_1043202)) +# Process ERRATA_N1_1043202 flag +$(eval $(call assert_boolean,ERRATA_N1_1043202)) +$(eval $(call add_define,ERRATA_N1_1043202)) # Process ERRATA_DSU_936184 flag $(eval $(call assert_boolean,ERRATA_DSU_936184)) diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 42a9095..8e69399 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -103,7 +103,7 @@ lib/cpus/aarch64/cortex_a73.S \ lib/cpus/aarch64/cortex_a75.S \ lib/cpus/aarch64/cortex_a76.S \ - lib/cpus/aarch64/cortex_ares.S \ + lib/cpus/aarch64/neoverse_n1.S \ lib/cpus/aarch64/cortex_deimos.S else FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S @@ -214,7 +214,7 @@ ifeq (${ENABLE_AMU},1) BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ - lib/cpus/aarch64/cortex_ares_pubsub.c \ + lib/cpus/aarch64/neoverse_n1_pubsub.c \ lib/cpus/aarch64/cpuamu.c \ lib/cpus/aarch64/cpuamu_helpers.S endif diff --git a/plat/arm/board/n1sdp/aarch64/n1sdp_helper.S b/plat/arm/board/n1sdp/aarch64/n1sdp_helper.S index 6eb01aa..c03185a 100644 --- a/plat/arm/board/n1sdp/aarch64/n1sdp_helper.S +++ b/plat/arm/board/n1sdp/aarch64/n1sdp_helper.S @@ -1,12 +1,12 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include #include -#include +#include #include #include @@ -58,17 +58,17 @@ */ func plat_reset_handler - jump_if_cpu_midr CORTEX_ARES_MIDR, ARES + jump_if_cpu_midr NEOVERSE_N1_MIDR, N1 ret /* ----------------------------------------------------- * Disable CPU power down bit in power control register * ----------------------------------------------------- */ -ARES: - mrs x0, CORTEX_ARES_CPUPWRCTLR_EL1 - bic x0, x0, #CORTEX_ARES_CORE_PWRDN_EN_MASK - msr CORTEX_ARES_CPUPWRCTLR_EL1, x0 +N1: + mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 + bic x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK + msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 isb ret endfunc plat_reset_handler diff --git a/plat/arm/board/n1sdp/platform.mk b/plat/arm/board/n1sdp/platform.mk index 2b68f65..653d081 100644 --- a/plat/arm/board/n1sdp/platform.mk +++ b/plat/arm/board/n1sdp/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -12,7 +12,7 @@ PLAT_INCLUDES := -I${N1SDP_BASE}/include -N1SDP_CPU_SOURCES := lib/cpus/aarch64/cortex_ares.S +N1SDP_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S N1SDP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ diff --git a/plat/arm/board/sgiclarka/platform.mk b/plat/arm/board/sgiclarka/platform.mk index 1a8b157..81e416e 100644 --- a/plat/arm/board/sgiclarka/platform.mk +++ b/plat/arm/board/sgiclarka/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -10,7 +10,7 @@ PLAT_INCLUDES += -I${SGICLARKA_BASE}/include/ -SGI_CPU_SOURCES := lib/cpus/aarch64/cortex_ares.S +SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S BL1_SOURCES += ${SGI_CPU_SOURCES} diff --git a/plat/arm/board/sgiclarkh/platform.mk b/plat/arm/board/sgiclarkh/platform.mk index 222ca60..1e93d93 100644 --- a/plat/arm/board/sgiclarkh/platform.mk +++ b/plat/arm/board/sgiclarkh/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2018, Arm Limited. All rights reserved. +# Copyright (c) 2018-2019, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -10,7 +10,7 @@ PLAT_INCLUDES += -I${SGICLARKH_BASE}/include/ -SGI_CPU_SOURCES := lib/cpus/aarch64/cortex_helios.S +SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_e1.S BL1_SOURCES += ${SGI_CPU_SOURCES} diff --git a/plat/arm/css/sgi/aarch64/sgi_helper.S b/plat/arm/css/sgi/aarch64/sgi_helper.S index d79f1aa..b80903d 100644 --- a/plat/arm/css/sgi/aarch64/sgi_helper.S +++ b/plat/arm/css/sgi/aarch64/sgi_helper.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include .globl plat_arm_calc_core_pos @@ -59,7 +59,7 @@ */ func plat_reset_handler jump_if_cpu_midr CORTEX_A75_MIDR, A75 - jump_if_cpu_midr CORTEX_ARES_MIDR, ARES + jump_if_cpu_midr NEOVERSE_N1_MIDR, N1 ret /* ----------------------------------------------------- @@ -73,10 +73,10 @@ isb ret -ARES: - mrs x0, CORTEX_ARES_CPUPWRCTLR_EL1 - bic x0, x0, #CORTEX_ARES_CORE_PWRDN_EN_MASK - msr CORTEX_ARES_CPUPWRCTLR_EL1, x0 +N1: + mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 + bic x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK + msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 isb ret endfunc plat_reset_handler diff --git a/readme.rst b/readme.rst index 5404e74..deca2d2 100644 --- a/readme.rst +++ b/readme.rst @@ -195,7 +195,7 @@ - Allwinner sun50i_64 and sun50i_h6 - Amlogic Meson S905 (GXBB) - Arm SGI-575, SGI Clark.A, SGI Clark.H and SGM-775 -- Arm NeoVerse N1 System Development Platform +- Arm Neoverse N1 System Development Platform - HiKey, HiKey960 and Poplar boards - Marvell Armada 3700 and 8K - MediaTek MT6795 and MT8173 SoCs