diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h index e0bf2db..9a6a7fa 100644 --- a/include/bl31/interrupt_mgmt.h +++ b/include/bl31/interrupt_mgmt.h @@ -12,16 +12,16 @@ /******************************************************************************* * Constants for the types of interrupts recognised by the IM framework ******************************************************************************/ -#define INTR_TYPE_S_EL1 0 -#define INTR_TYPE_EL3 1 -#define INTR_TYPE_NS 2 -#define MAX_INTR_TYPES 3 +#define INTR_TYPE_S_EL1 U(0) +#define INTR_TYPE_EL3 U(1) +#define INTR_TYPE_NS U(2) +#define MAX_INTR_TYPES U(3) #define INTR_TYPE_INVAL MAX_INTR_TYPES /* * Constant passed to the interrupt handler in the 'id' field when the * framework does not read the gic registers to determine the interrupt id. */ -#define INTR_ID_UNAVAILABLE 0xFFFFFFFF +#define INTR_ID_UNAVAILABLE U(0xFFFFFFFF) /******************************************************************************* @@ -29,37 +29,37 @@ * constants to define the valid routing models for each supported interrupt * type ******************************************************************************/ -#define INTR_RM_FLAGS_SHIFT 0x0 -#define INTR_RM_FLAGS_MASK 0x3 +#define INTR_RM_FLAGS_SHIFT U(0x0) +#define INTR_RM_FLAGS_MASK U(0x3) /* Routed to EL3 from NS. Taken to S-EL1 from Secure */ -#define INTR_SEL1_VALID_RM0 0x2 +#define INTR_SEL1_VALID_RM0 U(0x2) /* Routed to EL3 from NS and Secure */ -#define INTR_SEL1_VALID_RM1 0x3 +#define INTR_SEL1_VALID_RM1 U(0x3) /* Routed to EL1/EL2 from NS and to S-EL1 from Secure */ -#define INTR_NS_VALID_RM0 0x0 +#define INTR_NS_VALID_RM0 U(0x0) /* Routed to EL1/EL2 from NS and to EL3 from Secure */ -#define INTR_NS_VALID_RM1 0x1 +#define INTR_NS_VALID_RM1 U(0x1) /* Routed to EL3 from NS. Taken to S-EL1 from Secure and handed over to EL3 */ -#define INTR_EL3_VALID_RM0 0x2 +#define INTR_EL3_VALID_RM0 U(0x2) /* Routed to EL3 from NS and Secure */ -#define INTR_EL3_VALID_RM1 0x3 +#define INTR_EL3_VALID_RM1 U(0x3) /* This is the default routing model */ -#define INTR_DEFAULT_RM 0x0 +#define INTR_DEFAULT_RM U(0x0) /******************************************************************************* * Constants for the _individual_ routing model bits in the 'flags' field for * each interrupt type and mask to validate the 'flags' parameter while * registering an interrupt handler ******************************************************************************/ -#define INTR_TYPE_FLAGS_MASK 0xFFFFFFFC +#define INTR_TYPE_FLAGS_MASK U(0xFFFFFFFC) #define INTR_RM_FROM_SEC_SHIFT SECURE /* BIT[0] */ #define INTR_RM_FROM_NS_SHIFT NON_SECURE /* BIT[1] */ -#define INTR_RM_FROM_FLAG_MASK 1 +#define INTR_RM_FROM_FLAG_MASK U(1) #define get_interrupt_rm_flag(flag, ss) (((flag >> INTR_RM_FLAGS_SHIFT) >> ss) \ & INTR_RM_FROM_FLAG_MASK) -#define set_interrupt_rm_flag(flag, ss) (flag |= 1 << ss) -#define clr_interrupt_rm_flag(flag, ss) (flag &= ~(1 << ss)) +#define set_interrupt_rm_flag(flag, ss) (flag |= U(1) << ss) +#define clr_interrupt_rm_flag(flag, ss) (flag &= ~(U(1) << ss)) /******************************************************************************* @@ -84,10 +84,10 @@ * the flag to indicate the security state when the exception was generated is * supported. ******************************************************************************/ -#define INTR_SRC_SS_FLAG_SHIFT 0 /* BIT[0] */ -#define INTR_SRC_SS_FLAG_MASK 1 +#define INTR_SRC_SS_FLAG_SHIFT U(0) /* BIT[0] */ +#define INTR_SRC_SS_FLAG_MASK U(1) #define set_interrupt_src_ss(flag, val) (flag |= val << INTR_SRC_SS_FLAG_SHIFT) -#define clr_interrupt_src_ss(flag) (flag &= ~(1 << INTR_SRC_SS_FLAG_SHIFT)) +#define clr_interrupt_src_ss(flag) (flag &= ~(U(1) << INTR_SRC_SS_FLAG_SHIFT)) #define get_interrupt_src_ss(flag) ((flag >> INTR_SRC_SS_FLAG_SHIFT) & \ INTR_SRC_SS_FLAG_MASK) diff --git a/include/common/ep_info.h b/include/common/ep_info.h index 7f54523..23d27c4 100644 --- a/include/common/ep_info.h +++ b/include/common/ep_info.h @@ -8,49 +8,50 @@ #define __EP_INFO_H__ #include +#include -#define SECURE 0x0 -#define NON_SECURE 0x1 +#define SECURE U(0x0) +#define NON_SECURE U(0x1) #define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE)) /******************************************************************************* * Constants that allow assembler code to access members of and the * 'entry_point_info' structure at their correct offsets. ******************************************************************************/ -#define ENTRY_POINT_INFO_PC_OFFSET 0x08 +#define ENTRY_POINT_INFO_PC_OFFSET U(0x08) #ifdef AARCH32 -#define ENTRY_POINT_INFO_ARGS_OFFSET 0x10 +#define ENTRY_POINT_INFO_ARGS_OFFSET U(0x10) #else -#define ENTRY_POINT_INFO_ARGS_OFFSET 0x18 +#define ENTRY_POINT_INFO_ARGS_OFFSET U(0x18) #endif /* The following are used to set/get image attributes. */ -#define PARAM_EP_SECURITY_MASK (0x1) +#define PARAM_EP_SECURITY_MASK U(0x1) #define GET_SECURITY_STATE(x) (x & PARAM_EP_SECURITY_MASK) #define SET_SECURITY_STATE(x, security) \ ((x) = ((x) & ~PARAM_EP_SECURITY_MASK) | (security)) -#define EP_EE_MASK 0x2 -#define EP_EE_LITTLE 0x0 -#define EP_EE_BIG 0x2 +#define EP_EE_MASK U(0x2) +#define EP_EE_LITTLE U(0x0) +#define EP_EE_BIG U(0x2) #define EP_GET_EE(x) (x & EP_EE_MASK) #define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee)) -#define EP_ST_MASK 0x4 -#define EP_ST_DISABLE 0x0 -#define EP_ST_ENABLE 0x4 +#define EP_ST_MASK U(0x4) +#define EP_ST_DISABLE U(0x0) +#define EP_ST_ENABLE U(0x4) #define EP_GET_ST(x) (x & EP_ST_MASK) #define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee)) -#define EP_EXE_MASK 0x8 -#define NON_EXECUTABLE 0x0 -#define EXECUTABLE 0x8 +#define EP_EXE_MASK U(0x8) +#define NON_EXECUTABLE U(0x0) +#define EXECUTABLE U(0x8) #define EP_GET_EXE(x) (x & EP_EXE_MASK) #define EP_SET_EXE(x, ee) ((x) = ((x) & ~EP_EXE_MASK) | (ee)) -#define EP_FIRST_EXE_MASK 0x10 -#define EP_FIRST_EXE 0x10 +#define EP_FIRST_EXE_MASK U(0x10) +#define EP_FIRST_EXE U(0x10) #define EP_GET_FIRST_EXE(x) ((x) & EP_FIRST_EXE_MASK) #define EP_SET_FIRST_EXE(x, ee) ((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee)) diff --git a/include/drivers/arm/gic_v2.h b/include/drivers/arm/gic_v2.h index 7959bb7..3a3d7aa 100644 --- a/include/drivers/arm/gic_v2.h +++ b/include/drivers/arm/gic_v2.h @@ -15,115 +15,115 @@ #error " The legacy ARM GIC driver is deprecated." #endif -#define GIC400_NUM_SPIS 480 -#define MAX_PPIS 14 -#define MAX_SGIS 16 +#define GIC400_NUM_SPIS U(480) +#define MAX_PPIS U(14) +#define MAX_SGIS U(16) -#define MIN_SGI_ID 0 -#define MIN_PPI_ID 16 -#define MIN_SPI_ID 32 +#define MIN_SGI_ID U(0) +#define MIN_PPI_ID U(16) +#define MIN_SPI_ID U(32) -#define GRP0 0 -#define GRP1 1 -#define GIC_PRI_MASK 0xff -#define GIC_HIGHEST_SEC_PRIORITY 0 -#define GIC_LOWEST_SEC_PRIORITY 127 -#define GIC_HIGHEST_NS_PRIORITY 128 -#define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */ -#define GIC_SPURIOUS_INTERRUPT 1023 -#define GIC_TARGET_CPU_MASK 0xff +#define GRP0 U(0) +#define GRP1 U(1) +#define GIC_PRI_MASK U(0xff) +#define GIC_HIGHEST_SEC_PRIORITY U(0) +#define GIC_LOWEST_SEC_PRIORITY U(127) +#define GIC_HIGHEST_NS_PRIORITY U(128) +#define GIC_LOWEST_NS_PRIORITY U(254) /* 255 would disable an interrupt */ +#define GIC_SPURIOUS_INTERRUPT U(1023) +#define GIC_TARGET_CPU_MASK U(0xff) -#define ENABLE_GRP0 (1 << 0) -#define ENABLE_GRP1 (1 << 1) +#define ENABLE_GRP0 (U(1) << 0) +#define ENABLE_GRP1 (U(1) << 1) /* Distributor interface definitions */ -#define GICD_CTLR 0x0 -#define GICD_TYPER 0x4 -#define GICD_IGROUPR 0x80 -#define GICD_ISENABLER 0x100 -#define GICD_ICENABLER 0x180 -#define GICD_ISPENDR 0x200 -#define GICD_ICPENDR 0x280 -#define GICD_ISACTIVER 0x300 -#define GICD_ICACTIVER 0x380 -#define GICD_IPRIORITYR 0x400 -#define GICD_ITARGETSR 0x800 -#define GICD_ICFGR 0xC00 -#define GICD_SGIR 0xF00 -#define GICD_CPENDSGIR 0xF10 -#define GICD_SPENDSGIR 0xF20 +#define GICD_CTLR U(0x0) +#define GICD_TYPER U(0x4) +#define GICD_IGROUPR U(0x80) +#define GICD_ISENABLER U(0x100) +#define GICD_ICENABLER U(0x180) +#define GICD_ISPENDR U(0x200) +#define GICD_ICPENDR U(0x280) +#define GICD_ISACTIVER U(0x300) +#define GICD_ICACTIVER U(0x380) +#define GICD_IPRIORITYR U(0x400) +#define GICD_ITARGETSR U(0x800) +#define GICD_ICFGR U(0xC00) +#define GICD_SGIR U(0xF00) +#define GICD_CPENDSGIR U(0xF10) +#define GICD_SPENDSGIR U(0xF20) -#define IGROUPR_SHIFT 5 -#define ISENABLER_SHIFT 5 +#define IGROUPR_SHIFT U(5) +#define ISENABLER_SHIFT U(5) #define ICENABLER_SHIFT ISENABLER_SHIFT -#define ISPENDR_SHIFT 5 +#define ISPENDR_SHIFT U(5) #define ICPENDR_SHIFT ISPENDR_SHIFT -#define ISACTIVER_SHIFT 5 +#define ISACTIVER_SHIFT U(5) #define ICACTIVER_SHIFT ISACTIVER_SHIFT -#define IPRIORITYR_SHIFT 2 -#define ITARGETSR_SHIFT 2 -#define ICFGR_SHIFT 4 -#define CPENDSGIR_SHIFT 2 +#define IPRIORITYR_SHIFT U(2) +#define ITARGETSR_SHIFT U(2) +#define ICFGR_SHIFT U(4) +#define CPENDSGIR_SHIFT U(2) #define SPENDSGIR_SHIFT CPENDSGIR_SHIFT /* GICD_TYPER bit definitions */ -#define IT_LINES_NO_MASK 0x1f +#define IT_LINES_NO_MASK U(0x1f) /* Physical CPU Interface registers */ -#define GICC_CTLR 0x0 -#define GICC_PMR 0x4 -#define GICC_BPR 0x8 -#define GICC_IAR 0xC -#define GICC_EOIR 0x10 -#define GICC_RPR 0x14 -#define GICC_HPPIR 0x18 -#define GICC_AHPPIR 0x28 -#define GICC_IIDR 0xFC -#define GICC_DIR 0x1000 +#define GICC_CTLR U(0x0) +#define GICC_PMR U(0x4) +#define GICC_BPR U(0x8) +#define GICC_IAR U(0xC) +#define GICC_EOIR U(0x10) +#define GICC_RPR U(0x14) +#define GICC_HPPIR U(0x18) +#define GICC_AHPPIR U(0x28) +#define GICC_IIDR U(0xFC) +#define GICC_DIR U(0x1000) #define GICC_PRIODROP GICC_EOIR /* Common CPU Interface definitions */ -#define INT_ID_MASK 0x3ff +#define INT_ID_MASK U(0x3ff) /* GICC_CTLR bit definitions */ -#define EOI_MODE_NS (1 << 10) -#define EOI_MODE_S (1 << 9) -#define IRQ_BYP_DIS_GRP1 (1 << 8) -#define FIQ_BYP_DIS_GRP1 (1 << 7) -#define IRQ_BYP_DIS_GRP0 (1 << 6) -#define FIQ_BYP_DIS_GRP0 (1 << 5) -#define CBPR (1 << 4) -#define FIQ_EN (1 << 3) -#define ACK_CTL (1 << 2) +#define EOI_MODE_NS (U(1) << 10) +#define EOI_MODE_S (U(1) << 9) +#define IRQ_BYP_DIS_GRP1 (U(1) << 8) +#define FIQ_BYP_DIS_GRP1 (U(1) << 7) +#define IRQ_BYP_DIS_GRP0 (U(1) << 6) +#define FIQ_BYP_DIS_GRP0 (U(1) << 5) +#define CBPR (U(1) << 4) +#define FIQ_EN (U(1) << 3) +#define ACK_CTL (U(1) << 2) /* GICC_IIDR bit masks and shifts */ -#define GICC_IIDR_PID_SHIFT 20 -#define GICC_IIDR_ARCH_SHIFT 16 -#define GICC_IIDR_REV_SHIFT 12 -#define GICC_IIDR_IMP_SHIFT 0 +#define GICC_IIDR_PID_SHIFT U(20) +#define GICC_IIDR_ARCH_SHIFT U(16) +#define GICC_IIDR_REV_SHIFT U(12) +#define GICC_IIDR_IMP_SHIFT U(0) -#define GICC_IIDR_PID_MASK 0xfff -#define GICC_IIDR_ARCH_MASK 0xf -#define GICC_IIDR_REV_MASK 0xf -#define GICC_IIDR_IMP_MASK 0xfff +#define GICC_IIDR_PID_MASK U(0xfff) +#define GICC_IIDR_ARCH_MASK U(0xf) +#define GICC_IIDR_REV_MASK U(0xf) +#define GICC_IIDR_IMP_MASK U(0xfff) /* HYP view virtual CPU Interface registers */ -#define GICH_CTL 0x0 -#define GICH_VTR 0x4 -#define GICH_ELRSR0 0x30 -#define GICH_ELRSR1 0x34 -#define GICH_APR0 0xF0 -#define GICH_LR_BASE 0x100 +#define GICH_CTL U(0x0) +#define GICH_VTR U(0x4) +#define GICH_ELRSR0 U(0x30) +#define GICH_ELRSR1 U(0x34) +#define GICH_APR0 U(0xF0) +#define GICH_LR_BASE U(0x100) /* Virtual CPU Interface registers */ -#define GICV_CTL 0x0 -#define GICV_PRIMASK 0x4 -#define GICV_BP 0x8 -#define GICV_INTACK 0xC -#define GICV_EOI 0x10 -#define GICV_RUNNINGPRI 0x14 -#define GICV_HIGHESTPEND 0x18 -#define GICV_DEACTIVATE 0x1000 +#define GICV_CTL U(0x0) +#define GICV_PRIMASK U(0x4) +#define GICV_BP U(0x8) +#define GICV_INTACK U(0xC) +#define GICV_EOI U(0x10) +#define GICV_RUNNINGPRI U(0x14) +#define GICV_HIGHESTPEND U(0x18) +#define GICV_DEACTIVATE U(0x1000) #ifndef __ASSEMBLY__ diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 16adcf7..e84c888 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -12,35 +12,35 @@ /******************************************************************************* * MIDR bit definitions ******************************************************************************/ -#define MIDR_IMPL_MASK 0xff -#define MIDR_IMPL_SHIFT 0x18 -#define MIDR_VAR_SHIFT 20 -#define MIDR_VAR_BITS 4 -#define MIDR_VAR_MASK 0xf -#define MIDR_REV_SHIFT 0 -#define MIDR_REV_BITS 4 -#define MIDR_REV_MASK 0xf -#define MIDR_PN_MASK 0xfff -#define MIDR_PN_SHIFT 0x4 +#define MIDR_IMPL_MASK U(0xff) +#define MIDR_IMPL_SHIFT U(0x18) +#define MIDR_VAR_SHIFT U(20) +#define MIDR_VAR_BITS U(4) +#define MIDR_VAR_MASK U(0xf) +#define MIDR_REV_SHIFT U(0) +#define MIDR_REV_BITS U(4) +#define MIDR_REV_MASK U(0xf) +#define MIDR_PN_MASK U(0xfff) +#define MIDR_PN_SHIFT U(0x4) /******************************************************************************* * MPIDR macros ******************************************************************************/ -#define MPIDR_MT_MASK (1 << 24) +#define MPIDR_MT_MASK (U(1) << 24) #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK -#define MPIDR_CLUSTER_MASK MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS -#define MPIDR_AFFINITY_BITS 8 -#define MPIDR_AFFLVL_MASK 0xff -#define MPIDR_AFF0_SHIFT 0 -#define MPIDR_AFF1_SHIFT 8 -#define MPIDR_AFF2_SHIFT 16 -#define MPIDR_AFF3_SHIFT 32 -#define MPIDR_AFFINITY_MASK 0xff00ffffff -#define MPIDR_AFFLVL_SHIFT 3 -#define MPIDR_AFFLVL0 0 -#define MPIDR_AFFLVL1 1 -#define MPIDR_AFFLVL2 2 -#define MPIDR_AFFLVL3 3 +#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) +#define MPIDR_AFFINITY_BITS U(8) +#define MPIDR_AFFLVL_MASK U(0xff) +#define MPIDR_AFF0_SHIFT U(0) +#define MPIDR_AFF1_SHIFT U(8) +#define MPIDR_AFF2_SHIFT U(16) +#define MPIDR_AFF3_SHIFT U(32) +#define MPIDR_AFFINITY_MASK U(0xff00ffffff) +#define MPIDR_AFFLVL_SHIFT U(3) +#define MPIDR_AFFLVL0 U(0) +#define MPIDR_AFFLVL1 U(1) +#define MPIDR_AFFLVL2 U(2) +#define MPIDR_AFFLVL3 U(3) #define MPIDR_AFFLVL0_VAL(mpidr) \ ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) #define MPIDR_AFFLVL1_VAL(mpidr) \ @@ -54,10 +54,10 @@ * add one while using this macro to define array sizes. * TODO: Support only the first 3 affinity levels for now. */ -#define MPIDR_MAX_AFFLVL 2 +#define MPIDR_MAX_AFFLVL U(2) /* Constant to highlight the assumption that MPIDR allocation starts from 0 */ -#define FIRST_MPIDR 0 +#define FIRST_MPIDR U(0) /******************************************************************************* * Definitions for CPU system register interface to GICv3 @@ -80,164 +80,164 @@ /******************************************************************************* * Generic timer memory mapped registers & offsets ******************************************************************************/ -#define CNTCR_OFF 0x000 -#define CNTFID_OFF 0x020 +#define CNTCR_OFF U(0x000) +#define CNTFID_OFF U(0x020) -#define CNTCR_EN (1 << 0) -#define CNTCR_HDBG (1 << 1) +#define CNTCR_EN (U(1) << 0) +#define CNTCR_HDBG (U(1) << 1) #define CNTCR_FCREQ(x) ((x) << 8) /******************************************************************************* * System register bit definitions ******************************************************************************/ /* CLIDR definitions */ -#define LOUIS_SHIFT 21 -#define LOC_SHIFT 24 -#define CLIDR_FIELD_WIDTH 3 +#define LOUIS_SHIFT U(21) +#define LOC_SHIFT U(24) +#define CLIDR_FIELD_WIDTH U(3) /* CSSELR definitions */ -#define LEVEL_SHIFT 1 +#define LEVEL_SHIFT U(1) /* D$ set/way op type defines */ -#define DCISW 0x0 -#define DCCISW 0x1 -#define DCCSW 0x2 +#define DCISW U(0x0) +#define DCCISW U(0x1) +#define DCCSW U(0x2) /* ID_AA64PFR0_EL1 definitions */ -#define ID_AA64PFR0_EL0_SHIFT 0 -#define ID_AA64PFR0_EL1_SHIFT 4 -#define ID_AA64PFR0_EL2_SHIFT 8 -#define ID_AA64PFR0_EL3_SHIFT 12 -#define ID_AA64PFR0_ELX_MASK 0xf +#define ID_AA64PFR0_EL0_SHIFT U(0) +#define ID_AA64PFR0_EL1_SHIFT U(4) +#define ID_AA64PFR0_EL2_SHIFT U(8) +#define ID_AA64PFR0_EL3_SHIFT U(12) +#define ID_AA64PFR0_ELX_MASK U(0xf) -#define EL_IMPL_NONE 0 -#define EL_IMPL_A64ONLY 1 -#define EL_IMPL_A64_A32 2 +#define EL_IMPL_NONE U(0) +#define EL_IMPL_A64ONLY U(1) +#define EL_IMPL_A64_A32 U(2) -#define ID_AA64PFR0_GIC_SHIFT 24 -#define ID_AA64PFR0_GIC_WIDTH 4 -#define ID_AA64PFR0_GIC_MASK ((1 << ID_AA64PFR0_GIC_WIDTH) - 1) +#define ID_AA64PFR0_GIC_SHIFT U(24) +#define ID_AA64PFR0_GIC_WIDTH U(4) +#define ID_AA64PFR0_GIC_MASK ((U(1) << ID_AA64PFR0_GIC_WIDTH) - 1) /* ID_AA64MMFR0_EL1 definitions */ -#define ID_AA64MMFR0_EL1_PARANGE_MASK 0xf +#define ID_AA64MMFR0_EL1_PARANGE_MASK U(0xf) -#define PARANGE_0000 32 -#define PARANGE_0001 36 -#define PARANGE_0010 40 -#define PARANGE_0011 42 -#define PARANGE_0100 44 -#define PARANGE_0101 48 +#define PARANGE_0000 U(32) +#define PARANGE_0001 U(36) +#define PARANGE_0010 U(40) +#define PARANGE_0011 U(42) +#define PARANGE_0100 U(44) +#define PARANGE_0101 U(48) /* ID_PFR1_EL1 definitions */ -#define ID_PFR1_VIRTEXT_SHIFT 12 -#define ID_PFR1_VIRTEXT_MASK 0xf +#define ID_PFR1_VIRTEXT_SHIFT U(12) +#define ID_PFR1_VIRTEXT_MASK U(0xf) #define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \ & ID_PFR1_VIRTEXT_MASK) /* SCTLR definitions */ -#define SCTLR_EL2_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \ - (1 << 18) | (1 << 16) | (1 << 11) | (1 << 5) | \ - (1 << 4)) +#define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ + (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ + (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) -#define SCTLR_EL1_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \ - (1 << 20) | (1 << 11)) +#define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ + (U(1) << 22) | (U(1) << 20) | (U(1) << 11)) #define SCTLR_AARCH32_EL1_RES1 \ - ((1 << 23) | (1 << 22) | (1 << 11) | (1 << 4) | \ - (1 << 3)) + ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ + (U(1) << 4) | (U(1) << 3)) -#define SCTLR_M_BIT (1 << 0) -#define SCTLR_A_BIT (1 << 1) -#define SCTLR_C_BIT (1 << 2) -#define SCTLR_SA_BIT (1 << 3) -#define SCTLR_CP15BEN_BIT (1 << 5) -#define SCTLR_I_BIT (1 << 12) -#define SCTLR_NTWI_BIT (1 << 16) -#define SCTLR_NTWE_BIT (1 << 18) -#define SCTLR_WXN_BIT (1 << 19) -#define SCTLR_EE_BIT (1 << 25) +#define SCTLR_M_BIT (U(1) << 0) +#define SCTLR_A_BIT (U(1) << 1) +#define SCTLR_C_BIT (U(1) << 2) +#define SCTLR_SA_BIT (U(1) << 3) +#define SCTLR_CP15BEN_BIT (U(1) << 5) +#define SCTLR_I_BIT (U(1) << 12) +#define SCTLR_NTWI_BIT (U(1) << 16) +#define SCTLR_NTWE_BIT (U(1) << 18) +#define SCTLR_WXN_BIT (U(1) << 19) +#define SCTLR_EE_BIT (U(1) << 25) /* CPACR_El1 definitions */ -#define CPACR_EL1_FPEN(x) (x << 20) -#define CPACR_EL1_FP_TRAP_EL0 0x1 -#define CPACR_EL1_FP_TRAP_ALL 0x2 -#define CPACR_EL1_FP_TRAP_NONE 0x3 +#define CPACR_EL1_FPEN(x) ((x) << 20) +#define CPACR_EL1_FP_TRAP_EL0 U(0x1) +#define CPACR_EL1_FP_TRAP_ALL U(0x2) +#define CPACR_EL1_FP_TRAP_NONE U(0x3) /* SCR definitions */ -#define SCR_RES1_BITS ((1 << 4) | (1 << 5)) -#define SCR_TWE_BIT (1 << 13) -#define SCR_TWI_BIT (1 << 12) -#define SCR_ST_BIT (1 << 11) -#define SCR_RW_BIT (1 << 10) -#define SCR_SIF_BIT (1 << 9) -#define SCR_HCE_BIT (1 << 8) -#define SCR_SMD_BIT (1 << 7) -#define SCR_EA_BIT (1 << 3) -#define SCR_FIQ_BIT (1 << 2) -#define SCR_IRQ_BIT (1 << 1) -#define SCR_NS_BIT (1 << 0) -#define SCR_VALID_BIT_MASK 0x2f8f +#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) +#define SCR_TWE_BIT (U(1) << 13) +#define SCR_TWI_BIT (U(1) << 12) +#define SCR_ST_BIT (U(1) << 11) +#define SCR_RW_BIT (U(1) << 10) +#define SCR_SIF_BIT (U(1) << 9) +#define SCR_HCE_BIT (U(1) << 8) +#define SCR_SMD_BIT (U(1) << 7) +#define SCR_EA_BIT (U(1) << 3) +#define SCR_FIQ_BIT (U(1) << 2) +#define SCR_IRQ_BIT (U(1) << 1) +#define SCR_NS_BIT (U(1) << 0) +#define SCR_VALID_BIT_MASK U(0x2f8f) /* MDCR definitions */ #define MDCR_SPD32(x) ((x) << 14) -#define MDCR_SPD32_LEGACY 0x0 -#define MDCR_SPD32_DISABLE 0x2 -#define MDCR_SPD32_ENABLE 0x3 -#define MDCR_SDD_BIT (1 << 16) +#define MDCR_SPD32_LEGACY U(0x0) +#define MDCR_SPD32_DISABLE U(0x2) +#define MDCR_SPD32_ENABLE U(0x3) +#define MDCR_SDD_BIT (U(1) << 16) #define MDCR_DEF_VAL (MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) /* HCR definitions */ -#define HCR_RW_SHIFT 31 -#define HCR_RW_BIT (1ull << HCR_RW_SHIFT) -#define HCR_AMO_BIT (1 << 5) -#define HCR_IMO_BIT (1 << 4) -#define HCR_FMO_BIT (1 << 3) +#define HCR_RW_SHIFT U(31) +#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) +#define HCR_AMO_BIT (U(1) << 5) +#define HCR_IMO_BIT (U(1) << 4) +#define HCR_FMO_BIT (U(1) << 3) /* ISR definitions */ -#define ISR_A_SHIFT 8 -#define ISR_I_SHIFT 7 -#define ISR_F_SHIFT 6 +#define ISR_A_SHIFT U(8) +#define ISR_I_SHIFT U(7) +#define ISR_F_SHIFT U(6) /* CNTHCTL_EL2 definitions */ -#define EVNTEN_BIT (1 << 2) -#define EL1PCEN_BIT (1 << 1) -#define EL1PCTEN_BIT (1 << 0) +#define EVNTEN_BIT (U(1) << 2) +#define EL1PCEN_BIT (U(1) << 1) +#define EL1PCTEN_BIT (U(1) << 0) /* CNTKCTL_EL1 definitions */ -#define EL0PTEN_BIT (1 << 9) -#define EL0VTEN_BIT (1 << 8) -#define EL0PCTEN_BIT (1 << 0) -#define EL0VCTEN_BIT (1 << 1) -#define EVNTEN_BIT (1 << 2) -#define EVNTDIR_BIT (1 << 3) -#define EVNTI_SHIFT 4 -#define EVNTI_MASK 0xf +#define EL0PTEN_BIT (U(1) << 9) +#define EL0VTEN_BIT (U(1) << 8) +#define EL0PCTEN_BIT (U(1) << 0) +#define EL0VCTEN_BIT (U(1) << 1) +#define EVNTEN_BIT (U(1) << 2) +#define EVNTDIR_BIT (U(1) << 3) +#define EVNTI_SHIFT U(4) +#define EVNTI_MASK U(0xf) /* CPTR_EL3 definitions */ -#define TCPAC_BIT (1 << 31) -#define TTA_BIT (1 << 20) -#define TFP_BIT (1 << 10) +#define TCPAC_BIT (U(1) << 31) +#define TTA_BIT (U(1) << 20) +#define TFP_BIT (U(1) << 10) /* CPSR/SPSR definitions */ -#define DAIF_FIQ_BIT (1 << 0) -#define DAIF_IRQ_BIT (1 << 1) -#define DAIF_ABT_BIT (1 << 2) -#define DAIF_DBG_BIT (1 << 3) -#define SPSR_DAIF_SHIFT 6 -#define SPSR_DAIF_MASK 0xf +#define DAIF_FIQ_BIT (U(1) << 0) +#define DAIF_IRQ_BIT (U(1) << 1) +#define DAIF_ABT_BIT (U(1) << 2) +#define DAIF_DBG_BIT (U(1) << 3) +#define SPSR_DAIF_SHIFT U(6) +#define SPSR_DAIF_MASK U(0xf) -#define SPSR_AIF_SHIFT 6 -#define SPSR_AIF_MASK 0x7 +#define SPSR_AIF_SHIFT U(6) +#define SPSR_AIF_MASK U(0x7) -#define SPSR_E_SHIFT 9 -#define SPSR_E_MASK 0x1 -#define SPSR_E_LITTLE 0x0 -#define SPSR_E_BIG 0x1 +#define SPSR_E_SHIFT U(9) +#define SPSR_E_MASK U(0x1) +#define SPSR_E_LITTLE U(0x0) +#define SPSR_E_BIG U(0x1) -#define SPSR_T_SHIFT 5 -#define SPSR_T_MASK 0x1 -#define SPSR_T_ARM 0x0 -#define SPSR_T_THUMB 0x1 +#define SPSR_T_SHIFT U(5) +#define SPSR_T_MASK U(0x1) +#define SPSR_T_ARM U(0x0) +#define SPSR_T_THUMB U(0x1) #define DISABLE_ALL_EXCEPTIONS \ (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) @@ -245,81 +245,81 @@ /* * RMR_EL3 definitions */ -#define RMR_EL3_RR_BIT (1 << 1) -#define RMR_EL3_AA64_BIT (1 << 0) +#define RMR_EL3_RR_BIT (U(1) << 1) +#define RMR_EL3_AA64_BIT (U(1) << 0) /* * HI-VECTOR address for AArch32 state */ -#define HI_VECTOR_BASE (0xFFFF0000) +#define HI_VECTOR_BASE U(0xFFFF0000) /* * TCR defintions */ #define TCR_EL3_RES1 ((1UL << 31) | (1UL << 23)) -#define TCR_EL1_IPS_SHIFT 32 -#define TCR_EL3_PS_SHIFT 16 +#define TCR_EL1_IPS_SHIFT U(32) +#define TCR_EL3_PS_SHIFT U(16) -#define TCR_TxSZ_MIN 16 -#define TCR_TxSZ_MAX 39 +#define TCR_TxSZ_MIN U(16) +#define TCR_TxSZ_MAX U(39) /* (internal) physical address size bits in EL3/EL1 */ -#define TCR_PS_BITS_4GB (0x0) -#define TCR_PS_BITS_64GB (0x1) -#define TCR_PS_BITS_1TB (0x2) -#define TCR_PS_BITS_4TB (0x3) -#define TCR_PS_BITS_16TB (0x4) -#define TCR_PS_BITS_256TB (0x5) +#define TCR_PS_BITS_4GB U(0x0) +#define TCR_PS_BITS_64GB U(0x1) +#define TCR_PS_BITS_1TB U(0x2) +#define TCR_PS_BITS_4TB U(0x3) +#define TCR_PS_BITS_16TB U(0x4) +#define TCR_PS_BITS_256TB U(0x5) -#define ADDR_MASK_48_TO_63 0xFFFF000000000000UL -#define ADDR_MASK_44_TO_47 0x0000F00000000000UL -#define ADDR_MASK_42_TO_43 0x00000C0000000000UL -#define ADDR_MASK_40_TO_41 0x0000030000000000UL -#define ADDR_MASK_36_TO_39 0x000000F000000000UL -#define ADDR_MASK_32_TO_35 0x0000000F00000000UL +#define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) +#define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) +#define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) +#define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) +#define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) +#define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) -#define TCR_RGN_INNER_NC (0x0 << 8) -#define TCR_RGN_INNER_WBA (0x1 << 8) -#define TCR_RGN_INNER_WT (0x2 << 8) -#define TCR_RGN_INNER_WBNA (0x3 << 8) +#define TCR_RGN_INNER_NC (U(0x0) << 8) +#define TCR_RGN_INNER_WBA (U(0x1) << 8) +#define TCR_RGN_INNER_WT (U(0x2) << 8) +#define TCR_RGN_INNER_WBNA (U(0x3) << 8) -#define TCR_RGN_OUTER_NC (0x0 << 10) -#define TCR_RGN_OUTER_WBA (0x1 << 10) -#define TCR_RGN_OUTER_WT (0x2 << 10) -#define TCR_RGN_OUTER_WBNA (0x3 << 10) +#define TCR_RGN_OUTER_NC (U(0x0) << 10) +#define TCR_RGN_OUTER_WBA (U(0x1) << 10) +#define TCR_RGN_OUTER_WT (U(0x2) << 10) +#define TCR_RGN_OUTER_WBNA (U(0x3) << 10) -#define TCR_SH_NON_SHAREABLE (0x0 << 12) -#define TCR_SH_OUTER_SHAREABLE (0x2 << 12) -#define TCR_SH_INNER_SHAREABLE (0x3 << 12) +#define TCR_SH_NON_SHAREABLE (U(0x0) << 12) +#define TCR_SH_OUTER_SHAREABLE (U(0x2) << 12) +#define TCR_SH_INNER_SHAREABLE (U(0x3) << 12) -#define MODE_SP_SHIFT 0x0 -#define MODE_SP_MASK 0x1 -#define MODE_SP_EL0 0x0 -#define MODE_SP_ELX 0x1 +#define MODE_SP_SHIFT U(0x0) +#define MODE_SP_MASK U(0x1) +#define MODE_SP_EL0 U(0x0) +#define MODE_SP_ELX U(0x1) -#define MODE_RW_SHIFT 0x4 -#define MODE_RW_MASK 0x1 -#define MODE_RW_64 0x0 -#define MODE_RW_32 0x1 +#define MODE_RW_SHIFT U(0x4) +#define MODE_RW_MASK U(0x1) +#define MODE_RW_64 U(0x0) +#define MODE_RW_32 U(0x1) -#define MODE_EL_SHIFT 0x2 -#define MODE_EL_MASK 0x3 -#define MODE_EL3 0x3 -#define MODE_EL2 0x2 -#define MODE_EL1 0x1 -#define MODE_EL0 0x0 +#define MODE_EL_SHIFT U(0x2) +#define MODE_EL_MASK U(0x3) +#define MODE_EL3 U(0x3) +#define MODE_EL2 U(0x2) +#define MODE_EL1 U(0x1) +#define MODE_EL0 U(0x0) -#define MODE32_SHIFT 0 -#define MODE32_MASK 0xf -#define MODE32_usr 0x0 -#define MODE32_fiq 0x1 -#define MODE32_irq 0x2 -#define MODE32_svc 0x3 -#define MODE32_mon 0x6 -#define MODE32_abt 0x7 -#define MODE32_hyp 0xa -#define MODE32_und 0xb -#define MODE32_sys 0xf +#define MODE32_SHIFT U(0) +#define MODE32_MASK U(0xf) +#define MODE32_usr U(0x0) +#define MODE32_fiq U(0x1) +#define MODE32_irq U(0x2) +#define MODE32_svc U(0x3) +#define MODE32_mon U(0x6) +#define MODE32_abt U(0x7) +#define MODE32_hyp U(0xa) +#define MODE32_und U(0xb) +#define MODE32_sys U(0xf) #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) @@ -333,93 +333,93 @@ ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT) #define SPSR_MODE32(mode, isa, endian, aif) \ - (MODE_RW_32 << MODE_RW_SHIFT | \ - ((mode) & MODE32_MASK) << MODE32_SHIFT | \ - ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \ - ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \ - ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) + ((MODE_RW_32 << MODE_RW_SHIFT) | \ + (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ + (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ + (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ + (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) /* * CTR_EL0 definitions */ -#define CTR_CWG_SHIFT 24 -#define CTR_CWG_MASK 0xf -#define CTR_ERG_SHIFT 20 -#define CTR_ERG_MASK 0xf -#define CTR_DMINLINE_SHIFT 16 -#define CTR_DMINLINE_MASK 0xf -#define CTR_L1IP_SHIFT 14 -#define CTR_L1IP_MASK 0x3 -#define CTR_IMINLINE_SHIFT 0 -#define CTR_IMINLINE_MASK 0xf +#define CTR_CWG_SHIFT U(24) +#define CTR_CWG_MASK U(0xf) +#define CTR_ERG_SHIFT U(20) +#define CTR_ERG_MASK U(0xf) +#define CTR_DMINLINE_SHIFT U(16) +#define CTR_DMINLINE_MASK U(0xf) +#define CTR_L1IP_SHIFT U(14) +#define CTR_L1IP_MASK U(0x3) +#define CTR_IMINLINE_SHIFT U(0) +#define CTR_IMINLINE_MASK U(0xf) -#define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */ +#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ /* Physical timer control register bit fields shifts and masks */ -#define CNTP_CTL_ENABLE_SHIFT 0 -#define CNTP_CTL_IMASK_SHIFT 1 -#define CNTP_CTL_ISTATUS_SHIFT 2 +#define CNTP_CTL_ENABLE_SHIFT U(0) +#define CNTP_CTL_IMASK_SHIFT U(1) +#define CNTP_CTL_ISTATUS_SHIFT U(2) -#define CNTP_CTL_ENABLE_MASK 1 -#define CNTP_CTL_IMASK_MASK 1 -#define CNTP_CTL_ISTATUS_MASK 1 +#define CNTP_CTL_ENABLE_MASK U(1) +#define CNTP_CTL_IMASK_MASK U(1) +#define CNTP_CTL_ISTATUS_MASK U(1) -#define get_cntp_ctl_enable(x) ((x >> CNTP_CTL_ENABLE_SHIFT) & \ +#define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \ CNTP_CTL_ENABLE_MASK) -#define get_cntp_ctl_imask(x) ((x >> CNTP_CTL_IMASK_SHIFT) & \ +#define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \ CNTP_CTL_IMASK_MASK) -#define get_cntp_ctl_istatus(x) ((x >> CNTP_CTL_ISTATUS_SHIFT) & \ +#define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \ CNTP_CTL_ISTATUS_MASK) -#define set_cntp_ctl_enable(x) (x |= 1 << CNTP_CTL_ENABLE_SHIFT) -#define set_cntp_ctl_imask(x) (x |= 1 << CNTP_CTL_IMASK_SHIFT) +#define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT)) +#define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT)) -#define clr_cntp_ctl_enable(x) (x &= ~(1 << CNTP_CTL_ENABLE_SHIFT)) -#define clr_cntp_ctl_imask(x) (x &= ~(1 << CNTP_CTL_IMASK_SHIFT)) +#define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT)) +#define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT)) /* Exception Syndrome register bits and bobs */ -#define ESR_EC_SHIFT 26 -#define ESR_EC_MASK 0x3f -#define ESR_EC_LENGTH 6 -#define EC_UNKNOWN 0x0 -#define EC_WFE_WFI 0x1 -#define EC_AARCH32_CP15_MRC_MCR 0x3 -#define EC_AARCH32_CP15_MRRC_MCRR 0x4 -#define EC_AARCH32_CP14_MRC_MCR 0x5 -#define EC_AARCH32_CP14_LDC_STC 0x6 -#define EC_FP_SIMD 0x7 -#define EC_AARCH32_CP10_MRC 0x8 -#define EC_AARCH32_CP14_MRRC_MCRR 0xc -#define EC_ILLEGAL 0xe -#define EC_AARCH32_SVC 0x11 -#define EC_AARCH32_HVC 0x12 -#define EC_AARCH32_SMC 0x13 -#define EC_AARCH64_SVC 0x15 -#define EC_AARCH64_HVC 0x16 -#define EC_AARCH64_SMC 0x17 -#define EC_AARCH64_SYS 0x18 -#define EC_IABORT_LOWER_EL 0x20 -#define EC_IABORT_CUR_EL 0x21 -#define EC_PC_ALIGN 0x22 -#define EC_DABORT_LOWER_EL 0x24 -#define EC_DABORT_CUR_EL 0x25 -#define EC_SP_ALIGN 0x26 -#define EC_AARCH32_FP 0x28 -#define EC_AARCH64_FP 0x2c -#define EC_SERROR 0x2f +#define ESR_EC_SHIFT U(26) +#define ESR_EC_MASK U(0x3f) +#define ESR_EC_LENGTH U(6) +#define EC_UNKNOWN U(0x0) +#define EC_WFE_WFI U(0x1) +#define EC_AARCH32_CP15_MRC_MCR U(0x3) +#define EC_AARCH32_CP15_MRRC_MCRR U(0x4) +#define EC_AARCH32_CP14_MRC_MCR U(0x5) +#define EC_AARCH32_CP14_LDC_STC U(0x6) +#define EC_FP_SIMD U(0x7) +#define EC_AARCH32_CP10_MRC U(0x8) +#define EC_AARCH32_CP14_MRRC_MCRR U(0xc) +#define EC_ILLEGAL U(0xe) +#define EC_AARCH32_SVC U(0x11) +#define EC_AARCH32_HVC U(0x12) +#define EC_AARCH32_SMC U(0x13) +#define EC_AARCH64_SVC U(0x15) +#define EC_AARCH64_HVC U(0x16) +#define EC_AARCH64_SMC U(0x17) +#define EC_AARCH64_SYS U(0x18) +#define EC_IABORT_LOWER_EL U(0x20) +#define EC_IABORT_CUR_EL U(0x21) +#define EC_PC_ALIGN U(0x22) +#define EC_DABORT_LOWER_EL U(0x24) +#define EC_DABORT_CUR_EL U(0x25) +#define EC_SP_ALIGN U(0x26) +#define EC_AARCH32_FP U(0x28) +#define EC_AARCH64_FP U(0x2c) +#define EC_SERROR U(0x2f) -#define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK +#define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ -#define RMR_RESET_REQUEST_SHIFT 0x1u -#define RMR_WARM_RESET_CPU (1u << RMR_RESET_REQUEST_SHIFT) +#define RMR_RESET_REQUEST_SHIFT U(0x1) +#define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) /******************************************************************************* * Definitions of register offsets, fields and macros for CPU system * instructions. ******************************************************************************/ -#define TLBI_ADDR_SHIFT 12 +#define TLBI_ADDR_SHIFT U(12) #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) @@ -427,20 +427,20 @@ * Definitions of register offsets and fields in the CNTCTLBase Frame of the * system level implementation of the Generic Timer. ******************************************************************************/ -#define CNTNSAR 0x4 -#define CNTNSAR_NS_SHIFT(x) x +#define CNTNSAR U(0x4) +#define CNTNSAR_NS_SHIFT(x) (x) -#define CNTACR_BASE(x) (0x40 + (x << 2)) -#define CNTACR_RPCT_SHIFT 0x0 -#define CNTACR_RVCT_SHIFT 0x1 -#define CNTACR_RFRQ_SHIFT 0x2 -#define CNTACR_RVOFF_SHIFT 0x3 -#define CNTACR_RWVT_SHIFT 0x4 -#define CNTACR_RWPT_SHIFT 0x5 +#define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) +#define CNTACR_RPCT_SHIFT U(0x0) +#define CNTACR_RVCT_SHIFT U(0x1) +#define CNTACR_RFRQ_SHIFT U(0x2) +#define CNTACR_RVOFF_SHIFT U(0x3) +#define CNTACR_RWVT_SHIFT U(0x4) +#define CNTACR_RWPT_SHIFT U(0x5) /* PMCR_EL0 definitions */ -#define PMCR_EL0_N_SHIFT 11 -#define PMCR_EL0_N_MASK 0x1f +#define PMCR_EL0_N_SHIFT U(11) +#define PMCR_EL0_N_MASK U(0x1f) #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) #endif /* __ARCH_H__ */ diff --git a/include/lib/aarch64/smcc_helpers.h b/include/lib/aarch64/smcc_helpers.h index ea2f707..62294d0 100644 --- a/include/lib/aarch64/smcc_helpers.h +++ b/include/lib/aarch64/smcc_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,35 +17,35 @@ return (uint64_t) (_h); \ } #define SMC_RET1(_h, _x0) { \ - write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X0, (_x0)); \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X0), (_x0)); \ SMC_RET0(_h); \ } #define SMC_RET2(_h, _x0, _x1) { \ - write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X1, (_x1)); \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X1), (_x1)); \ SMC_RET1(_h, (_x0)); \ } #define SMC_RET3(_h, _x0, _x1, _x2) { \ - write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X2, (_x2)); \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X2), (_x2)); \ SMC_RET2(_h, (_x0), (_x1)); \ } #define SMC_RET4(_h, _x0, _x1, _x2, _x3) { \ - write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X3, (_x3)); \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X3), (_x3)); \ SMC_RET3(_h, (_x0), (_x1), (_x2)); \ } #define SMC_RET5(_h, _x0, _x1, _x2, _x3, _x4) { \ - write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X4, (_x4)); \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X4), (_x4)); \ SMC_RET4(_h, (_x0), (_x1), (_x2), (_x3)); \ } #define SMC_RET6(_h, _x0, _x1, _x2, _x3, _x4, _x5) { \ - write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X5, (_x5)); \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X5), (_x5)); \ SMC_RET5(_h, (_x0), (_x1), (_x2), (_x3), (_x4)); \ } #define SMC_RET7(_h, _x0, _x1, _x2, _x3, _x4, _x5, _x6) { \ - write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X6, (_x6)); \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X6), (_x6)); \ SMC_RET6(_h, (_x0), (_x1), (_x2), (_x3), (_x4), (_x5)); \ } #define SMC_RET8(_h, _x0, _x1, _x2, _x3, _x4, _x5, _x6, _x7) { \ - write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X7, (_x7)); \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X7), (_x7)); \ SMC_RET7(_h, (_x0), (_x1), (_x2), (_x3), (_x4), (_x5), (_x6)); \ } @@ -54,18 +54,18 @@ * to SMC handler. These take the offset values defined in context.h */ #define SMC_GET_GP(_h, _g) \ - read_ctx_reg(get_gpregs_ctx(_h), (_g)) + read_ctx_reg((get_gpregs_ctx(_h)), (_g)) #define SMC_SET_GP(_h, _g, _v) \ - write_ctx_reg(get_gpregs_ctx(_h), (_g), (_v)) + write_ctx_reg((get_gpregs_ctx(_h)), (_g), (_v)) /* * Convenience macros to access EL3 context registers using handle provided to * SMC handler. These take the offset values defined in context.h */ #define SMC_GET_EL3(_h, _e) \ - read_ctx_reg(get_el3state_ctx(_h), (_e)) + read_ctx_reg((get_el3state_ctx(_h)), (_e)) #define SMC_SET_EL3(_h, _e, _v) \ - write_ctx_reg(get_el3state_ctx(_h), (_e), (_v)) + write_ctx_reg((get_el3state_ctx(_h)), (_e), (_v)) /* Return a UUID in the SMC return registers */ #define SMC_UUID_RET(_h, _uuid) \ diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h index e87e969..6627dcf 100644 --- a/include/lib/cpus/aarch64/cortex_a53.h +++ b/include/lib/cpus/aarch64/cortex_a53.h @@ -8,29 +8,29 @@ #define __CORTEX_A53_H__ /* Cortex-A53 midr for revision 0 */ -#define CORTEX_A53_MIDR 0x410FD030 +#define CORTEX_A53_MIDR U(0x410FD030) /* Retention timer tick definitions */ -#define RETENTION_ENTRY_TICKS_2 0x1 -#define RETENTION_ENTRY_TICKS_8 0x2 -#define RETENTION_ENTRY_TICKS_32 0x3 -#define RETENTION_ENTRY_TICKS_64 0x4 -#define RETENTION_ENTRY_TICKS_128 0x5 -#define RETENTION_ENTRY_TICKS_256 0x6 -#define RETENTION_ENTRY_TICKS_512 0x7 +#define RETENTION_ENTRY_TICKS_2 U(0x1) +#define RETENTION_ENTRY_TICKS_8 U(0x2) +#define RETENTION_ENTRY_TICKS_32 U(0x3) +#define RETENTION_ENTRY_TICKS_64 U(0x4) +#define RETENTION_ENTRY_TICKS_128 U(0x5) +#define RETENTION_ENTRY_TICKS_256 U(0x6) +#define RETENTION_ENTRY_TICKS_512 U(0x7) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ #define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1 -#define CORTEX_A53_ECTLR_SMP_BIT (1 << 6) +#define CORTEX_A53_ECTLR_SMP_BIT (U(1) << 6) -#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT 0 -#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT) +#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0) +#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT) -#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT 3 -#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT) +#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3) +#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. @@ -42,30 +42,29 @@ ******************************************************************************/ #define CORTEX_A53_ACTLR_EL1 S3_1_C15_C2_0 -#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT 44 -#define CORTEX_A53_ACTLR_ENDCCASCI (1 << CORTEX_A53_ACTLR_ENDCCASCI_SHIFT) -#define CORTEX_A53_ACTLR_RADIS_SHIFT 27 -#define CORTEX_A53_ACTLR_RADIS (3 << CORTEX_A53_ACTLR_RADIS_SHIFT) -#define CORTEX_A53_ACTLR_L1RADIS_SHIFT 25 -#define CORTEX_A53_ACTLR_L1RADIS (3 << CORTEX_A53_ACTLR_L1RADIS_SHIFT) -#define CORTEX_A53_ACTLR_DTAH_SHIFT 24 -#define CORTEX_A53_ACTLR_DTAH (1 << CORTEX_A53_ACTLR_DTAH_SHIFT) +#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT U(44) +#define CORTEX_A53_ACTLR_ENDCCASCI (U(1) << CORTEX_A53_ACTLR_ENDCCASCI_SHIFT) +#define CORTEX_A53_ACTLR_RADIS_SHIFT U(27) +#define CORTEX_A53_ACTLR_RADIS (U(3) << CORTEX_A53_ACTLR_RADIS_SHIFT) +#define CORTEX_A53_ACTLR_L1RADIS_SHIFT U(25) +#define CORTEX_A53_ACTLR_L1RADIS (U(3) << CORTEX_A53_ACTLR_L1RADIS_SHIFT) +#define CORTEX_A53_ACTLR_DTAH_SHIFT U(24) +#define CORTEX_A53_ACTLR_DTAH (U(1) << CORTEX_A53_ACTLR_DTAH_SHIFT) /******************************************************************************* * L2 Auxiliary Control register specific definitions. ******************************************************************************/ #define CORTEX_A53_L2ACTLR_EL1 S3_1_C15_C0_0 -#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14) -#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3) - +#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14) +#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3) /******************************************************************************* * L2 Extended Control register specific definitions. ******************************************************************************/ #define CORTEX_A53_L2ECTLR_EL1 S3_1_C11_C0_3 -#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT 0 -#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) +#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0) +#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT) /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index 228a91b..20d11e1 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,29 +8,29 @@ #define __CORTEX_A57_H__ /* Cortex-A57 midr for revision 0 */ -#define CORTEX_A57_MIDR 0x410FD070 +#define CORTEX_A57_MIDR U(0x410FD070) /* Retention timer tick definitions */ -#define RETENTION_ENTRY_TICKS_2 0x1 -#define RETENTION_ENTRY_TICKS_8 0x2 -#define RETENTION_ENTRY_TICKS_32 0x3 -#define RETENTION_ENTRY_TICKS_64 0x4 -#define RETENTION_ENTRY_TICKS_128 0x5 -#define RETENTION_ENTRY_TICKS_256 0x6 -#define RETENTION_ENTRY_TICKS_512 0x7 +#define RETENTION_ENTRY_TICKS_2 U(0x1) +#define RETENTION_ENTRY_TICKS_8 U(0x2) +#define RETENTION_ENTRY_TICKS_32 U(0x3) +#define RETENTION_ENTRY_TICKS_64 U(0x4) +#define RETENTION_ENTRY_TICKS_128 U(0x5) +#define RETENTION_ENTRY_TICKS_256 U(0x6) +#define RETENTION_ENTRY_TICKS_512 U(0x7) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ #define CORTEX_A57_ECTLR_EL1 S3_1_C15_C2_1 -#define CORTEX_A57_ECTLR_SMP_BIT (1 << 6) -#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) -#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) -#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) +#define CORTEX_A57_ECTLR_SMP_BIT (U(1) << 6) +#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (U(1) << 38) +#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (U(0x3) << 35) +#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (U(0x3) << 32) -#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT 0 -#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) +#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0) +#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. @@ -42,36 +42,36 @@ ******************************************************************************/ #define CORTEX_A57_ACTLR_EL1 S3_1_C15_C2_0 -#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (1 << 59) -#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (1 << 54) -#define CORTEX_A57_ACTLR_DIS_OVERREAD (1 << 52) -#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (1 << 49) -#define CORTEX_A57_ACTLR_DCC_AS_DCCI (1 << 44) -#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (1 << 38) -#define CORTEX_A57_ACTLR_DIS_STREAMING (3 << 27) -#define CORTEX_A57_ACTLR_DIS_L1_STREAMING (3 << 25) -#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (1 << 4) +#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59) +#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54) +#define CORTEX_A57_ACTLR_DIS_OVERREAD (ULL(1) << 52) +#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (ULL(1) << 49) +#define CORTEX_A57_ACTLR_DCC_AS_DCCI (ULL(1) << 44) +#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38) +#define CORTEX_A57_ACTLR_DIS_STREAMING (ULL(3) << 27) +#define CORTEX_A57_ACTLR_DIS_L1_STREAMING (ULL(3) << 25) +#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) /******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ #define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2 -#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 -#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 +#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) +#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) -#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 -#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) +#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) -#define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (1 << 21) +#define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21) /******************************************************************************* * L2 Extended Control register specific definitions. ******************************************************************************/ #define CORTEX_A57_L2ECTLR_EL1 S3_1_C11_C0_3 -#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT 0 -#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (0x7 << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) +#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0) +#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h index d582d81..d8c4d2e 100644 --- a/include/lib/cpus/aarch64/denver.h +++ b/include/lib/cpus/aarch64/denver.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,17 +8,17 @@ #define __DENVER_H__ /* MIDR values for Denver */ -#define DENVER_MIDR_PN0 0x4E0F0000 -#define DENVER_MIDR_PN1 0x4E0F0010 -#define DENVER_MIDR_PN2 0x4E0F0020 -#define DENVER_MIDR_PN3 0x4E0F0030 -#define DENVER_MIDR_PN4 0x4E0F0040 +#define DENVER_MIDR_PN0 U(0x4E0F0000) +#define DENVER_MIDR_PN1 U(0x4E0F0010) +#define DENVER_MIDR_PN2 U(0x4E0F0020) +#define DENVER_MIDR_PN3 U(0x4E0F0030) +#define DENVER_MIDR_PN4 U(0x4E0F0040) /* Implementer code in the MIDR register */ -#define DENVER_IMPL 0x4E +#define DENVER_IMPL U(0x4E) /* CPU state ids - implementation defined */ -#define DENVER_CPU_STATE_POWER_DOWN 0x3 +#define DENVER_CPU_STATE_POWER_DOWN U(0x3) #ifndef __ASSEMBLY__ diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index a2ae897..dead971 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,40 +11,40 @@ * Constants that allow assembler code to access members of and the 'gp_regs' * structure at their correct offsets. ******************************************************************************/ -#define CTX_GPREGS_OFFSET 0x0 -#define CTX_GPREG_X0 0x0 -#define CTX_GPREG_X1 0x8 -#define CTX_GPREG_X2 0x10 -#define CTX_GPREG_X3 0x18 -#define CTX_GPREG_X4 0x20 -#define CTX_GPREG_X5 0x28 -#define CTX_GPREG_X6 0x30 -#define CTX_GPREG_X7 0x38 -#define CTX_GPREG_X8 0x40 -#define CTX_GPREG_X9 0x48 -#define CTX_GPREG_X10 0x50 -#define CTX_GPREG_X11 0x58 -#define CTX_GPREG_X12 0x60 -#define CTX_GPREG_X13 0x68 -#define CTX_GPREG_X14 0x70 -#define CTX_GPREG_X15 0x78 -#define CTX_GPREG_X16 0x80 -#define CTX_GPREG_X17 0x88 -#define CTX_GPREG_X18 0x90 -#define CTX_GPREG_X19 0x98 -#define CTX_GPREG_X20 0xa0 -#define CTX_GPREG_X21 0xa8 -#define CTX_GPREG_X22 0xb0 -#define CTX_GPREG_X23 0xb8 -#define CTX_GPREG_X24 0xc0 -#define CTX_GPREG_X25 0xc8 -#define CTX_GPREG_X26 0xd0 -#define CTX_GPREG_X27 0xd8 -#define CTX_GPREG_X28 0xe0 -#define CTX_GPREG_X29 0xe8 -#define CTX_GPREG_LR 0xf0 -#define CTX_GPREG_SP_EL0 0xf8 -#define CTX_GPREGS_END 0x100 +#define CTX_GPREGS_OFFSET U(0x0) +#define CTX_GPREG_X0 U(0x0) +#define CTX_GPREG_X1 U(0x8) +#define CTX_GPREG_X2 U(0x10) +#define CTX_GPREG_X3 U(0x18) +#define CTX_GPREG_X4 U(0x20) +#define CTX_GPREG_X5 U(0x28) +#define CTX_GPREG_X6 U(0x30) +#define CTX_GPREG_X7 U(0x38) +#define CTX_GPREG_X8 U(0x40) +#define CTX_GPREG_X9 U(0x48) +#define CTX_GPREG_X10 U(0x50) +#define CTX_GPREG_X11 U(0x58) +#define CTX_GPREG_X12 U(0x60) +#define CTX_GPREG_X13 U(0x68) +#define CTX_GPREG_X14 U(0x70) +#define CTX_GPREG_X15 U(0x78) +#define CTX_GPREG_X16 U(0x80) +#define CTX_GPREG_X17 U(0x88) +#define CTX_GPREG_X18 U(0x90) +#define CTX_GPREG_X19 U(0x98) +#define CTX_GPREG_X20 U(0xa0) +#define CTX_GPREG_X21 U(0xa8) +#define CTX_GPREG_X22 U(0xb0) +#define CTX_GPREG_X23 U(0xb8) +#define CTX_GPREG_X24 U(0xc0) +#define CTX_GPREG_X25 U(0xc8) +#define CTX_GPREG_X26 U(0xd0) +#define CTX_GPREG_X27 U(0xd8) +#define CTX_GPREG_X28 U(0xe0) +#define CTX_GPREG_X29 U(0xe8) +#define CTX_GPREG_LR U(0xf0) +#define CTX_GPREG_SP_EL0 U(0xf8) +#define CTX_GPREGS_END U(0x100) /******************************************************************************* * Constants that allow assembler code to access members of and the 'el3_state' @@ -52,11 +52,11 @@ * 32-bits wide but are stored as 64-bit values for convenience ******************************************************************************/ #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) -#define CTX_SCR_EL3 0x0 -#define CTX_RUNTIME_SP 0x8 -#define CTX_SPSR_EL3 0x10 -#define CTX_ELR_EL3 0x18 -#define CTX_EL3STATE_END 0x20 +#define CTX_SCR_EL3 U(0x0) +#define CTX_RUNTIME_SP U(0x8) +#define CTX_SPSR_EL3 U(0x10) +#define CTX_ELR_EL3 U(0x18) +#define CTX_EL3STATE_END U(0x20) /******************************************************************************* * Constants that allow assembler code to access members of and the @@ -65,44 +65,44 @@ * convenience ******************************************************************************/ #define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) -#define CTX_SPSR_EL1 0x0 -#define CTX_ELR_EL1 0x8 -#define CTX_SCTLR_EL1 0x10 -#define CTX_ACTLR_EL1 0x18 -#define CTX_CPACR_EL1 0x20 -#define CTX_CSSELR_EL1 0x28 -#define CTX_SP_EL1 0x30 -#define CTX_ESR_EL1 0x38 -#define CTX_TTBR0_EL1 0x40 -#define CTX_TTBR1_EL1 0x48 -#define CTX_MAIR_EL1 0x50 -#define CTX_AMAIR_EL1 0x58 -#define CTX_TCR_EL1 0x60 -#define CTX_TPIDR_EL1 0x68 -#define CTX_TPIDR_EL0 0x70 -#define CTX_TPIDRRO_EL0 0x78 -#define CTX_PAR_EL1 0x80 -#define CTX_FAR_EL1 0x88 -#define CTX_AFSR0_EL1 0x90 -#define CTX_AFSR1_EL1 0x98 -#define CTX_CONTEXTIDR_EL1 0xa0 -#define CTX_VBAR_EL1 0xa8 +#define CTX_SPSR_EL1 U(0x0) +#define CTX_ELR_EL1 U(0x8) +#define CTX_SCTLR_EL1 U(0x10) +#define CTX_ACTLR_EL1 U(0x18) +#define CTX_CPACR_EL1 U(0x20) +#define CTX_CSSELR_EL1 U(0x28) +#define CTX_SP_EL1 U(0x30) +#define CTX_ESR_EL1 U(0x38) +#define CTX_TTBR0_EL1 U(0x40) +#define CTX_TTBR1_EL1 U(0x48) +#define CTX_MAIR_EL1 U(0x50) +#define CTX_AMAIR_EL1 U(0x58) +#define CTX_TCR_EL1 U(0x60) +#define CTX_TPIDR_EL1 U(0x68) +#define CTX_TPIDR_EL0 U(0x70) +#define CTX_TPIDRRO_EL0 U(0x78) +#define CTX_PAR_EL1 U(0x80) +#define CTX_FAR_EL1 U(0x88) +#define CTX_AFSR0_EL1 U(0x90) +#define CTX_AFSR1_EL1 U(0x98) +#define CTX_CONTEXTIDR_EL1 U(0xa0) +#define CTX_VBAR_EL1 U(0xa8) /* * If the platform is AArch64-only, there is no need to save and restore these * AArch32 registers. */ #if CTX_INCLUDE_AARCH32_REGS -#define CTX_SPSR_ABT 0xb0 -#define CTX_SPSR_UND 0xb8 -#define CTX_SPSR_IRQ 0xc0 -#define CTX_SPSR_FIQ 0xc8 -#define CTX_DACR32_EL2 0xd0 -#define CTX_IFSR32_EL2 0xd8 -#define CTX_FP_FPEXC32_EL2 0xe0 -#define CTX_TIMER_SYSREGS_OFF 0xf0 /* Align to the next 16 byte boundary */ +#define CTX_SPSR_ABT U(0xb0) +#define CTX_SPSR_UND U(0xb8) +#define CTX_SPSR_IRQ U(0xc0) +#define CTX_SPSR_FIQ U(0xc8) +#define CTX_DACR32_EL2 U(0xd0) +#define CTX_IFSR32_EL2 U(0xd8) +#define CTX_FP_FPEXC32_EL2 U(0xe0) +#define CTX_TIMER_SYSREGS_OFF U(0xf0) /* Align to the next 16 byte boundary */ #else -#define CTX_TIMER_SYSREGS_OFF 0xb0 +#define CTX_TIMER_SYSREGS_OFF U(0xb0) #endif /* __CTX_INCLUDE_AARCH32_REGS__ */ /* @@ -110,12 +110,12 @@ * space for them in the context */ #if NS_TIMER_SWITCH -#define CTX_CNTP_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + 0x0) -#define CTX_CNTP_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + 0x8) -#define CTX_CNTV_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + 0x10) -#define CTX_CNTV_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + 0x18) -#define CTX_CNTKCTL_EL1 (CTX_TIMER_SYSREGS_OFF + 0x20) -#define CTX_SYSREGS_END (CTX_TIMER_SYSREGS_OFF + 0x30) /* Align to the next 16 byte boundary */ +#define CTX_CNTP_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x0)) +#define CTX_CNTP_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x8)) +#define CTX_CNTV_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x10)) +#define CTX_CNTV_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x18)) +#define CTX_CNTKCTL_EL1 (CTX_TIMER_SYSREGS_OFF + U(0x20)) +#define CTX_SYSREGS_END (CTX_TIMER_SYSREGS_OFF + U(0x30)) /* Align to the next 16 byte boundary */ #else #define CTX_SYSREGS_END CTX_TIMER_SYSREGS_OFF #endif /* __NS_TIMER_SWITCH__ */ @@ -126,41 +126,41 @@ ******************************************************************************/ #if CTX_INCLUDE_FPREGS #define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END) -#define CTX_FP_Q0 0x0 -#define CTX_FP_Q1 0x10 -#define CTX_FP_Q2 0x20 -#define CTX_FP_Q3 0x30 -#define CTX_FP_Q4 0x40 -#define CTX_FP_Q5 0x50 -#define CTX_FP_Q6 0x60 -#define CTX_FP_Q7 0x70 -#define CTX_FP_Q8 0x80 -#define CTX_FP_Q9 0x90 -#define CTX_FP_Q10 0xa0 -#define CTX_FP_Q11 0xb0 -#define CTX_FP_Q12 0xc0 -#define CTX_FP_Q13 0xd0 -#define CTX_FP_Q14 0xe0 -#define CTX_FP_Q15 0xf0 -#define CTX_FP_Q16 0x100 -#define CTX_FP_Q17 0x110 -#define CTX_FP_Q18 0x120 -#define CTX_FP_Q19 0x130 -#define CTX_FP_Q20 0x140 -#define CTX_FP_Q21 0x150 -#define CTX_FP_Q22 0x160 -#define CTX_FP_Q23 0x170 -#define CTX_FP_Q24 0x180 -#define CTX_FP_Q25 0x190 -#define CTX_FP_Q26 0x1a0 -#define CTX_FP_Q27 0x1b0 -#define CTX_FP_Q28 0x1c0 -#define CTX_FP_Q29 0x1d0 -#define CTX_FP_Q30 0x1e0 -#define CTX_FP_Q31 0x1f0 -#define CTX_FP_FPSR 0x200 -#define CTX_FP_FPCR 0x208 -#define CTX_FPREGS_END 0x210 +#define CTX_FP_Q0 U(0x0) +#define CTX_FP_Q1 U(0x10) +#define CTX_FP_Q2 U(0x20) +#define CTX_FP_Q3 U(0x30) +#define CTX_FP_Q4 U(0x40) +#define CTX_FP_Q5 U(0x50) +#define CTX_FP_Q6 U(0x60) +#define CTX_FP_Q7 U(0x70) +#define CTX_FP_Q8 U(0x80) +#define CTX_FP_Q9 U(0x90) +#define CTX_FP_Q10 U(0xa0) +#define CTX_FP_Q11 U(0xb0) +#define CTX_FP_Q12 U(0xc0) +#define CTX_FP_Q13 U(0xd0) +#define CTX_FP_Q14 U(0xe0) +#define CTX_FP_Q15 U(0xf0) +#define CTX_FP_Q16 U(0x100) +#define CTX_FP_Q17 U(0x110) +#define CTX_FP_Q18 U(0x120) +#define CTX_FP_Q19 U(0x130) +#define CTX_FP_Q20 U(0x140) +#define CTX_FP_Q21 U(0x150) +#define CTX_FP_Q22 U(0x160) +#define CTX_FP_Q23 U(0x170) +#define CTX_FP_Q24 U(0x180) +#define CTX_FP_Q25 U(0x190) +#define CTX_FP_Q26 U(0x1a0) +#define CTX_FP_Q27 U(0x1b0) +#define CTX_FP_Q28 U(0x1c0) +#define CTX_FP_Q29 U(0x1d0) +#define CTX_FP_Q30 U(0x1e0) +#define CTX_FP_Q31 U(0x1f0) +#define CTX_FP_FPSR U(0x200) +#define CTX_FP_FPCR U(0x208) +#define CTX_FPREGS_END U(0x210) #endif #ifndef __ASSEMBLY__ @@ -173,7 +173,7 @@ * Common constants to help define the 'cpu_context' structure and its * members below. */ -#define DWORD_SHIFT 3 +#define DWORD_SHIFT U(3) #define DEFINE_REG_STRUCT(name, num_regs) \ typedef struct name { \ uint64_t _regs[num_regs]; \ diff --git a/include/lib/psci/psci.h b/include/lib/psci/psci.h index b23ed94..fee6a24 100644 --- a/include/lib/psci/psci.h +++ b/include/lib/psci/psci.h @@ -14,6 +14,7 @@ #include #endif #include /* To maintain compatibility for SPDs */ +#include /******************************************************************************* * Number of power domains whose state this PSCI implementation can track @@ -21,90 +22,90 @@ #ifdef PLAT_NUM_PWR_DOMAINS #define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS #else -#define PSCI_NUM_PWR_DOMAINS (2 * PLATFORM_CORE_COUNT) +#define PSCI_NUM_PWR_DOMAINS (U(2) * PLATFORM_CORE_COUNT) #endif #define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \ PLATFORM_CORE_COUNT) /* This is the power level corresponding to a CPU */ -#define PSCI_CPU_PWR_LVL 0 +#define PSCI_CPU_PWR_LVL (0) /* * The maximum power level supported by PSCI. Since PSCI CPU_SUSPEND * uses the old power_state parameter format which has 2 bits to specify the * power level, this constant is defined to be 3. */ -#define PSCI_MAX_PWR_LVL 3 +#define PSCI_MAX_PWR_LVL U(3) /******************************************************************************* * Defines for runtime services function ids ******************************************************************************/ -#define PSCI_VERSION 0x84000000 -#define PSCI_CPU_SUSPEND_AARCH32 0x84000001 -#define PSCI_CPU_SUSPEND_AARCH64 0xc4000001 -#define PSCI_CPU_OFF 0x84000002 -#define PSCI_CPU_ON_AARCH32 0x84000003 -#define PSCI_CPU_ON_AARCH64 0xc4000003 -#define PSCI_AFFINITY_INFO_AARCH32 0x84000004 -#define PSCI_AFFINITY_INFO_AARCH64 0xc4000004 -#define PSCI_MIG_AARCH32 0x84000005 -#define PSCI_MIG_AARCH64 0xc4000005 -#define PSCI_MIG_INFO_TYPE 0x84000006 -#define PSCI_MIG_INFO_UP_CPU_AARCH32 0x84000007 -#define PSCI_MIG_INFO_UP_CPU_AARCH64 0xc4000007 -#define PSCI_SYSTEM_OFF 0x84000008 -#define PSCI_SYSTEM_RESET 0x84000009 -#define PSCI_FEATURES 0x8400000A -#define PSCI_NODE_HW_STATE_AARCH32 0x8400000d -#define PSCI_NODE_HW_STATE_AARCH64 0xc400000d -#define PSCI_SYSTEM_SUSPEND_AARCH32 0x8400000E -#define PSCI_SYSTEM_SUSPEND_AARCH64 0xc400000E -#define PSCI_STAT_RESIDENCY_AARCH32 0x84000010 -#define PSCI_STAT_RESIDENCY_AARCH64 0xc4000010 -#define PSCI_STAT_COUNT_AARCH32 0x84000011 -#define PSCI_STAT_COUNT_AARCH64 0xc4000011 +#define PSCI_VERSION U(0x84000000) +#define PSCI_CPU_SUSPEND_AARCH32 U(0x84000001) +#define PSCI_CPU_SUSPEND_AARCH64 U(0xc4000001) +#define PSCI_CPU_OFF U(0x84000002) +#define PSCI_CPU_ON_AARCH32 U(0x84000003) +#define PSCI_CPU_ON_AARCH64 U(0xc4000003) +#define PSCI_AFFINITY_INFO_AARCH32 U(0x84000004) +#define PSCI_AFFINITY_INFO_AARCH64 U(0xc4000004) +#define PSCI_MIG_AARCH32 U(0x84000005) +#define PSCI_MIG_AARCH64 U(0xc4000005) +#define PSCI_MIG_INFO_TYPE U(0x84000006) +#define PSCI_MIG_INFO_UP_CPU_AARCH32 U(0x84000007) +#define PSCI_MIG_INFO_UP_CPU_AARCH64 U(0xc4000007) +#define PSCI_SYSTEM_OFF U(0x84000008) +#define PSCI_SYSTEM_RESET U(0x84000009) +#define PSCI_FEATURES U(0x8400000A) +#define PSCI_NODE_HW_STATE_AARCH32 U(0x8400000d) +#define PSCI_NODE_HW_STATE_AARCH64 U(0xc400000d) +#define PSCI_SYSTEM_SUSPEND_AARCH32 U(0x8400000E) +#define PSCI_SYSTEM_SUSPEND_AARCH64 U(0xc400000E) +#define PSCI_STAT_RESIDENCY_AARCH32 U(0x84000010) +#define PSCI_STAT_RESIDENCY_AARCH64 U(0xc4000010) +#define PSCI_STAT_COUNT_AARCH32 U(0x84000011) +#define PSCI_STAT_COUNT_AARCH64 U(0xc4000011) /* Macro to help build the psci capabilities bitfield */ -#define define_psci_cap(x) (1 << (x & 0x1f)) +#define define_psci_cap(x) (U(1) << (x & U(0x1f))) /* * Number of PSCI calls (above) implemented */ #if ENABLE_PSCI_STAT -#define PSCI_NUM_CALLS 22 +#define PSCI_NUM_CALLS U(22) #else -#define PSCI_NUM_CALLS 18 +#define PSCI_NUM_CALLS U(18) #endif /* The macros below are used to identify PSCI calls from the SMC function ID */ -#define PSCI_FID_MASK 0xffe0u -#define PSCI_FID_VALUE 0u +#define PSCI_FID_MASK U(0xffe0) +#define PSCI_FID_VALUE U(0) #define is_psci_fid(_fid) \ (((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE) /******************************************************************************* * PSCI Migrate and friends ******************************************************************************/ -#define PSCI_TOS_UP_MIG_CAP 0 -#define PSCI_TOS_NOT_UP_MIG_CAP 1 -#define PSCI_TOS_NOT_PRESENT_MP 2 +#define PSCI_TOS_UP_MIG_CAP U(0) +#define PSCI_TOS_NOT_UP_MIG_CAP U(1) +#define PSCI_TOS_NOT_PRESENT_MP U(2) /******************************************************************************* * PSCI CPU_SUSPEND 'power_state' parameter specific defines ******************************************************************************/ -#define PSTATE_ID_SHIFT 0 +#define PSTATE_ID_SHIFT U(0) #if PSCI_EXTENDED_STATE_ID -#define PSTATE_VALID_MASK 0xB0000000 -#define PSTATE_TYPE_SHIFT 30 -#define PSTATE_ID_MASK 0xfffffff +#define PSTATE_VALID_MASK U(0xB0000000) +#define PSTATE_TYPE_SHIFT U(30) +#define PSTATE_ID_MASK U(0xfffffff) #else -#define PSTATE_VALID_MASK 0xFCFE0000 -#define PSTATE_TYPE_SHIFT 16 -#define PSTATE_PWR_LVL_SHIFT 24 -#define PSTATE_ID_MASK 0xffff -#define PSTATE_PWR_LVL_MASK 0x3 +#define PSTATE_VALID_MASK U(0xFCFE0000) +#define PSTATE_TYPE_SHIFT U(16) +#define PSTATE_PWR_LVL_SHIFT U(24) +#define PSTATE_ID_MASK U(0xffff) +#define PSTATE_PWR_LVL_MASK U(0x3) #define psci_get_pstate_pwrlvl(pstate) (((pstate) >> PSTATE_PWR_LVL_SHIFT) & \ PSTATE_PWR_LVL_MASK) @@ -114,9 +115,9 @@ (((pwrlvl) & PSTATE_PWR_LVL_MASK) << PSTATE_PWR_LVL_SHIFT) #endif /* __PSCI_EXTENDED_STATE_ID__ */ -#define PSTATE_TYPE_STANDBY 0x0 -#define PSTATE_TYPE_POWERDOWN 0x1 -#define PSTATE_TYPE_MASK 0x1 +#define PSTATE_TYPE_STANDBY U(0x0) +#define PSTATE_TYPE_POWERDOWN U(0x1) +#define PSTATE_TYPE_MASK U(0x1) #define psci_get_pstate_id(pstate) (((pstate) >> PSTATE_ID_SHIFT) & \ PSTATE_ID_MASK) @@ -128,9 +129,9 @@ * PSCI CPU_FEATURES feature flag specific defines ******************************************************************************/ /* Features flags for CPU SUSPEND power state parameter format. Bits [1:1] */ -#define FF_PSTATE_SHIFT 1 -#define FF_PSTATE_ORIG 0 -#define FF_PSTATE_EXTENDED 1 +#define FF_PSTATE_SHIFT U(1) +#define FF_PSTATE_ORIG U(0) +#define FF_PSTATE_EXTENDED U(1) #if PSCI_EXTENDED_STATE_ID #define FF_PSTATE FF_PSTATE_EXTENDED #else @@ -138,14 +139,14 @@ #endif /* Features flags for CPU SUSPEND OS Initiated mode support. Bits [0:0] */ -#define FF_MODE_SUPPORT_SHIFT 0 -#define FF_SUPPORTS_OS_INIT_MODE 1 +#define FF_MODE_SUPPORT_SHIFT U(0) +#define FF_SUPPORTS_OS_INIT_MODE U(1) /******************************************************************************* * PSCI version ******************************************************************************/ -#define PSCI_MAJOR_VER (1 << 16) -#define PSCI_MINOR_VER 0x0 +#define PSCI_MAJOR_VER (U(1) << 16) +#define PSCI_MINOR_VER U(0x0) /******************************************************************************* * PSCI error codes @@ -174,9 +175,9 @@ * PSCI specification (ARM DEN 0022C). */ typedef enum { - AFF_STATE_ON = 0, - AFF_STATE_OFF = 1, - AFF_STATE_ON_PENDING = 2 + AFF_STATE_ON = U(0), + AFF_STATE_OFF = U(1), + AFF_STATE_ON_PENDING = U(2) } aff_info_state_t; /* @@ -185,15 +186,15 @@ * of PSCI specification (ARM DEN 0022C). */ typedef enum { - HW_ON = 0, - HW_OFF = 1, - HW_STANDBY = 2 + HW_ON = U(0), + HW_OFF = U(1), + HW_STANDBY = U(2) } node_hw_state_t; /* * Macro to represent invalid affinity level within PSCI. */ -#define PSCI_INVALID_PWR_LVL (PLAT_MAX_PWR_LVL + 1) +#define PSCI_INVALID_PWR_LVL (PLAT_MAX_PWR_LVL + U(1)) /* * Type for representing the local power state at a particular level. @@ -201,7 +202,7 @@ typedef uint8_t plat_local_state_t; /* The local state macro used to represent RUN state. */ -#define PSCI_LOCAL_STATE_RUN 0 +#define PSCI_LOCAL_STATE_RUN U(0) /* * Macro to test whether the plat_local_state is RUN state @@ -236,7 +237,7 @@ * The pwr_domain_state[] stores the local power state at each level * for the CPU. */ - plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + 1]; + plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + U(1)]; } psci_power_state_t; /******************************************************************************* diff --git a/include/lib/smcc.h b/include/lib/smcc.h index 7270a88..13b1e7a 100644 --- a/include/lib/smcc.h +++ b/include/lib/smcc.h @@ -12,55 +12,55 @@ /******************************************************************************* * Bit definitions inside the function id as per the SMC calling convention ******************************************************************************/ -#define FUNCID_TYPE_SHIFT 31 -#define FUNCID_CC_SHIFT 30 -#define FUNCID_OEN_SHIFT 24 -#define FUNCID_NUM_SHIFT 0 +#define FUNCID_TYPE_SHIFT U(31) +#define FUNCID_CC_SHIFT U(30) +#define FUNCID_OEN_SHIFT U(24) +#define FUNCID_NUM_SHIFT U(0) -#define FUNCID_TYPE_MASK 0x1 -#define FUNCID_CC_MASK 0x1 -#define FUNCID_OEN_MASK 0x3f -#define FUNCID_NUM_MASK 0xffff +#define FUNCID_TYPE_MASK U(0x1) +#define FUNCID_CC_MASK U(0x1) +#define FUNCID_OEN_MASK U(0x3f) +#define FUNCID_NUM_MASK U(0xffff) -#define FUNCID_TYPE_WIDTH 1 -#define FUNCID_CC_WIDTH 1 -#define FUNCID_OEN_WIDTH 6 -#define FUNCID_NUM_WIDTH 16 +#define FUNCID_TYPE_WIDTH U(1) +#define FUNCID_CC_WIDTH U(1) +#define FUNCID_OEN_WIDTH U(6) +#define FUNCID_NUM_WIDTH U(16) #define GET_SMC_CC(id) ((id >> FUNCID_CC_SHIFT) & \ FUNCID_CC_MASK) #define GET_SMC_TYPE(id) ((id >> FUNCID_TYPE_SHIFT) & \ FUNCID_TYPE_MASK) -#define SMC_64 1 -#define SMC_32 0 -#define SMC_OK 0 -#define SMC_UNK 0xffffffff +#define SMC_64 U(1) +#define SMC_32 U(0) +#define SMC_OK U(0) +#define SMC_UNK U(0xffffffff) #define SMC_TYPE_FAST ULL(1) #if !ERROR_DEPRECATED -#define SMC_TYPE_STD 0 +#define SMC_TYPE_STD ULL(0) #endif -#define SMC_TYPE_YIELD 0 -#define SMC_PREEMPTED 0xfffffffe +#define SMC_TYPE_YIELD U(0) +#define SMC_PREEMPTED U(0xfffffffe) /******************************************************************************* * Owning entity number definitions inside the function id as per the SMC * calling convention ******************************************************************************/ -#define OEN_ARM_START 0 -#define OEN_ARM_END 0 -#define OEN_CPU_START 1 -#define OEN_CPU_END 1 -#define OEN_SIP_START 2 -#define OEN_SIP_END 2 -#define OEN_OEM_START 3 -#define OEN_OEM_END 3 -#define OEN_STD_START 4 /* Standard Service Calls */ -#define OEN_STD_END 4 -#define OEN_TAP_START 48 /* Trusted Applications */ -#define OEN_TAP_END 49 -#define OEN_TOS_START 50 /* Trusted OS */ -#define OEN_TOS_END 63 -#define OEN_LIMIT 64 +#define OEN_ARM_START U(0) +#define OEN_ARM_END U(0) +#define OEN_CPU_START U(1) +#define OEN_CPU_END U(1) +#define OEN_SIP_START U(2) +#define OEN_SIP_END U(2) +#define OEN_OEM_START U(3) +#define OEN_OEM_END U(3) +#define OEN_STD_START U(4) /* Standard Service Calls */ +#define OEN_STD_END U(4) +#define OEN_TAP_START U(48) /* Trusted Applications */ +#define OEN_TAP_END U(49) +#define OEN_TOS_START U(50) /* Trusted OS */ +#define OEN_TOS_END U(63) +#define OEN_LIMIT U(64) #ifndef __ASSEMBLY__ @@ -68,8 +68,8 @@ #include /* Various flags passed to SMC handlers */ -#define SMC_FROM_SECURE (0 << 0) -#define SMC_FROM_NON_SECURE (1 << 0) +#define SMC_FROM_SECURE (U(0) << 0) +#define SMC_FROM_NON_SECURE (U(1) << 0) #define is_caller_non_secure(_f) (!!(_f & SMC_FROM_NON_SECURE)) #define is_caller_secure(_f) (!(is_caller_non_secure(_f))) @@ -79,7 +79,7 @@ FUNCID_OEN_MASK) == OEN_STD_START) /* The macro below is used to identify a valid Fast SMC call */ -#define is_valid_fast_smc(_fid) ((!(((_fid) >> 16) & 0xff)) && \ +#define is_valid_fast_smc(_fid) ((!(((_fid) >> 16) & U(0xff))) && \ (GET_SMC_TYPE(_fid) == SMC_TYPE_FAST)) /* diff --git a/include/lib/xlat_tables/xlat_tables.h b/include/lib/xlat_tables/xlat_tables.h index 66efa20..91f2f05 100644 --- a/include/lib/xlat_tables/xlat_tables.h +++ b/include/lib/xlat_tables/xlat_tables.h @@ -27,14 +27,14 @@ /* * Shifts and masks to access fields of an mmap_attr_t */ -#define MT_TYPE_MASK 0x7 +#define MT_TYPE_MASK U(0x7) #define MT_TYPE(_attr) ((_attr) & MT_TYPE_MASK) /* Access permissions (RO/RW) */ -#define MT_PERM_SHIFT 3 +#define MT_PERM_SHIFT U(3) /* Security state (SECURE/NS) */ -#define MT_SEC_SHIFT 4 +#define MT_SEC_SHIFT U(4) /* Access permissions for instruction execution (EXECUTE/EXECUTE_NEVER) */ -#define MT_EXECUTE_SHIFT 5 +#define MT_EXECUTE_SHIFT U(5) /* * Memory mapping attributes @@ -51,11 +51,11 @@ MT_MEMORY, /* Values up to 7 are reserved to add new memory types in the future */ - MT_RO = 0 << MT_PERM_SHIFT, - MT_RW = 1 << MT_PERM_SHIFT, + MT_RO = U(0) << MT_PERM_SHIFT, + MT_RW = U(1) << MT_PERM_SHIFT, - MT_SECURE = 0 << MT_SEC_SHIFT, - MT_NS = 1 << MT_SEC_SHIFT, + MT_SECURE = U(0) << MT_SEC_SHIFT, + MT_NS = U(1) << MT_SEC_SHIFT, /* * Access permissions for instruction execution are only relevant for @@ -64,8 +64,8 @@ * - Device memory is always marked as execute-never. * - Read-write normal memory is always marked as execute-never. */ - MT_EXECUTE = 0 << MT_EXECUTE_SHIFT, - MT_EXECUTE_NEVER = 1 << MT_EXECUTE_SHIFT, + MT_EXECUTE = U(0) << MT_EXECUTE_SHIFT, + MT_EXECUTE_NEVER = U(1) << MT_EXECUTE_SHIFT, } mmap_attr_t; #define MT_CODE (MT_MEMORY | MT_RO | MT_EXECUTE) diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h index c54b729..4b993a0 100644 --- a/include/lib/xlat_tables/xlat_tables_defs.h +++ b/include/lib/xlat_tables/xlat_tables_defs.h @@ -10,23 +10,23 @@ #include /* Miscellaneous MMU related constants */ -#define NUM_2MB_IN_GB (1 << 9) -#define NUM_4K_IN_2MB (1 << 9) -#define NUM_GB_IN_4GB (1 << 2) +#define NUM_2MB_IN_GB (U(1) << 9) +#define NUM_4K_IN_2MB (U(1) << 9) +#define NUM_GB_IN_4GB (U(1) << 2) -#define TWO_MB_SHIFT 21 -#define ONE_GB_SHIFT 30 -#define FOUR_KB_SHIFT 12 +#define TWO_MB_SHIFT U(21) +#define ONE_GB_SHIFT U(30) +#define FOUR_KB_SHIFT U(12) #define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT) #define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT) #define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT) -#define INVALID_DESC 0x0 -#define BLOCK_DESC 0x1 /* Table levels 0-2 */ -#define TABLE_DESC 0x3 /* Table levels 0-2 */ -#define PAGE_DESC 0x3 /* Table level 3 */ -#define DESC_MASK 0x3 +#define INVALID_DESC U(0x0) +#define BLOCK_DESC U(0x1) /* Table levels 0-2 */ +#define TABLE_DESC U(0x3) /* Table levels 0-2 */ +#define PAGE_DESC U(0x3) /* Table level 3 */ +#define DESC_MASK U(0x3) #define FIRST_LEVEL_DESC_N ONE_GB_SHIFT #define SECOND_LEVEL_DESC_N TWO_MB_SHIFT @@ -40,36 +40,36 @@ #define CONT_HINT (ULL(1) << 0) #define UPPER_ATTRS(x) (((x) & ULL(0x7)) << 52) -#define NON_GLOBAL (1 << 9) -#define ACCESS_FLAG (1 << 8) -#define NSH (0x0 << 6) -#define OSH (0x2 << 6) -#define ISH (0x3 << 6) +#define NON_GLOBAL (U(1) << 9) +#define ACCESS_FLAG (U(1) << 8) +#define NSH (U(0x0) << 6) +#define OSH (U(0x2) << 6) +#define ISH (U(0x3) << 6) #define TABLE_ADDR_MASK ULL(0x0000FFFFFFFFF000) #define PAGE_SIZE_SHIFT FOUR_KB_SHIFT /* 4, 16 or 64 KB */ -#define PAGE_SIZE (1 << PAGE_SIZE_SHIFT) +#define PAGE_SIZE (U(1) << PAGE_SIZE_SHIFT) #define PAGE_SIZE_MASK (PAGE_SIZE - 1) #define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0) -#define XLAT_ENTRY_SIZE_SHIFT 3 /* Each MMU table entry is 8 bytes (1 << 3) */ -#define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SIZE_SHIFT) +#define XLAT_ENTRY_SIZE_SHIFT U(3) /* Each MMU table entry is 8 bytes (1 << 3) */ +#define XLAT_ENTRY_SIZE (U(1) << XLAT_ENTRY_SIZE_SHIFT) #define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */ -#define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT) +#define XLAT_TABLE_SIZE (U(1) << XLAT_TABLE_SIZE_SHIFT) #ifdef AARCH32 -#define XLAT_TABLE_LEVEL_MIN 1 +#define XLAT_TABLE_LEVEL_MIN U(1) #else -#define XLAT_TABLE_LEVEL_MIN 0 +#define XLAT_TABLE_LEVEL_MIN U(0) #endif /* AARCH32 */ -#define XLAT_TABLE_LEVEL_MAX 3 +#define XLAT_TABLE_LEVEL_MAX U(3) /* Values for number of entries in each MMU translation table */ #define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT) -#define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT) +#define XLAT_TABLE_ENTRIES (U(1) << XLAT_TABLE_ENTRIES_SHIFT) #define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1) /* Values to convert a memory address to an index into a translation table */ @@ -90,34 +90,34 @@ * AP[1] bit is ignored by hardware and is * treated as if it is One in EL2/EL3 */ -#define AP_RO (0x1 << 5) -#define AP_RW (0x0 << 5) +#define AP_RO (U(0x1) << 5) +#define AP_RW (U(0x0) << 5) -#define NS (0x1 << 3) -#define ATTR_NON_CACHEABLE_INDEX 0x2 -#define ATTR_DEVICE_INDEX 0x1 -#define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0 -#define LOWER_ATTRS(x) (((x) & 0xfff) << 2) +#define NS (U(0x1) << 3) +#define ATTR_NON_CACHEABLE_INDEX U(0x2) +#define ATTR_DEVICE_INDEX U(0x1) +#define ATTR_IWBWA_OWBWA_NTR_INDEX U(0x0) +#define LOWER_ATTRS(x) (((x) & U(0xfff)) << 2) /* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */ -#define ATTR_NON_CACHEABLE (0x44) +#define ATTR_NON_CACHEABLE U(0x44) /* Device-nGnRE */ -#define ATTR_DEVICE (0x4) +#define ATTR_DEVICE U(0x4) /* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */ -#define ATTR_IWBWA_OWBWA_NTR (0xff) +#define ATTR_IWBWA_OWBWA_NTR U(0xff) #define MAIR_ATTR_SET(attr, index) ((attr) << ((index) << 3)) -#define ATTR_INDEX_MASK 0x3 +#define ATTR_INDEX_MASK U(0x3) #define ATTR_INDEX_GET(attr) (((attr) >> 2) & ATTR_INDEX_MASK) /* * Flags to override default values used to program system registers while * enabling the MMU. */ -#define DISABLE_DCACHE (1 << 0) +#define DISABLE_DCACHE (U(1) << 0) /* * This flag marks the translation tables are Non-cacheable for MMU accesses. * If the flag is not specified, by default the tables are cacheable. */ -#define XLAT_TABLE_NC (1 << 1) +#define XLAT_TABLE_NC (U(1) << 1) #endif /* __XLAT_TABLES_DEFS_H__ */ diff --git a/include/lib/xlat_tables/xlat_tables_v2.h b/include/lib/xlat_tables/xlat_tables_v2.h index e7ed233..9db6719 100644 --- a/include/lib/xlat_tables/xlat_tables_v2.h +++ b/include/lib/xlat_tables/xlat_tables_v2.h @@ -27,14 +27,14 @@ /* * Shifts and masks to access fields of an mmap_attr_t */ -#define MT_TYPE_MASK 0x7 +#define MT_TYPE_MASK U(0x7) #define MT_TYPE(_attr) ((_attr) & MT_TYPE_MASK) /* Access permissions (RO/RW) */ -#define MT_PERM_SHIFT 3 +#define MT_PERM_SHIFT U(3) /* Security state (SECURE/NS) */ -#define MT_SEC_SHIFT 4 +#define MT_SEC_SHIFT U(4) /* Access permissions for instruction execution (EXECUTE/EXECUTE_NEVER) */ -#define MT_EXECUTE_SHIFT 5 +#define MT_EXECUTE_SHIFT U(5) /* All other bits are reserved */ /* @@ -52,11 +52,11 @@ MT_MEMORY, /* Values up to 7 are reserved to add new memory types in the future */ - MT_RO = 0 << MT_PERM_SHIFT, - MT_RW = 1 << MT_PERM_SHIFT, + MT_RO = U(0) << MT_PERM_SHIFT, + MT_RW = U(1) << MT_PERM_SHIFT, - MT_SECURE = 0 << MT_SEC_SHIFT, - MT_NS = 1 << MT_SEC_SHIFT, + MT_SECURE = U(0) << MT_SEC_SHIFT, + MT_NS = U(1) << MT_SEC_SHIFT, /* * Access permissions for instruction execution are only relevant for @@ -65,8 +65,8 @@ * - Device memory is always marked as execute-never. * - Read-write normal memory is always marked as execute-never. */ - MT_EXECUTE = 0 << MT_EXECUTE_SHIFT, - MT_EXECUTE_NEVER = 1 << MT_EXECUTE_SHIFT, + MT_EXECUTE = U(0) << MT_EXECUTE_SHIFT, + MT_EXECUTE_NEVER = U(1) << MT_EXECUTE_SHIFT, } mmap_attr_t; #define MT_CODE (MT_MEMORY | MT_RO | MT_EXECUTE)