diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index a9b7271..0734429 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -361,4 +361,26 @@
 #define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1	0x17D4
 #define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR	0x17DC
 
+/*******************************************************************************
+ * XUSB PADCTL
+ ******************************************************************************/
+#define TEGRA_XUSB_PADCTL_BASE			(0x3520000U)
+#define TEGRA_XUSB_PADCTL_SIZE			(0x10000U)
+#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0	(0x136cU)
+#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0	(0x1370U)
+#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1	(0x1374U)
+#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2	(0x1378U)
+#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3	(0x137cU)
+#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0	(0x139cU)
+
+/*******************************************************************************
+ * XUSB STREAMIDs
+ ******************************************************************************/
+#define TEGRA_SID_XUSB_HOST			(0x1bU)
+#define TEGRA_SID_XUSB_DEV			(0x1cU)
+#define TEGRA_SID_XUSB_VF0			(0x5dU)
+#define TEGRA_SID_XUSB_VF1			(0x5eU)
+#define TEGRA_SID_XUSB_VF2			(0x5fU)
+#define TEGRA_SID_XUSB_VF3			(0x60U)
+
 #endif /* __TEGRA_DEF_H__ */
diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
index a4c35e9..0a39ef1 100644
--- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c
+++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
@@ -151,10 +151,10 @@
 	mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
 	mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE),
 	mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, NO_OVERRIDE, ENABLE),
 	mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
 	mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
 	mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE),
diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c
index a3a2515..1f0c07b 100644
--- a/plat/nvidia/tegra/soc/t194/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t194/plat_setup.c
@@ -92,6 +92,8 @@
 			MT_DEVICE | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000, /* 64KB */
 			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x10000, /* 64KB */
+			MT_DEVICE | MT_RW | MT_SECURE),
 	{0}
 };
 
@@ -151,6 +153,53 @@
 	/* sanity check MCE firmware compatibility */
 	mce_verify_firmware_version();
 
+	/* Program XUSB STREAMIDs
+	 * Xavier XUSB has support for XUSB virtualization. It will have one
+	 * physical function (PF) and four Virtual function (VF)
+	 *
+	 * There were below two SIDs for XUSB until T186.
+	 * 1) #define TEGRA_SID_XUSB_HOST    0x1bU
+	 * 2) #define TEGRA_SID_XUSB_DEV    0x1cU
+	 *
+	 * We have below four new SIDs added for VF(s)
+	 * 3) #define TEGRA_SID_XUSB_VF0    0x5dU
+	 * 4) #define TEGRA_SID_XUSB_VF1    0x5eU
+	 * 5) #define TEGRA_SID_XUSB_VF2    0x5fU
+	 * 6) #define TEGRA_SID_XUSB_VF3    0x60U
+	 *
+	 * When virtualization is enabled then we have to disable SID override
+	 * and program above SIDs in below newly added SID registers in XUSB
+	 * PADCTL MMIO space. These registers are TZ protected and so need to
+	 * be done in ATF.
+	 * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU)
+	 * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0  (0x139cU)
+	 * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U)
+	 * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U)
+	 * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U)
+	 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU)
+	 *
+	 * This change disables SID override and programs XUSB SIDs in
+	 * above registers to support both virtualization and non-virtualization
+	 *
+	 * Known Limitations:
+	 * If xusb interface disables SMMU in XUSB DT in non-virtualization
+	 * setup then there will be SMMU fault. We need to use WAR at
+	 * https://git-master.nvidia.com/r/1529227/ to the issue.
+	 *
+	 * More details can be found in the bug 1971161
+	 */
+	mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+		XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);
+	mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+		XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0);
+	mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+		XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1);
+	mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+		XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2);
+	mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+		XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3);
+	mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+		XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
 }
 
 /* Secure IRQs for Tegra186 */
diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk
index 3f624dd..7ee8b7e 100644
--- a/plat/nvidia/tegra/soc/t194/platform_t194.mk
+++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk
@@ -39,10 +39,10 @@
 PLATFORM_MAX_CPUS_PER_CLUSTER		:= 4
 $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
 
-MAX_XLAT_TABLES				:= 24
+MAX_XLAT_TABLES				:= 25
 $(eval $(call add_define,MAX_XLAT_TABLES))
 
-MAX_MMAP_REGIONS			:= 24
+MAX_MMAP_REGIONS			:= 25
 $(eval $(call add_define,MAX_MMAP_REGIONS))
 
 # platform files