diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c index 02866a2..2e89ecf 100644 --- a/drivers/st/clk/stm32mp1_clk.c +++ b/drivers/st/clk/stm32mp1_clk.c @@ -27,16 +27,16 @@ #include #include -#define MAX_HSI_HZ 64000000 +#define MAX_HSI_HZ 64000000 -#define TIMEOUT_200MS (plat_get_syscnt_freq2() / 5U) -#define TIMEOUT_1S plat_get_syscnt_freq2() +#define TIMEOUT_US_200MS U(200000) +#define TIMEOUT_US_1S U(1000000) -#define PLLRDY_TIMEOUT TIMEOUT_200MS -#define CLKSRC_TIMEOUT TIMEOUT_200MS -#define CLKDIV_TIMEOUT TIMEOUT_200MS -#define HSIDIV_TIMEOUT TIMEOUT_200MS -#define OSCRDY_TIMEOUT TIMEOUT_1S +#define PLLRDY_TIMEOUT TIMEOUT_US_200MS +#define CLKSRC_TIMEOUT TIMEOUT_US_200MS +#define CLKDIV_TIMEOUT TIMEOUT_US_200MS +#define HSIDIV_TIMEOUT TIMEOUT_US_200MS +#define OSCRDY_TIMEOUT TIMEOUT_US_1S enum stm32mp1_parent_id { /* Oscillators are defined in enum stm32mp_osc_id */ @@ -870,7 +870,7 @@ static int stm32mp1_osc_wait(int enable, uint32_t rcc, uint32_t offset, uint32_t mask_rdy) { - unsigned long start; + uint64_t timeout; uint32_t mask_test; uint32_t address = rcc + offset; @@ -880,9 +880,9 @@ mask_test = 0; } - start = get_timer(0); + timeout = timeout_init_us(OSCRDY_TIMEOUT); while ((mmio_read_32(address) & mask_rdy) != mask_test) { - if (get_timer(start) > OSCRDY_TIMEOUT) { + if (timeout_elapsed(timeout)) { ERROR("OSC %x @ %x timeout for enable=%d : 0x%x\n", mask_rdy, address, enable, mmio_read_32(address)); return -ETIMEDOUT; @@ -975,16 +975,16 @@ static int stm32mp1_set_hsidiv(uint32_t rcc, uint8_t hsidiv) { - unsigned long start; uint32_t address = rcc + RCC_OCRDYR; + uint64_t timeout; mmio_clrsetbits_32(rcc + RCC_HSICFGR, RCC_HSICFGR_HSIDIV_MASK, RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); - start = get_timer(0); + timeout = timeout_init_us(HSIDIV_TIMEOUT); while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { - if (get_timer(start) > HSIDIV_TIMEOUT) { + if (timeout_elapsed(timeout)) { ERROR("HSIDIV failed @ 0x%x: 0x%x\n", address, mmio_read_32(address)); return -ETIMEDOUT; @@ -1032,12 +1032,11 @@ { const struct stm32mp1_clk_pll *pll = priv->data->pll; uint32_t pllxcr = priv->base + pll[pll_id].pllxcr; - unsigned long start; + uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); - start = get_timer(0); /* Wait PLL lock */ while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { - if (get_timer(start) > PLLRDY_TIMEOUT) { + if (timeout_elapsed(timeout)) { ERROR("PLL%d start failed @ 0x%x: 0x%x\n", pll_id, pllxcr, mmio_read_32(pllxcr)); return -ETIMEDOUT; @@ -1055,7 +1054,7 @@ { const struct stm32mp1_clk_pll *pll = priv->data->pll; uint32_t pllxcr = priv->base + pll[pll_id].pllxcr; - unsigned long start; + uint64_t timeout; /* Stop all output */ mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | @@ -1064,10 +1063,10 @@ /* Stop PLL */ mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); - start = get_timer(0); + timeout = timeout_init_us(PLLRDY_TIMEOUT); /* Wait PLL stopped */ while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { - if (get_timer(start) > PLLRDY_TIMEOUT) { + if (timeout_elapsed(timeout)) { ERROR("PLL%d stop failed @ 0x%x: 0x%x\n", pll_id, pllxcr, mmio_read_32(pllxcr)); return -ETIMEDOUT; @@ -1166,14 +1165,14 @@ unsigned int clksrc) { uint32_t address = priv->base + (clksrc >> 4); - unsigned long start; + uint64_t timeout; mmio_clrsetbits_32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK); - start = get_timer(0); + timeout = timeout_init_us(CLKSRC_TIMEOUT); while ((mmio_read_32(address) & RCC_SELR_SRCRDY) == 0U) { - if (get_timer(start) > CLKSRC_TIMEOUT) { + if (timeout_elapsed(timeout)) { ERROR("CLKSRC %x start failed @ 0x%x: 0x%x\n", clksrc, address, mmio_read_32(address)); return -ETIMEDOUT; @@ -1185,14 +1184,14 @@ static int stm32mp1_set_clkdiv(unsigned int clkdiv, uint32_t address) { - unsigned long start; + uint64_t timeout; mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK); - start = get_timer(0); + timeout = timeout_init_us(CLKDIV_TIMEOUT); while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { - if (get_timer(start) > CLKDIV_TIMEOUT) { + if (timeout_elapsed(timeout)) { ERROR("CLKDIV %x start failed @ 0x%x: 0x%x\n", clkdiv, address, mmio_read_32(address)); return -ETIMEDOUT; diff --git a/drivers/st/ddr/stm32mp1_ddr.c b/drivers/st/ddr/stm32mp1_ddr.c index 26a5a4d..9db0c5d 100644 --- a/drivers/st/ddr/stm32mp1_ddr.c +++ b/drivers/st/ddr/stm32mp1_ddr.c @@ -29,7 +29,7 @@ #define INVALID_OFFSET 0xFFU -#define TIMESLOT_1US (plat_get_syscnt_freq2() / 1000000U) +#define TIMEOUT_US_1S 1000000U #define DDRCTL_REG(x, y) \ { \ @@ -324,49 +324,43 @@ { uint32_t pgsr; int error = 0; - unsigned long start; - unsigned long time0, time; - - start = get_timer(0); - time0 = start; + uint64_t timeout = timeout_init_us(TIMEOUT_US_1S); do { pgsr = mmio_read_32((uintptr_t)&phy->pgsr); - time = get_timer(start); - if (time != time0) { - VERBOSE(" > [0x%lx] pgsr = 0x%x &\n", - (uintptr_t)&phy->pgsr, pgsr); - VERBOSE(" [0x%lx] pir = 0x%x (time=%lx)\n", - (uintptr_t)&phy->pir, - mmio_read_32((uintptr_t)&phy->pir), - time); - } - time0 = time; - if (time > plat_get_syscnt_freq2()) { + VERBOSE(" > [0x%lx] pgsr = 0x%x &\n", + (uintptr_t)&phy->pgsr, pgsr); + + if (timeout_elapsed(timeout)) { panic(); } + if ((pgsr & DDRPHYC_PGSR_DTERR) != 0U) { VERBOSE("DQS Gate Trainig Error\n"); error++; } + if ((pgsr & DDRPHYC_PGSR_DTIERR) != 0U) { VERBOSE("DQS Gate Trainig Intermittent Error\n"); error++; } + if ((pgsr & DDRPHYC_PGSR_DFTERR) != 0U) { VERBOSE("DQS Drift Error\n"); error++; } + if ((pgsr & DDRPHYC_PGSR_RVERR) != 0U) { VERBOSE("Read Valid Training Error\n"); error++; } + if ((pgsr & DDRPHYC_PGSR_RVEIRR) != 0U) { VERBOSE("Read Valid Training Intermittent Error\n"); error++; } - } while ((pgsr & DDRPHYC_PGSR_IDONE) == 0U && error == 0); + } while (((pgsr & DDRPHYC_PGSR_IDONE) == 0U) && (error == 0)); VERBOSE("\n[0x%lx] pgsr = 0x%x\n", (uintptr_t)&phy->pgsr, pgsr); } @@ -398,21 +392,19 @@ /* Wait quasi dynamic register update */ static void stm32mp1_wait_sw_done_ack(struct stm32mp1_ddrctl *ctl) { - unsigned long start; + uint64_t timeout; uint32_t swstat; mmio_setbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE); VERBOSE("[0x%lx] swctl = 0x%x\n", (uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl)); - start = get_timer(0); + timeout = timeout_init_us(TIMEOUT_US_1S); do { swstat = mmio_read_32((uintptr_t)&ctl->swstat); VERBOSE("[0x%lx] swstat = 0x%x ", (uintptr_t)&ctl->swstat, swstat); - VERBOSE("timer in ms 0x%x = start 0x%lx\r", - get_timer(0), start); - if (get_timer(start) > plat_get_syscnt_freq2()) { + if (timeout_elapsed(timeout)) { panic(); } } while ((swstat & DDRCTRL_SWSTAT_SW_DONE_ACK) == 0U); @@ -424,22 +416,21 @@ /* Wait quasi dynamic register update */ static void stm32mp1_wait_operating_mode(struct ddr_info *priv, uint32_t mode) { - unsigned long start; + uint64_t timeout; uint32_t stat; - uint32_t operating_mode; - uint32_t selref_type; int break_loop = 0; - start = get_timer(0); + timeout = timeout_init_us(TIMEOUT_US_1S); for ( ; ; ) { + uint32_t operating_mode; + uint32_t selref_type; + stat = mmio_read_32((uintptr_t)&priv->ctl->stat); operating_mode = stat & DDRCTRL_STAT_OPERATING_MODE_MASK; selref_type = stat & DDRCTRL_STAT_SELFREF_TYPE_MASK; VERBOSE("[0x%lx] stat = 0x%x\n", (uintptr_t)&priv->ctl->stat, stat); - VERBOSE("timer in ms 0x%x = start 0x%lx\r", - get_timer(0), start); - if (get_timer(start) > plat_get_syscnt_freq2()) { + if (timeout_elapsed(timeout)) { panic(); } diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c index dce8345..017dd88 100644 --- a/drivers/st/mmc/stm32_sdmmc2.c +++ b/drivers/st/mmc/stm32_sdmmc2.c @@ -119,8 +119,8 @@ SDMMC_STAR_IDMATE | \ SDMMC_STAR_IDMABTC) -#define TIMEOUT_10_MS (plat_get_syscnt_freq2() / 100U) -#define TIMEOUT_1_S plat_get_syscnt_freq2() +#define TIMEOUT_US_10_MS 10000U +#define TIMEOUT_US_1_S 1000000U #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" @@ -181,11 +181,12 @@ static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) { + uint64_t timeout; uint32_t flags_cmd, status; uint32_t flags_data = 0; int err = 0; uintptr_t base = sdmmc2_params.reg_base; - unsigned int cmd_reg, arg_reg, start; + unsigned int cmd_reg, arg_reg; if (cmd == NULL) { return -EINVAL; @@ -268,10 +269,10 @@ status = mmio_read_32(base + SDMMC_STAR); - start = get_timer(0); + timeout = timeout_init_us(TIMEOUT_US_10_MS); while ((status & flags_cmd) == 0U) { - if (get_timer(start) > TIMEOUT_10_MS) { + if (timeout_elapsed(timeout)) { err = -ETIMEDOUT; ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", __func__, cmd->cmd_idx, status); @@ -335,10 +336,10 @@ status = mmio_read_32(base + SDMMC_STAR); - start = get_timer(0); + timeout = timeout_init_us(TIMEOUT_US_10_MS); while ((status & flags_data) == 0U) { - if (get_timer(start) > TIMEOUT_10_MS) { + if (timeout_elapsed(timeout)) { ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", __func__, cmd->cmd_idx, status); err = -ETIMEDOUT; @@ -360,7 +361,7 @@ mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS); - if (err != 0) { + if ((err != 0) && ((status & SDMMC_STAR_DPSMACT) != 0U)) { int ret_stop = stm32_sdmmc2_stop_transfer(); if (ret_stop != 0) { @@ -519,7 +520,7 @@ uint32_t *buffer; uintptr_t base = sdmmc2_params.reg_base; uintptr_t fifo_reg = base + SDMMC_FIFOR; - unsigned int start; + uint64_t timeout; int ret; /* Assert buf is 4 bytes aligned */ @@ -537,7 +538,7 @@ flags |= SDMMC_STAR_DBCKEND; } - start = get_timer(0); + timeout = timeout_init_us(TIMEOUT_US_1_S); do { status = mmio_read_32(base + SDMMC_STAR); @@ -559,7 +560,7 @@ return -EIO; } - if (get_timer(start) > TIMEOUT_1_S) { + if (timeout_elapsed(timeout)) { ERROR("%s: timeout 1s (status = %x)\n", __func__, status); mmio_write_32(base + SDMMC_ICR, diff --git a/include/drivers/st/stm32mp1_clk.h b/include/drivers/st/stm32mp1_clk.h index 11ff7bf..3ba8909 100644 --- a/include/drivers/st/stm32mp1_clk.h +++ b/include/drivers/st/stm32mp1_clk.h @@ -13,13 +13,4 @@ int stm32mp1_clk_init(void); void stm32mp1_stgen_increment(unsigned long long offset_in_ms); -static inline uint32_t get_timer(uint32_t base) -{ - if (base == 0U) { - return (uint32_t)(~read_cntpct_el0()); - } - - return base - (uint32_t)(~read_cntpct_el0()); -} - #endif /* STM32MP1_CLK_H */