diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index a9ed9c1..8c951de 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -76,6 +76,9 @@ - ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. +- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 + CPU. This needs to be enabled only for revision >= r3p0 of the CPU. + For Cortex-A53, the following errata build flags are defined : - ``ERRATA_A53_819472``: This applies errata 819472 workaround to all diff --git a/include/lib/cpus/aarch32/cortex_a15.h b/include/lib/cpus/aarch32/cortex_a15.h index 957afbd..9526a9c 100644 --- a/include/lib/cpus/aarch32/cortex_a15.h +++ b/include/lib/cpus/aarch32/cortex_a15.h @@ -10,6 +10,13 @@ #include /******************************************************************************* + * Auxiliary Control Register 2 specific definitions. + ******************************************************************************/ +#define CORTEX_A15_ACTLR2 p15, 1, c15, c0, 4 + +#define CORTEX_A15_ACTLR2_INV_DCC_BIT (U(1) << 0) + +/******************************************************************************* * Cortex-A15 midr with version/revision set to 0 ******************************************************************************/ #define CORTEX_A15_MIDR U(0x410FC0F0) diff --git a/lib/cpus/aarch32/cortex_a15.S b/lib/cpus/aarch32/cortex_a15.S index 8c3bbf4..ab136ad 100644 --- a/lib/cpus/aarch32/cortex_a15.S +++ b/lib/cpus/aarch32/cortex_a15.S @@ -62,6 +62,35 @@ bx lr endfunc check_errata_816470 + /* ---------------------------------------------------- + * Errata Workaround for Cortex A15 Errata #827671. + * This applies only to revision >= r3p0 of Cortex A15. + * Inputs: + * r0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: r0-r3 + * ---------------------------------------------------- + */ +func errata_a15_827671_wa + /* + * Compare r0 against revision r3p0 + */ + mov r2, lr + bl check_errata_827671 + cmp r0, #ERRATA_NOT_APPLIES + beq 1f + ldcopr r0, CORTEX_A15_ACTLR2 + orr r0, #CORTEX_A15_ACTLR2_INV_DCC_BIT + stcopr r0, CORTEX_A15_ACTLR2 + isb +1: + bx r2 +endfunc errata_a15_827671_wa + +func check_errata_827671 + mov r1, #0x30 + b cpu_rev_var_hs +endfunc check_errata_827671 + func check_errata_cve_2017_5715 #if WORKAROUND_CVE_2017_5715 mov r0, #ERRATA_APPLIES @@ -86,6 +115,7 @@ * checking functions of each errata. */ report_errata ERRATA_A15_816470, cortex_a15, 816470 + report_errata ERRATA_A15_827671, cortex_a15, 827671 report_errata WORKAROUND_CVE_2017_5715, cortex_a15, cve_2017_5715 pop {r12, lr} @@ -94,6 +124,13 @@ #endif func cortex_a15_reset_func + mov r5, lr + bl cpu_get_rev_var + +#if ERRATA_A15_827671 + bl errata_a15_827671_wa +#endif + #if IMAGE_BL32 && WORKAROUND_CVE_2017_5715 ldcopr r0, ACTLR orr r0, #CORTEX_A15_ACTLR_INV_BTB_BIT @@ -103,6 +140,8 @@ stcopr r0, MVBAR /* isb will be applied in the course of the reset func */ #endif + + mov lr, r5 b cortex_a15_enable_smp endfunc cortex_a15_reset_func diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index a82db10..f178f1a 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -57,6 +57,10 @@ # applies only to revision >= r3p0 of the Cortex A15 cpu. ERRATA_A15_816470 ?=0 +# Flag to apply erratum 827671 workaround during reset. This erratum applies +# only to revision >= r3p0 of the Cortex A15 cpu. +ERRATA_A15_827671 ?=0 + # Flag to apply erratum 819472 workaround during reset. This erratum applies # only to revision <= r0p1 of the Cortex A53 cpu. ERRATA_A53_819472 ?=0 @@ -204,6 +208,10 @@ $(eval $(call assert_boolean,ERRATA_A15_816470)) $(eval $(call add_define,ERRATA_A15_816470)) +# Process ERRATA_A15_827671 flag +$(eval $(call assert_boolean,ERRATA_A15_827671)) +$(eval $(call add_define,ERRATA_A15_827671)) + # Process ERRATA_A53_819472 flag $(eval $(call assert_boolean,ERRATA_A53_819472)) $(eval $(call add_define,ERRATA_A53_819472))