diff --git a/drivers/st/reset/stm32mp1_reset.c b/drivers/st/reset/stm32mp1_reset.c index b2de760..fd3f93e 100644 --- a/drivers/st/reset/stm32mp1_reset.c +++ b/drivers/st/reset/stm32mp1_reset.c @@ -10,33 +10,53 @@ #include #include +#include #include #include #include -#define RST_CLR_OFFSET 4U +#define RESET_TIMEOUT_US_1MS U(1000) + +static uint32_t id2reg_offset(unsigned int reset_id) +{ + return ((reset_id & GENMASK(31, 5)) >> 5) * sizeof(uint32_t); +} + +static uint8_t id2reg_bit_pos(unsigned int reset_id) +{ + return (uint8_t)(reset_id & GENMASK(4, 0)); +} void stm32mp_reset_assert(uint32_t id) { - uint32_t offset = (id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t); - uint32_t bit = id % (uint32_t)__LONG_BIT; + uint32_t offset = id2reg_offset(id); + uint32_t bitmsk = BIT(id2reg_bit_pos(id)); + uint64_t timeout_ref; uintptr_t rcc_base = stm32mp_rcc_base(); - mmio_write_32(rcc_base + offset, BIT(bit)); - while ((mmio_read_32(rcc_base + offset) & BIT(bit)) == 0U) { - ; + mmio_write_32(rcc_base + offset, bitmsk); + + timeout_ref = timeout_init_us(RESET_TIMEOUT_US_1MS); + while ((mmio_read_32(rcc_base + offset) & bitmsk) == 0U) { + if (timeout_elapsed(timeout_ref)) { + panic(); + } } } void stm32mp_reset_deassert(uint32_t id) { - uint32_t offset = ((id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t)) + - RST_CLR_OFFSET; - uint32_t bit = id % (uint32_t)__LONG_BIT; + uint32_t offset = id2reg_offset(id) + RCC_RSTCLRR_OFFSET; + uint32_t bitmsk = BIT(id2reg_bit_pos(id)); + uint64_t timeout_ref; uintptr_t rcc_base = stm32mp_rcc_base(); - mmio_write_32(rcc_base + offset, BIT(bit)); - while ((mmio_read_32(rcc_base + offset) & BIT(bit)) != 0U) { - ; + mmio_write_32(rcc_base + offset, bitmsk); + + timeout_ref = timeout_init_us(RESET_TIMEOUT_US_1MS); + while ((mmio_read_32(rcc_base + offset) & bitmsk) != 0U) { + if (timeout_elapsed(timeout_ref)) { + panic(); + } } } diff --git a/include/drivers/st/stm32mp1_rcc.h b/include/drivers/st/stm32mp1_rcc.h index 2f29e84..1922c48 100644 --- a/include/drivers/st/stm32mp1_rcc.h +++ b/include/drivers/st/stm32mp1_rcc.h @@ -280,6 +280,9 @@ /* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ #define RCC_MP_ENCLRR_OFFSET U(4) +/* Offset between RCC_xxxRSTSETR and RCC_xxxRSTCLRR registers */ +#define RCC_RSTCLRR_OFFSET U(4) + /* Fields of RCC_BDCR register */ #define RCC_BDCR_LSEON BIT(0) #define RCC_BDCR_LSEBYP BIT(1)