diff --git a/plat/intel/soc/agilex/aarch64/plat_helpers.S b/plat/intel/soc/agilex/aarch64/plat_helpers.S deleted file mode 100644 index b3f5a5e..0000000 --- a/plat/intel/soc/agilex/aarch64/plat_helpers.S +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - - .globl plat_secondary_cold_boot_setup - .globl platform_is_primary_cpu - .globl plat_is_my_cpu_primary - .globl plat_my_core_pos - .globl plat_crash_console_init - .globl plat_crash_console_putc - .globl plat_crash_console_flush - .globl platform_mem_init - - .globl plat_get_my_entrypoint - - /* ----------------------------------------------------- - * void plat_secondary_cold_boot_setup (void); - * - * This function performs any platform specific actions - * needed for a secondary cpu after a cold reset e.g - * mark the cpu's presence, mechanism to place it in a - * holding pen etc. - * ----------------------------------------------------- - */ -func plat_secondary_cold_boot_setup - /* Wait until the it gets reset signal from rstmgr gets populated */ -poll_mailbox: - wfi - - mov_imm x0, PLAT_AGX_SEC_ENTRY - ldr x1, [x0] - mov_imm x2, PLAT_CPUID_RELEASE - ldr x3, [x2] - mrs x4, mpidr_el1 - and x4, x4, #0xff - cmp x3, x4 - b.ne poll_mailbox - br x1 -endfunc plat_secondary_cold_boot_setup - -func platform_is_primary_cpu - and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) - cmp x0, #PLAT_PRIMARY_CPU - cset x0, eq - ret -endfunc platform_is_primary_cpu - -func plat_is_my_cpu_primary - mrs x0, mpidr_el1 - b platform_is_primary_cpu -endfunc plat_is_my_cpu_primary - -func plat_my_core_pos - mrs x0, mpidr_el1 - and x1, x0, #MPIDR_CPU_MASK - and x0, x0, #MPIDR_CLUSTER_MASK - add x0, x1, x0, LSR #6 - ret -endfunc plat_my_core_pos - -func plat_get_my_entrypoint - mov_imm x1, PLAT_AGX_SEC_ENTRY - ldr x0, [x1] - ret -endfunc plat_get_my_entrypoint - - /* --------------------------------------------- - * int plat_crash_console_init(void) - * Function to initialize the crash console - * without a C Runtime to print crash report. - * Clobber list : x0, x1, x2 - * --------------------------------------------- - */ -func plat_crash_console_init - mov_imm x0, PLAT_UART0_BASE - mov_imm x1, PLAT_UART_CLOCK - mov_imm x2, PLAT_BAUDRATE - b console_16550_core_init -endfunc plat_crash_console_init - - /* --------------------------------------------- - * int plat_crash_console_putc(void) - * Function to print a character on the crash - * console without a C Runtime. - * Clobber list : x1, x2 - * --------------------------------------------- - */ -func plat_crash_console_putc - mov_imm x1, PLAT_UART0_BASE - b console_16550_core_putc -endfunc plat_crash_console_putc - -func plat_crash_console_flush - mov_imm x0, CRASH_CONSOLE_BASE - b console_16550_core_flush -endfunc plat_crash_console_flush - - - /* -------------------------------------------------------- - * void platform_mem_init (void); - * - * Any memory init, relocation to be done before the - * platform boots. Called very early in the boot process. - * -------------------------------------------------------- - */ -func platform_mem_init - mov x0, #0 - ret -endfunc platform_mem_init diff --git a/plat/intel/soc/agilex/aarch64/platform_common.c b/plat/intel/soc/agilex/aarch64/platform_common.c deleted file mode 100644 index 6d3d817..0000000 --- a/plat/intel/soc/agilex/aarch64/platform_common.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include - - -unsigned int plat_get_syscnt_freq2(void) -{ - return PLAT_SYS_COUNTER_FREQ_IN_TICKS; -} - -unsigned long socfpga_get_ns_image_entrypoint(void) -{ - return PLAT_NS_IMAGE_OFFSET; -} - -/****************************************************************************** - * Gets SPSR for BL32 entry - *****************************************************************************/ -uint32_t socfpga_get_spsr_for_bl32_entry(void) -{ - /* - * The Secure Payload Dispatcher service is responsible for - * setting the SPSR prior to entry into the BL32 image. - */ - return 0; -} - -/****************************************************************************** - * Gets SPSR for BL33 entry - *****************************************************************************/ -uint32_t socfpga_get_spsr_for_bl33_entry(void) -{ - unsigned long el_status; - unsigned int mode; - uint32_t spsr; - - /* Figure out what mode we enter the non-secure world in */ - el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; - el_status &= ID_AA64PFR0_ELX_MASK; - - mode = (el_status) ? MODE_EL2 : MODE_EL1; - - /* - * TODO: Consider the possibility of specifying the SPSR in - * the FIP ToC and allowing the platform to have a say as - * well. - */ - spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); - return spsr; -} - diff --git a/plat/intel/soc/agilex/bl2_plat_mem_params_desc.c b/plat/intel/soc/agilex/bl2_plat_mem_params_desc.c deleted file mode 100644 index 4f75665..0000000 --- a/plat/intel/soc/agilex/bl2_plat_mem_params_desc.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - - -/******************************************************************************* - * Following descriptor provides BL image/ep information that gets used - * by BL2 to load the images and also subset of this information is - * passed to next BL image. The image loading sequence is managed by - * populating the images in required loading order. The image execution - * sequence is managed by populating the `next_handoff_image_id` with - * the next executable image id. - ******************************************************************************/ -static bl_mem_params_node_t bl2_mem_params_descs[] = { -#ifdef SCP_BL2_BASE - /* Fill SCP_BL2 related information if it exists */ - { - .image_id = SCP_BL2_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, 0), - .image_info.image_base = SCP_BL2_BASE, - .image_info.image_max_size = SCP_BL2_SIZE, - - .next_handoff_image_id = INVALID_IMAGE_ID, - }, -#endif /* SCP_BL2_BASE */ - -#ifdef EL3_PAYLOAD_BASE - /* Fill EL3 payload related information (BL31 is EL3 payload)*/ - { - .image_id = BL31_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = EL3_PAYLOAD_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), - - .next_handoff_image_id = INVALID_IMAGE_ID, - }, - -#else /* EL3_PAYLOAD_BASE */ - - /* Fill BL31 related information */ - { - .image_id = BL31_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = BL31_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), - .image_info.image_base = BL31_BASE, - .image_info.image_max_size = BL31_LIMIT - BL31_BASE, - - .next_handoff_image_id = BL33_IMAGE_ID, - }, -#endif /* EL3_PAYLOAD_BASE */ - - { - .image_id = BL33_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), - .ep_info.pc = PLAT_NS_IMAGE_OFFSET, - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = PLAT_NS_IMAGE_OFFSET, - .image_info.image_max_size = - 0x0 + 0x40000000 - PLAT_NS_IMAGE_OFFSET, - - .next_handoff_image_id = INVALID_IMAGE_ID, - }, -}; - -REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs) diff --git a/plat/intel/soc/agilex/include/plat_macros.S b/plat/intel/soc/agilex/include/plat_macros.S deleted file mode 100644 index 43db9a2..0000000 --- a/plat/intel/soc/agilex/include/plat_macros.S +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef PLAT_MACROS_S -#define PLAT_MACROS_S - -#include - - /* --------------------------------------------- - * The below required platform porting macro - * prints out relevant platform registers - * whenever an unhandled exception is taken in - * BL31. - * --------------------------------------------- - */ - .macro plat_crash_print_regs - .endm - -#endif /* PLAT_MACROS_S */ diff --git a/plat/intel/soc/agilex/include/platform_def.h b/plat/intel/soc/agilex/include/platform_def.h index 10f7338..277862a 100644 --- a/plat/intel/soc/agilex/include/platform_def.h +++ b/plat/intel/soc/agilex/include/platform_def.h @@ -15,7 +15,7 @@ #define PLAT_CPUID_RELEASE 0xffe1b000 -#define PLAT_AGX_SEC_ENTRY 0xffe1b008 +#define PLAT_SEC_ENTRY 0xffe1b008 /* Define next boot image name and offset */ #define PLAT_NS_IMAGE_OFFSET 0x50000 diff --git a/plat/intel/soc/agilex/include/socfpga_private.h b/plat/intel/soc/agilex/include/socfpga_private.h deleted file mode 100644 index 6ab1409..0000000 --- a/plat/intel/soc/agilex/include/socfpga_private.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef PLATFORM_PRIVATE_H -#define PLATFORM_PRIVATE_H - -/******************************************************************************* - * Function and variable prototypes - ******************************************************************************/ -void socfgpa_configure_mmu_el3(unsigned long total_base, - unsigned long total_size, - unsigned long ro_start, - unsigned long ro_limit, - unsigned long coh_start, - unsigned long coh_limit); - - -void socfpga_configure_mmu_el1(unsigned long total_base, - unsigned long total_size, - unsigned long ro_start, - unsigned long ro_limit, - unsigned long coh_start, - unsigned long coh_limit); - -void socfpga_delay_timer_init(void); - -void socfpga_gic_driver_init(void); - -uint32_t socfpga_get_spsr_for_bl32_entry(void); - -uint32_t socfpga_get_spsr_for_bl33_entry(void); - -unsigned long socfpga_get_ns_image_entrypoint(void); - - -#endif /* PLATFORM_PRIVATE_H */ diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index 22ff160..5d20462 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -7,7 +7,8 @@ # PLAT_INCLUDES := \ -Iplat/intel/soc/agilex/include/ \ - -Iplat/intel/soc/common/drivers/ + -Iplat/intel/soc/common/drivers/ \ + -Iplat/intel/soc/common/include/ PLAT_BL_COMMON_SOURCES := \ drivers/arm/gic/common/gic_common.c \ @@ -19,8 +20,8 @@ lib/xlat_tables/aarch64/xlat_tables.c \ lib/xlat_tables/xlat_tables_common.c \ plat/common/plat_gicv2.c \ - plat/intel/soc/agilex/aarch64/platform_common.c \ - plat/intel/soc/agilex/aarch64/plat_helpers.S \ + plat/intel/soc/common/aarch64/platform_common.c \ + plat/intel/soc/common/aarch64/plat_helpers.S BL2_SOURCES += \ common/desc_image_load.c \ @@ -37,14 +38,14 @@ lib/cpus/aarch64/cortex_a53.S \ plat/intel/soc/agilex/bl2_plat_setup.c \ plat/intel/soc/agilex/socfpga_storage.c \ - plat/intel/soc/agilex/bl2_plat_mem_params_desc.c \ + plat/intel/soc/common/bl2_plat_mem_params_desc.c \ plat/intel/soc/agilex/soc/agilex_reset_manager.c \ plat/intel/soc/agilex/soc/agilex_handoff.c \ plat/intel/soc/agilex/soc/agilex_clock_manager.c \ plat/intel/soc/agilex/soc/agilex_pinmux.c \ plat/intel/soc/agilex/soc/agilex_memory_controller.c \ - plat/intel/soc/agilex/socfpga_delay_timer.c \ - plat/intel/soc/agilex/socfpga_image_load.c \ + plat/intel/soc/common/socfpga_delay_timer.c \ + plat/intel/soc/common/socfpga_image_load.c \ plat/intel/soc/agilex/soc/agilex_system_manager.c \ plat/intel/soc/agilex/soc/agilex_mailbox.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ @@ -59,8 +60,8 @@ plat/intel/soc/agilex/socfpga_sip_svc.c \ plat/intel/soc/agilex/bl31_plat_setup.c \ plat/intel/soc/agilex/socfpga_psci.c \ - plat/intel/soc/agilex/socfpga_topology.c \ - plat/intel/soc/agilex/socfpga_delay_timer.c \ + plat/intel/soc/common/socfpga_topology.c \ + plat/intel/soc/common/socfpga_delay_timer.c \ plat/intel/soc/agilex/soc/agilex_reset_manager.c \ plat/intel/soc/agilex/soc/agilex_pinmux.c \ plat/intel/soc/agilex/soc/agilex_clock_manager.c \ diff --git a/plat/intel/soc/agilex/socfpga_delay_timer.c b/plat/intel/soc/agilex/socfpga_delay_timer.c deleted file mode 100644 index e74b8bd..0000000 --- a/plat/intel/soc/agilex/socfpga_delay_timer.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - -#define AGX_GLOBAL_TIMER 0xffd01000 -#define AGX_GLOBAL_TIMER_EN 0x3 - -/******************************************************************** - * The timer delay function - ********************************************************************/ -static uint32_t socfpga_get_timer_value(void) -{ - /* - * Generic delay timer implementation expects the timer to be a down - * counter. We apply bitwise NOT operator to the tick values returned - * by read_cntpct_el0() to simulate the down counter. The value is - * clipped from 64 to 32 bits. - */ - return (uint32_t)(~read_cntpct_el0()); -} - -static const timer_ops_t plat_timer_ops = { - .get_timer_value = socfpga_get_timer_value, - .clk_mult = 1, - .clk_div = PLAT_SYS_COUNTER_FREQ_IN_MHZ, -}; - -void socfpga_delay_timer_init(void) -{ - timer_init(&plat_timer_ops); - mmio_write_32(AGX_GLOBAL_TIMER, AGX_GLOBAL_TIMER_EN); -} diff --git a/plat/intel/soc/agilex/socfpga_image_load.c b/plat/intel/soc/agilex/socfpga_image_load.c deleted file mode 100644 index 67c02bc..0000000 --- a/plat/intel/soc/agilex/socfpga_image_load.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -/******************************************************************************* - * This function flushes the data structures so that they are visible - * in memory for the next BL image. - ******************************************************************************/ -void plat_flush_next_bl_params(void) -{ - flush_bl_params_desc(); -} - -/******************************************************************************* - * This function returns the list of loadable images. - ******************************************************************************/ -bl_load_info_t *plat_get_bl_image_load_info(void) -{ - return get_bl_load_info_from_mem_params_desc(); -} - -/******************************************************************************* - * This function returns the list of executable images. - ******************************************************************************/ -bl_params_t *plat_get_next_bl_params(void) -{ - return get_next_bl_params_from_mem_params_desc(); -} diff --git a/plat/intel/soc/agilex/socfpga_psci.c b/plat/intel/soc/agilex/socfpga_psci.c index 411e89b..04d8a0e 100644 --- a/plat/intel/soc/agilex/socfpga_psci.c +++ b/plat/intel/soc/agilex/socfpga_psci.c @@ -17,7 +17,7 @@ #define AGX_RSTMGR_OFST 0xffd11000 #define AGX_RSTMGR_MPUMODRST_OFST 0x20 -uintptr_t *agilex_sec_entry = (uintptr_t *) PLAT_AGX_SEC_ENTRY; +uintptr_t *agilex_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY; uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE; /******************************************************************************* diff --git a/plat/intel/soc/agilex/socfpga_topology.c b/plat/intel/soc/agilex/socfpga_topology.c deleted file mode 100644 index ca1a91e..0000000 --- a/plat/intel/soc/agilex/socfpga_topology.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -static const unsigned char plat_power_domain_tree_desc[] = {1, 4}; - -/******************************************************************************* - * This function returns the default topology tree information. - ******************************************************************************/ -const unsigned char *plat_get_power_domain_tree_desc(void) -{ - return plat_power_domain_tree_desc; -} - -/******************************************************************************* - * This function implements a part of the critical interface between the psci - * generic layer and the platform that allows the former to query the platform - * to convert an MPIDR to a unique linear index. An error code (-1) is returned - * in case the MPIDR is invalid. - ******************************************************************************/ -int plat_core_pos_by_mpidr(u_register_t mpidr) -{ - unsigned int cluster_id, cpu_id; - - mpidr &= MPIDR_AFFINITY_MASK; - - if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) - return -1; - - cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; - cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; - - if (cluster_id >= PLATFORM_CLUSTER_COUNT) - return -1; - - /* - * Validate cpu_id by checking whether it represents a CPU in - * one of the two clusters present on the platform. - */ - if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) - return -1; - - return (cpu_id + (cluster_id * 4)); -} - diff --git a/plat/intel/soc/common/aarch64/plat_helpers.S b/plat/intel/soc/common/aarch64/plat_helpers.S new file mode 100644 index 0000000..00fe2d9 --- /dev/null +++ b/plat/intel/soc/common/aarch64/plat_helpers.S @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + + .globl plat_secondary_cold_boot_setup + .globl platform_is_primary_cpu + .globl plat_is_my_cpu_primary + .globl plat_my_core_pos + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl plat_crash_console_flush + .globl platform_mem_init + + .globl plat_get_my_entrypoint + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + /* Wait until the it gets reset signal from rstmgr gets populated */ +poll_mailbox: + wfi + + mov_imm x0, PLAT_SEC_ENTRY + ldr x1, [x0] + mov_imm x2, PLAT_CPUID_RELEASE + ldr x3, [x2] + mrs x4, mpidr_el1 + and x4, x4, #0xff + cmp x3, x4 + b.ne poll_mailbox + br x1 +endfunc plat_secondary_cold_boot_setup + +func platform_is_primary_cpu + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #PLAT_PRIMARY_CPU + cset x0, eq + ret +endfunc platform_is_primary_cpu + +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + b platform_is_primary_cpu +endfunc plat_is_my_cpu_primary + +func plat_my_core_pos + mrs x0, mpidr_el1 + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret +endfunc plat_my_core_pos + +func plat_get_my_entrypoint + mov_imm x1, PLAT_SEC_ENTRY + ldr x0, [x1] + ret +endfunc plat_get_my_entrypoint + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0, x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, PLAT_UART0_BASE + mov_imm x1, PLAT_UART_CLOCK + mov_imm x2, PLAT_BAUDRATE + b console_16550_core_init +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(void) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, PLAT_UART0_BASE + b console_16550_core_putc +endfunc plat_crash_console_putc + +func plat_crash_console_flush + mov_imm x0, CRASH_CONSOLE_BASE + b console_16550_core_flush +endfunc plat_crash_console_flush + + + /* -------------------------------------------------------- + * void platform_mem_init (void); + * + * Any memory init, relocation to be done before the + * platform boots. Called very early in the boot process. + * -------------------------------------------------------- + */ +func platform_mem_init + mov x0, #0 + ret +endfunc platform_mem_init diff --git a/plat/intel/soc/common/aarch64/platform_common.c b/plat/intel/soc/common/aarch64/platform_common.c new file mode 100644 index 0000000..6d3d817 --- /dev/null +++ b/plat/intel/soc/common/aarch64/platform_common.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + + +unsigned int plat_get_syscnt_freq2(void) +{ + return PLAT_SYS_COUNTER_FREQ_IN_TICKS; +} + +unsigned long socfpga_get_ns_image_entrypoint(void) +{ + return PLAT_NS_IMAGE_OFFSET; +} + +/****************************************************************************** + * Gets SPSR for BL32 entry + *****************************************************************************/ +uint32_t socfpga_get_spsr_for_bl32_entry(void) +{ + /* + * The Secure Payload Dispatcher service is responsible for + * setting the SPSR prior to entry into the BL32 image. + */ + return 0; +} + +/****************************************************************************** + * Gets SPSR for BL33 entry + *****************************************************************************/ +uint32_t socfpga_get_spsr_for_bl33_entry(void) +{ + unsigned long el_status; + unsigned int mode; + uint32_t spsr; + + /* Figure out what mode we enter the non-secure world in */ + el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; + el_status &= ID_AA64PFR0_ELX_MASK; + + mode = (el_status) ? MODE_EL2 : MODE_EL1; + + /* + * TODO: Consider the possibility of specifying the SPSR in + * the FIP ToC and allowing the platform to have a say as + * well. + */ + spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + return spsr; +} + diff --git a/plat/intel/soc/common/bl2_plat_mem_params_desc.c b/plat/intel/soc/common/bl2_plat_mem_params_desc.c new file mode 100644 index 0000000..4f75665 --- /dev/null +++ b/plat/intel/soc/common/bl2_plat_mem_params_desc.c @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + + +/******************************************************************************* + * Following descriptor provides BL image/ep information that gets used + * by BL2 to load the images and also subset of this information is + * passed to next BL image. The image loading sequence is managed by + * populating the images in required loading order. The image execution + * sequence is managed by populating the `next_handoff_image_id` with + * the next executable image id. + ******************************************************************************/ +static bl_mem_params_node_t bl2_mem_params_descs[] = { +#ifdef SCP_BL2_BASE + /* Fill SCP_BL2 related information if it exists */ + { + .image_id = SCP_BL2_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, 0), + .image_info.image_base = SCP_BL2_BASE, + .image_info.image_max_size = SCP_BL2_SIZE, + + .next_handoff_image_id = INVALID_IMAGE_ID, + }, +#endif /* SCP_BL2_BASE */ + +#ifdef EL3_PAYLOAD_BASE + /* Fill EL3 payload related information (BL31 is EL3 payload)*/ + { + .image_id = BL31_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = EL3_PAYLOAD_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, + IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), + + .next_handoff_image_id = INVALID_IMAGE_ID, + }, + +#else /* EL3_PAYLOAD_BASE */ + + /* Fill BL31 related information */ + { + .image_id = BL31_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = BL31_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), + .image_info.image_base = BL31_BASE, + .image_info.image_max_size = BL31_LIMIT - BL31_BASE, + + .next_handoff_image_id = BL33_IMAGE_ID, + }, +#endif /* EL3_PAYLOAD_BASE */ + + { + .image_id = BL33_IMAGE_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), + .ep_info.pc = PLAT_NS_IMAGE_OFFSET, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = PLAT_NS_IMAGE_OFFSET, + .image_info.image_max_size = + 0x0 + 0x40000000 - PLAT_NS_IMAGE_OFFSET, + + .next_handoff_image_id = INVALID_IMAGE_ID, + }, +}; + +REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs) diff --git a/plat/intel/soc/common/include/plat_macros.S b/plat/intel/soc/common/include/plat_macros.S new file mode 100644 index 0000000..43db9a2 --- /dev/null +++ b/plat/intel/soc/common/include/plat_macros.S @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant platform registers + * whenever an unhandled exception is taken in + * BL31. + * --------------------------------------------- + */ + .macro plat_crash_print_regs + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/intel/soc/common/include/socfpga_private.h b/plat/intel/soc/common/include/socfpga_private.h new file mode 100644 index 0000000..6ab1409 --- /dev/null +++ b/plat/intel/soc/common/include/socfpga_private.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_PRIVATE_H +#define PLATFORM_PRIVATE_H + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ +void socfgpa_configure_mmu_el3(unsigned long total_base, + unsigned long total_size, + unsigned long ro_start, + unsigned long ro_limit, + unsigned long coh_start, + unsigned long coh_limit); + + +void socfpga_configure_mmu_el1(unsigned long total_base, + unsigned long total_size, + unsigned long ro_start, + unsigned long ro_limit, + unsigned long coh_start, + unsigned long coh_limit); + +void socfpga_delay_timer_init(void); + +void socfpga_gic_driver_init(void); + +uint32_t socfpga_get_spsr_for_bl32_entry(void); + +uint32_t socfpga_get_spsr_for_bl33_entry(void); + +unsigned long socfpga_get_ns_image_entrypoint(void); + + +#endif /* PLATFORM_PRIVATE_H */ diff --git a/plat/intel/soc/common/socfpga_delay_timer.c b/plat/intel/soc/common/socfpga_delay_timer.c new file mode 100644 index 0000000..ff8a556 --- /dev/null +++ b/plat/intel/soc/common/socfpga_delay_timer.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#define SOCFPGA_GLOBAL_TIMER 0xffd01000 +#define SOCFPGA_GLOBAL_TIMER_EN 0x3 + +/******************************************************************** + * The timer delay function + ********************************************************************/ +static uint32_t socfpga_get_timer_value(void) +{ + /* + * Generic delay timer implementation expects the timer to be a down + * counter. We apply bitwise NOT operator to the tick values returned + * by read_cntpct_el0() to simulate the down counter. The value is + * clipped from 64 to 32 bits. + */ + return (uint32_t)(~read_cntpct_el0()); +} + +static const timer_ops_t plat_timer_ops = { + .get_timer_value = socfpga_get_timer_value, + .clk_mult = 1, + .clk_div = PLAT_SYS_COUNTER_FREQ_IN_MHZ, +}; + +void socfpga_delay_timer_init(void) +{ + timer_init(&plat_timer_ops); + mmio_write_32(SOCFPGA_GLOBAL_TIMER, SOCFPGA_GLOBAL_TIMER_EN); +} diff --git a/plat/intel/soc/common/socfpga_image_load.c b/plat/intel/soc/common/socfpga_image_load.c new file mode 100644 index 0000000..67c02bc --- /dev/null +++ b/plat/intel/soc/common/socfpga_image_load.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +/******************************************************************************* + * This function flushes the data structures so that they are visible + * in memory for the next BL image. + ******************************************************************************/ +void plat_flush_next_bl_params(void) +{ + flush_bl_params_desc(); +} + +/******************************************************************************* + * This function returns the list of loadable images. + ******************************************************************************/ +bl_load_info_t *plat_get_bl_image_load_info(void) +{ + return get_bl_load_info_from_mem_params_desc(); +} + +/******************************************************************************* + * This function returns the list of executable images. + ******************************************************************************/ +bl_params_t *plat_get_next_bl_params(void) +{ + return get_next_bl_params_from_mem_params_desc(); +} diff --git a/plat/intel/soc/common/socfpga_topology.c b/plat/intel/soc/common/socfpga_topology.c new file mode 100644 index 0000000..ca1a91e --- /dev/null +++ b/plat/intel/soc/common/socfpga_topology.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +static const unsigned char plat_power_domain_tree_desc[] = {1, 4}; + +/******************************************************************************* + * This function returns the default topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return plat_power_domain_tree_desc; +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is returned + * in case the MPIDR is invalid. + ******************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id; + + mpidr &= MPIDR_AFFINITY_MASK; + + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) + return -1; + + cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + + if (cluster_id >= PLATFORM_CLUSTER_COUNT) + return -1; + + /* + * Validate cpu_id by checking whether it represents a CPU in + * one of the two clusters present on the platform. + */ + if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) + return -1; + + return (cpu_id + (cluster_id * 4)); +} + diff --git a/plat/intel/soc/stratix10/aarch64/plat_helpers.S b/plat/intel/soc/stratix10/aarch64/plat_helpers.S deleted file mode 100644 index f077cf3..0000000 --- a/plat/intel/soc/stratix10/aarch64/plat_helpers.S +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - - .globl plat_secondary_cold_boot_setup - .globl platform_is_primary_cpu - .globl plat_is_my_cpu_primary - .globl plat_my_core_pos - .globl plat_crash_console_init - .globl plat_crash_console_putc - .globl plat_crash_console_flush - .globl platform_mem_init - - .globl plat_get_my_entrypoint - - /* ----------------------------------------------------- - * void plat_secondary_cold_boot_setup (void); - * - * This function performs any platform specific actions - * needed for a secondary cpu after a cold reset e.g - * mark the cpu's presence, mechanism to place it in a - * holding pen etc. - * ----------------------------------------------------- - */ -func plat_secondary_cold_boot_setup - /* Wait until the it gets reset signal from rstmgr gets populated */ -poll_mailbox: - wfi - - mov_imm x0, PLAT_S10_SEC_ENTRY - ldr x1, [x0] - mov_imm x2, PLAT_CPUID_RELEASE - ldr x3, [x2] - mrs x4, mpidr_el1 - and x4, x4, #0xff - cmp x3, x4 - b.ne poll_mailbox - br x1 -endfunc plat_secondary_cold_boot_setup - -func platform_is_primary_cpu - and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) - cmp x0, #PLAT_PRIMARY_CPU - cset x0, eq - ret -endfunc platform_is_primary_cpu - -func plat_is_my_cpu_primary - mrs x0, mpidr_el1 - b platform_is_primary_cpu -endfunc plat_is_my_cpu_primary - -func plat_my_core_pos - mrs x0, mpidr_el1 - and x1, x0, #MPIDR_CPU_MASK - and x0, x0, #MPIDR_CLUSTER_MASK - add x0, x1, x0, LSR #6 - ret -endfunc plat_my_core_pos - -func plat_get_my_entrypoint - mov_imm x1, PLAT_S10_SEC_ENTRY - ldr x0, [x1] - ret -endfunc plat_get_my_entrypoint - - /* --------------------------------------------- - * int plat_crash_console_init(void) - * Function to initialize the crash console - * without a C Runtime to print crash report. - * Clobber list : x0, x1, x2 - * --------------------------------------------- - */ -func plat_crash_console_init - mov_imm x0, PLAT_UART0_BASE - mov_imm x1, PLAT_UART_CLOCK - mov_imm x2, PLAT_BAUDRATE - b console_16550_core_init -endfunc plat_crash_console_init - - /* --------------------------------------------- - * int plat_crash_console_putc(void) - * Function to print a character on the crash - * console without a C Runtime. - * Clobber list : x1, x2 - * --------------------------------------------- - */ -func plat_crash_console_putc - mov_imm x1, PLAT_UART0_BASE - b console_16550_core_putc -endfunc plat_crash_console_putc - -func plat_crash_console_flush - mov_imm x0, CRASH_CONSOLE_BASE - b console_16550_core_flush -endfunc plat_crash_console_flush - - - /* -------------------------------------------------------- - * void platform_mem_init (void); - * - * Any memory init, relocation to be done before the - * platform boots. Called very early in the boot process. - * -------------------------------------------------------- - */ -func platform_mem_init - mov x0, #0 - ret -endfunc platform_mem_init - - - .data - .align 3 - diff --git a/plat/intel/soc/stratix10/aarch64/platform_common.c b/plat/intel/soc/stratix10/aarch64/platform_common.c deleted file mode 100644 index 094a362..0000000 --- a/plat/intel/soc/stratix10/aarch64/platform_common.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - -unsigned int plat_get_syscnt_freq2(void) -{ - return PLAT_SYS_COUNTER_FREQ_IN_TICKS; -} - -unsigned long plat_get_ns_image_entrypoint(void) -{ - return PLAT_NS_IMAGE_OFFSET; -} - -/****************************************************************************** - * Gets SPSR for BL32 entry - *****************************************************************************/ -uint32_t plat_get_spsr_for_bl32_entry(void) -{ - /* - * The Secure Payload Dispatcher service is responsible for - * setting the SPSR prior to entry into the BL32 image. - */ - return 0; -} - -/****************************************************************************** - * Gets SPSR for BL33 entry - *****************************************************************************/ -uint32_t plat_get_spsr_for_bl33_entry(void) -{ - unsigned long el_status; - unsigned int mode; - uint32_t spsr; - - /* Figure out what mode we enter the non-secure world in */ - el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; - el_status &= ID_AA64PFR0_ELX_MASK; - - mode = (el_status) ? MODE_EL2 : MODE_EL1; - - /* - * TODO: Consider the possibility of specifying the SPSR in - * the FIP ToC and allowing the platform to have a say as - * well. - */ - spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); - return spsr; -} - diff --git a/plat/intel/soc/stratix10/aarch64/stratix10_private.h b/plat/intel/soc/stratix10/aarch64/stratix10_private.h deleted file mode 100644 index f437202..0000000 --- a/plat/intel/soc/stratix10/aarch64/stratix10_private.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __S10_PRIVATE_H__ -#define __S10_PRIVATE_H__ - -#define S10_MMC_REG_BASE 0xff808000 - -#define EMMC_DESC_SIZE (1<<20) -#define EMMC_INIT_PARAMS(base) \ - { .bus_width = MMC_BUS_WIDTH_4, \ - .clk_rate = 50000000, \ - .desc_base = (base), \ - .desc_size = EMMC_DESC_SIZE, \ - .flags = 0, \ - .reg_base = S10_MMC_REG_BASE, \ - \ - } - -typedef enum { - BOOT_SOURCE_FPGA = 0, - BOOT_SOURCE_SDMMC, - BOOT_SOURCE_NAND, - BOOT_SOURCE_RSVD, - BOOT_SOURCE_QSPI, -} boot_source_type; - -void enable_nonsecure_access(void); -void stratix10_io_setup(int boot_source); - -#endif diff --git a/plat/intel/soc/stratix10/bl2_plat_mem_params_desc.c b/plat/intel/soc/stratix10/bl2_plat_mem_params_desc.c deleted file mode 100644 index 4f75665..0000000 --- a/plat/intel/soc/stratix10/bl2_plat_mem_params_desc.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - - -/******************************************************************************* - * Following descriptor provides BL image/ep information that gets used - * by BL2 to load the images and also subset of this information is - * passed to next BL image. The image loading sequence is managed by - * populating the images in required loading order. The image execution - * sequence is managed by populating the `next_handoff_image_id` with - * the next executable image id. - ******************************************************************************/ -static bl_mem_params_node_t bl2_mem_params_descs[] = { -#ifdef SCP_BL2_BASE - /* Fill SCP_BL2 related information if it exists */ - { - .image_id = SCP_BL2_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, 0), - .image_info.image_base = SCP_BL2_BASE, - .image_info.image_max_size = SCP_BL2_SIZE, - - .next_handoff_image_id = INVALID_IMAGE_ID, - }, -#endif /* SCP_BL2_BASE */ - -#ifdef EL3_PAYLOAD_BASE - /* Fill EL3 payload related information (BL31 is EL3 payload)*/ - { - .image_id = BL31_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = EL3_PAYLOAD_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), - - .next_handoff_image_id = INVALID_IMAGE_ID, - }, - -#else /* EL3_PAYLOAD_BASE */ - - /* Fill BL31 related information */ - { - .image_id = BL31_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = BL31_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), - .image_info.image_base = BL31_BASE, - .image_info.image_max_size = BL31_LIMIT - BL31_BASE, - - .next_handoff_image_id = BL33_IMAGE_ID, - }, -#endif /* EL3_PAYLOAD_BASE */ - - { - .image_id = BL33_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), - .ep_info.pc = PLAT_NS_IMAGE_OFFSET, - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = PLAT_NS_IMAGE_OFFSET, - .image_info.image_max_size = - 0x0 + 0x40000000 - PLAT_NS_IMAGE_OFFSET, - - .next_handoff_image_id = INVALID_IMAGE_ID, - }, -}; - -REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs) diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c index 7830162..8e8b582 100644 --- a/plat/intel/soc/stratix10/bl2_plat_setup.c +++ b/plat/intel/soc/stratix10/bl2_plat_setup.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include @@ -29,7 +29,7 @@ #include "s10_clock_manager.h" #include "s10_handoff.h" #include "s10_pinmux.h" -#include "aarch64/stratix10_private.h" +#include "stratix10_private.h" #include "include/s10_mailbox.h" #include "qspi/cadence_qspi.h" #include "wdt/watchdog.h" @@ -78,7 +78,7 @@ console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE, &console); - plat_delay_timer_init(); + socfpga_delay_timer_init(); init_hard_memory_controller(); } diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c index fcc4620..7c9833b 100644 --- a/plat/intel/soc/stratix10/bl31_plat_setup.c +++ b/plat/intel/soc/stratix10/bl31_plat_setup.c @@ -21,9 +21,8 @@ #include #include #include -#include -#include "aarch64/stratix10_private.h" +#include "stratix10_private.h" #include "s10_handoff.h" #include "s10_reset_manager.h" #include "s10_memory_controller.h" diff --git a/plat/intel/soc/stratix10/include/plat_macros.S b/plat/intel/soc/stratix10/include/plat_macros.S deleted file mode 100644 index 495aa9d..0000000 --- a/plat/intel/soc/stratix10/include/plat_macros.S +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __PLAT_MACROS_S__ -#define __PLAT_MACROS_S__ - -#include - - /* --------------------------------------------- - * The below required platform porting macro - * prints out relevant platform registers - * whenever an unhandled exception is taken in - * BL31. - * --------------------------------------------- - */ - .macro plat_crash_print_regs - .endm - -#endif /* __PLAT_MACROS_S__ */ diff --git a/plat/intel/soc/stratix10/include/platform_def.h b/plat/intel/soc/stratix10/include/platform_def.h new file mode 100644 index 0000000..a753acd --- /dev/null +++ b/plat/intel/soc/stratix10/include/platform_def.h @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +#include +#include +#include +#include +#include +#include + + +#define PLAT_CPUID_RELEASE 0xffe1b000 +#define PLAT_SEC_ENTRY 0xffe1b008 + +/* Define next boot image name and offset */ +#define PLAT_NS_IMAGE_OFFSET 0x50000 +#define PLAT_HANDOFF_OFFSET 0xFFE3F000 + +/******************************************************************************* + * Platform binary types for linking + ******************************************************************************/ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/* Stratix 10 supports up to 124GB RAM */ +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) + + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ +#define PLAT_PRIMARY_CPU 0 +#define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 + +/* Size of cacheable stacks */ +#define PLATFORM_STACK_SIZE 0x2000 + +/* PSCI related constant */ +#define PLAT_NUM_POWER_DOMAINS 5 +#define PLAT_MAX_PWR_LVL 1 +#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_OFF_STATE 2 +#define PLATFORM_SYSTEM_COUNT 1 +#define PLATFORM_CLUSTER_COUNT 1 +#define PLATFORM_CLUSTER0_CORE_COUNT 4 +#define PLATFORM_CLUSTER1_CORE_COUNT 0 +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ + PLATFORM_CLUSTER0_CORE_COUNT) +#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 + +/* Interrupt related constant */ + +#define INTEL_S10_IRQ_SEC_PHY_TIMER 29 + +#define INTEL_S10_IRQ_SEC_SGI_0 8 +#define INTEL_S10_IRQ_SEC_SGI_1 9 +#define INTEL_S10_IRQ_SEC_SGI_2 10 +#define INTEL_S10_IRQ_SEC_SGI_3 11 +#define INTEL_S10_IRQ_SEC_SGI_4 12 +#define INTEL_S10_IRQ_SEC_SGI_5 13 +#define INTEL_S10_IRQ_SEC_SGI_6 14 +#define INTEL_S10_IRQ_SEC_SGI_7 15 + +#define TSP_IRQ_SEC_PHY_TIMER INTEL_S10_IRQ_SEC_PHY_TIMER +#define TSP_SEC_MEM_BASE BL32_BASE +#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +#define DRAM_BASE (0x0) +#define DRAM_SIZE (0x80000000) + +#define OCRAM_BASE (0xFFE00000) +#define OCRAM_SIZE (0x00040000) + +#define MEM64_BASE (0x0100000000) +#define MEM64_SIZE (0x1F00000000) + +#define DEVICE1_BASE (0x80000000) +#define DEVICE1_SIZE (0x60000000) + +#define DEVICE2_BASE (0xF7000000) +#define DEVICE2_SIZE (0x08E00000) + +#define DEVICE3_BASE (0xFFFC0000) +#define DEVICE3_SIZE (0x00008000) + +#define DEVICE4_BASE (0x2000000000) +#define DEVICE4_SIZE (0x0100000000) + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if + * present). BL31_BASE is calculated using the current BL3-1 debug size plus a + * little space for growth. + */ + + +#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" + +#define BL1_RO_BASE (0xffe00000) +#define BL1_RO_LIMIT (0xffe0f000) +#define BL1_RW_BASE (0xffe10000) +#define BL1_RW_LIMIT (0xffe1ffff) +#define BL1_RW_SIZE (0x14000) + +#define BL2_BASE (0xffe00000) +#define BL2_LIMIT (0xffe1b000) + +#define BL31_BASE (0xffe1c000) +#define BL31_LIMIT (0xffe3bfff) + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define MAX_XLAT_TABLES 8 +#define MAX_MMAP_REGIONS 16 + +/******************************************************************************* + * Declarations and constants to access the mailboxes safely. Each mailbox is + * aligned on the biggest cache line size in the platform. This is known only + * to the platform as it might have a combination of integrated and external + * caches. Such alignment ensures that two maiboxes do not sit on the same cache + * line at any cache level. They could belong to different cpus/clusters & + * get written while being protected by different locks causing corruption of + * a valid mailbox address. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#define PLAT_GIC_BASE (0xFFFC0000) +#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) +#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) +#define PLAT_GICR_BASE 0 + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define PLAT_UART0_BASE (0xFFC02000) +#define PLAT_UART1_BASE (0xFFC02100) + +#define CRASH_CONSOLE_BASE PLAT_UART0_BASE + +#define PLAT_BAUDRATE (115200) +#define PLAT_UART_CLOCK (100000000) + +/******************************************************************************* + * System counter frequency related constants + ******************************************************************************/ +#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) +#define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400) + +#define PLAT_INTEL_S10_GICD_BASE PLAT_GICD_BASE +#define PLAT_INTEL_S10_GICC_BASE PLAT_GICC_BASE + +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define PLAT_INTEL_S10_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(INTEL_S10_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE) + +#define PLAT_INTEL_S10_G0_IRQ_PROPS(grp) + +#define MAX_IO_HANDLES 4 +#define MAX_IO_DEVICES 4 +#define MAX_IO_BLOCK_DEVICES 2 + + +#endif /* __PLATFORM_DEF_H__ */ + diff --git a/plat/intel/soc/stratix10/include/platform_private.h b/plat/intel/soc/stratix10/include/platform_private.h deleted file mode 100644 index db0c103..0000000 --- a/plat/intel/soc/stratix10/include/platform_private.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __PLATFORM_PRIVATE_H__ -#define __PLATFORM_PRIVATE_H__ -#include - -/******************************************************************************* - * Function and variable prototypes - ******************************************************************************/ -void plat_configure_mmu_el3(unsigned long total_base, - unsigned long total_size, - unsigned long ro_start, - unsigned long ro_limit, - unsigned long coh_start, - unsigned long coh_limit); - - -void plat_configure_mmu_el1(unsigned long total_base, - unsigned long total_size, - unsigned long ro_start, - unsigned long ro_limit, - unsigned long coh_start, - unsigned long coh_limit); - -void plat_gic_driver_init(void); - -void plat_arm_gic_init(void); - -void plat_delay_timer_init(void); - -unsigned long plat_get_ns_image_entrypoint(void); - -uint32_t plat_get_spsr_for_bl32_entry(void); - -uint32_t plat_get_spsr_for_bl33_entry(void); - -#endif /* __PLATFORM_PRIVATE_H__ */ diff --git a/plat/intel/soc/stratix10/include/stratix10_private.h b/plat/intel/soc/stratix10/include/stratix10_private.h new file mode 100644 index 0000000..f437202 --- /dev/null +++ b/plat/intel/soc/stratix10/include/stratix10_private.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __S10_PRIVATE_H__ +#define __S10_PRIVATE_H__ + +#define S10_MMC_REG_BASE 0xff808000 + +#define EMMC_DESC_SIZE (1<<20) +#define EMMC_INIT_PARAMS(base) \ + { .bus_width = MMC_BUS_WIDTH_4, \ + .clk_rate = 50000000, \ + .desc_base = (base), \ + .desc_size = EMMC_DESC_SIZE, \ + .flags = 0, \ + .reg_base = S10_MMC_REG_BASE, \ + \ + } + +typedef enum { + BOOT_SOURCE_FPGA = 0, + BOOT_SOURCE_SDMMC, + BOOT_SOURCE_NAND, + BOOT_SOURCE_RSVD, + BOOT_SOURCE_QSPI, +} boot_source_type; + +void enable_nonsecure_access(void); +void stratix10_io_setup(int boot_source); + +#endif diff --git a/plat/intel/soc/stratix10/plat_delay_timer.c b/plat/intel/soc/stratix10/plat_delay_timer.c deleted file mode 100644 index bf68cbc..0000000 --- a/plat/intel/soc/stratix10/plat_delay_timer.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - -#define S10_GLOBAL_TIMER 0xffd01000 -#define S10_GLOBAL_TIMER_EN 0x3 - -/******************************************************************** - * The timer delay function - ********************************************************************/ -static uint32_t plat_get_timer_value(void) -{ - /* - * Generic delay timer implementation expects the timer to be a down - * counter. We apply bitwise NOT operator to the tick values returned - * by read_cntpct_el0() to simulate the down counter. The value is - * clipped from 64 to 32 bits. - */ - return (uint32_t)(~read_cntpct_el0()); -} - -static const timer_ops_t plat_timer_ops = { - .get_timer_value = plat_get_timer_value, - .clk_mult = 1, - .clk_div = PLAT_SYS_COUNTER_FREQ_IN_MHZ, -}; - -void plat_delay_timer_init(void) -{ - timer_init(&plat_timer_ops); - mmio_write_32(S10_GLOBAL_TIMER, S10_GLOBAL_TIMER_EN); -} diff --git a/plat/intel/soc/stratix10/plat_psci.c b/plat/intel/soc/stratix10/plat_psci.c index 7578528..f4a970e 100644 --- a/plat/intel/soc/stratix10/plat_psci.c +++ b/plat/intel/soc/stratix10/plat_psci.c @@ -15,14 +15,13 @@ #include #include "platform_def.h" -#include "platform_private.h" #include "s10_reset_manager.h" #include "s10_mailbox.h" #define S10_RSTMGR_OFST 0xffd11000 #define S10_RSTMGR_MPUMODRST_OFST 0x20 -uintptr_t *stratix10_sec_entry = (uintptr_t *) PLAT_S10_SEC_ENTRY; +uintptr_t *stratix10_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY; uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE; /******************************************************************************* diff --git a/plat/intel/soc/stratix10/plat_storage.c b/plat/intel/soc/stratix10/plat_storage.c index f5fd871..0b8b9cd 100644 --- a/plat/intel/soc/stratix10/plat_storage.c +++ b/plat/intel/soc/stratix10/plat_storage.c @@ -21,7 +21,7 @@ #include #include #include "platform_def.h" -#include "aarch64/stratix10_private.h" +#include "stratix10_private.h" #define STRATIX10_FIP_BASE (0) #define STRATIX10_FIP_MAX_SIZE (0x1000000) diff --git a/plat/intel/soc/stratix10/plat_topology.c b/plat/intel/soc/stratix10/plat_topology.c deleted file mode 100644 index 4951f74..0000000 --- a/plat/intel/soc/stratix10/plat_topology.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -static const unsigned char plat_power_domain_tree_desc[] = {1, 4}; - -/******************************************************************************* - * This function returns the default topology tree information. - ******************************************************************************/ -const unsigned char *plat_get_power_domain_tree_desc(void) -{ - return plat_power_domain_tree_desc; -} - -/******************************************************************************* - * This function implements a part of the critical interface between the psci - * generic layer and the platform that allows the former to query the platform - * to convert an MPIDR to a unique linear index. An error code (-1) is returned - * in case the MPIDR is invalid. - ******************************************************************************/ -int plat_core_pos_by_mpidr(u_register_t mpidr) -{ - unsigned int cluster_id, cpu_id; - - mpidr &= MPIDR_AFFINITY_MASK; - - if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) - return -1; - - cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; - cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; - - if (cluster_id >= PLATFORM_CLUSTER_COUNT) - return -1; - - /* - * Validate cpu_id by checking whether it represents a CPU in - * one of the two clusters present on the platform. - */ - if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) - return -1; - - return (cpu_id + (cluster_id * 4)); -} - diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index a21280f..34674b0 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -5,9 +5,9 @@ # PLAT_INCLUDES := \ - -Iplat/intel/soc/stratix10/ \ -Iplat/intel/soc/stratix10/include/ \ - -Iplat/intel/soc/common/drivers/ + -Iplat/intel/soc/common/drivers/ \ + -Iplat/intel/soc/common/include/ PLAT_BL_COMMON_SOURCES := \ lib/xlat_tables/xlat_tables_common.c \ @@ -15,12 +15,12 @@ drivers/arm/gic/common/gic_common.c \ drivers/arm/gic/v2/gicv2_main.c \ drivers/arm/gic/v2/gicv2_helpers.c \ - plat/common/plat_gicv2.c \ + plat/common/plat_gicv2.c \ drivers/delay_timer/delay_timer.c \ drivers/delay_timer/generic_delay_timer.c \ drivers/ti/uart/aarch64/16550_console.S \ - plat/intel/soc/stratix10/aarch64/platform_common.c \ - plat/intel/soc/stratix10/aarch64/plat_helpers.S \ + plat/intel/soc/common/aarch64/platform_common.c \ + plat/intel/soc/common/aarch64/plat_helpers.S BL2_SOURCES += \ drivers/partition/partition.c \ @@ -35,15 +35,15 @@ drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \ plat/intel/soc/stratix10/bl2_plat_setup.c \ plat/intel/soc/stratix10/plat_storage.c \ - plat/intel/soc/stratix10/bl2_plat_mem_params_desc.c \ + plat/intel/soc/common/bl2_plat_mem_params_desc.c \ plat/intel/soc/stratix10/soc/s10_reset_manager.c \ plat/intel/soc/stratix10/soc/s10_handoff.c \ plat/intel/soc/stratix10/soc/s10_clock_manager.c \ plat/intel/soc/stratix10/soc/s10_pinmux.c \ plat/intel/soc/stratix10/soc/s10_memory_controller.c \ - plat/intel/soc/stratix10/plat_delay_timer.c \ + plat/intel/soc/common/socfpga_delay_timer.c \ lib/cpus/aarch64/cortex_a53.S \ - plat/intel/soc/stratix10/stratix10_image_load.c \ + plat/intel/soc/common/socfpga_image_load.c \ plat/intel/soc/stratix10/soc/s10_system_manager.c \ common/desc_image_load.c \ plat/intel/soc/stratix10/soc/s10_mailbox.c \ @@ -58,13 +58,13 @@ plat/intel/soc/stratix10/plat_sip_svc.c \ plat/intel/soc/stratix10/bl31_plat_setup.c \ plat/intel/soc/stratix10/plat_psci.c \ - plat/intel/soc/stratix10/plat_topology.c \ - plat/intel/soc/stratix10/plat_delay_timer.c \ + plat/intel/soc/common/socfpga_topology.c \ + plat/intel/soc/common/socfpga_delay_timer.c \ plat/intel/soc/stratix10/soc/s10_reset_manager.c\ plat/intel/soc/stratix10/soc/s10_pinmux.c \ plat/intel/soc/stratix10/soc/s10_clock_manager.c\ plat/intel/soc/stratix10/soc/s10_handoff.c \ - plat/intel/soc/stratix10/soc/s10_mailbox.c \ + plat/intel/soc/stratix10/soc/s10_mailbox.c PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 diff --git a/plat/intel/soc/stratix10/platform_def.h b/plat/intel/soc/stratix10/platform_def.h deleted file mode 100644 index 3ed9023..0000000 --- a/plat/intel/soc/stratix10/platform_def.h +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __PLATFORM_DEF_H__ -#define __PLATFORM_DEF_H__ - -#include -#include -#include -#include -#include -#include - - -#define PLAT_CPUID_RELEASE 0xffe1b000 -#define PLAT_S10_SEC_ENTRY 0xffe1b008 - -/* Define next boot image name and offset */ -#define PLAT_NS_IMAGE_OFFSET 0x50000 -#define PLAT_HANDOFF_OFFSET 0xFFE3F000 - -/******************************************************************************* - * Platform binary types for linking - ******************************************************************************/ -#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" -#define PLATFORM_LINKER_ARCH aarch64 - -/* Stratix 10 supports up to 124GB RAM */ -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) - - -/******************************************************************************* - * Generic platform constants - ******************************************************************************/ -#define PLAT_PRIMARY_CPU 0 -#define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 - -/* Size of cacheable stacks */ -#define PLATFORM_STACK_SIZE 0x2000 - -/* PSCI related constant */ -#define PLAT_NUM_POWER_DOMAINS 5 -#define PLAT_MAX_PWR_LVL 1 -#define PLAT_MAX_RET_STATE 1 -#define PLAT_MAX_OFF_STATE 2 -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 1 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 0 -#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ - PLATFORM_CLUSTER0_CORE_COUNT) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 - -/* Interrupt related constant */ - -#define INTEL_S10_IRQ_SEC_PHY_TIMER 29 - -#define INTEL_S10_IRQ_SEC_SGI_0 8 -#define INTEL_S10_IRQ_SEC_SGI_1 9 -#define INTEL_S10_IRQ_SEC_SGI_2 10 -#define INTEL_S10_IRQ_SEC_SGI_3 11 -#define INTEL_S10_IRQ_SEC_SGI_4 12 -#define INTEL_S10_IRQ_SEC_SGI_5 13 -#define INTEL_S10_IRQ_SEC_SGI_6 14 -#define INTEL_S10_IRQ_SEC_SGI_7 15 - -#define TSP_IRQ_SEC_PHY_TIMER INTEL_S10_IRQ_SEC_PHY_TIMER -#define TSP_SEC_MEM_BASE BL32_BASE -#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) -/******************************************************************************* - * Platform memory map related constants - ******************************************************************************/ -#define DRAM_BASE (0x0) -#define DRAM_SIZE (0x80000000) - -#define OCRAM_BASE (0xFFE00000) -#define OCRAM_SIZE (0x00040000) - -#define MEM64_BASE (0x0100000000) -#define MEM64_SIZE (0x1F00000000) - -#define DEVICE1_BASE (0x80000000) -#define DEVICE1_SIZE (0x60000000) - -#define DEVICE2_BASE (0xF7000000) -#define DEVICE2_SIZE (0x08E00000) - -#define DEVICE3_BASE (0xFFFC0000) -#define DEVICE3_SIZE (0x00008000) - -#define DEVICE4_BASE (0x2000000000) -#define DEVICE4_SIZE (0x0100000000) - -/******************************************************************************* - * BL31 specific defines. - ******************************************************************************/ -/* - * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if - * present). BL31_BASE is calculated using the current BL3-1 debug size plus a - * little space for growth. - */ - - -#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" - -#define BL1_RO_BASE (0xffe00000) -#define BL1_RO_LIMIT (0xffe0f000) -#define BL1_RW_BASE (0xffe10000) -#define BL1_RW_LIMIT (0xffe1ffff) -#define BL1_RW_SIZE (0x14000) - -#define BL2_BASE (0xffe00000) -#define BL2_LIMIT (0xffe1b000) - -#define BL31_BASE (0xffe1c000) -#define BL31_LIMIT (0xffe3bfff) - -/******************************************************************************* - * Platform specific page table and MMU setup constants - ******************************************************************************/ -#define MAX_XLAT_TABLES 8 -#define MAX_MMAP_REGIONS 16 - -/******************************************************************************* - * Declarations and constants to access the mailboxes safely. Each mailbox is - * aligned on the biggest cache line size in the platform. This is known only - * to the platform as it might have a combination of integrated and external - * caches. Such alignment ensures that two maiboxes do not sit on the same cache - * line at any cache level. They could belong to different cpus/clusters & - * get written while being protected by different locks causing corruption of - * a valid mailbox address. - ******************************************************************************/ -#define CACHE_WRITEBACK_SHIFT 6 -#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) - -#define PLAT_GIC_BASE (0xFFFC0000) -#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) -#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) -#define PLAT_GICR_BASE 0 - -/******************************************************************************* - * UART related constants - ******************************************************************************/ -#define PLAT_UART0_BASE (0xFFC02000) -#define PLAT_UART1_BASE (0xFFC02100) - -#define CRASH_CONSOLE_BASE PLAT_UART0_BASE - -#define PLAT_BAUDRATE (115200) -#define PLAT_UART_CLOCK (100000000) - -/******************************************************************************* - * System counter frequency related constants - ******************************************************************************/ -#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) -#define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400) - -#define PLAT_INTEL_S10_GICD_BASE PLAT_GICD_BASE -#define PLAT_INTEL_S10_GICC_BASE PLAT_GICC_BASE - -/* - * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 - * terminology. On a GICv2 system or mode, the lists will be merged and treated - * as Group 0 interrupts. - */ -#define PLAT_INTEL_S10_G1S_IRQ_PROPS(grp) \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE) - -#define PLAT_INTEL_S10_G0_IRQ_PROPS(grp) - -#define MAX_IO_HANDLES 4 -#define MAX_IO_DEVICES 4 -#define MAX_IO_BLOCK_DEVICES 2 - - -#endif /* __PLATFORM_DEF_H__ */ - diff --git a/plat/intel/soc/stratix10/soc/s10_clock_manager.c b/plat/intel/soc/stratix10/soc/s10_clock_manager.c index dc90076..b4d0573 100644 --- a/plat/intel/soc/stratix10/soc/s10_clock_manager.c +++ b/plat/intel/soc/stratix10/soc/s10_clock_manager.c @@ -10,7 +10,6 @@ #include #include #include -#include #include "s10_clock_manager.h" #include "s10_handoff.h" diff --git a/plat/intel/soc/stratix10/soc/s10_handoff.c b/plat/intel/soc/stratix10/soc/s10_handoff.c index 55516c0..1a4d5c3 100644 --- a/plat/intel/soc/stratix10/soc/s10_handoff.c +++ b/plat/intel/soc/stratix10/soc/s10_handoff.c @@ -13,7 +13,6 @@ #include #include #include -#include #include "s10_handoff.h" diff --git a/plat/intel/soc/stratix10/soc/s10_reset_manager.c b/plat/intel/soc/stratix10/soc/s10_reset_manager.c index 8b58db6..8b7420b 100644 --- a/plat/intel/soc/stratix10/soc/s10_reset_manager.c +++ b/plat/intel/soc/stratix10/soc/s10_reset_manager.c @@ -14,7 +14,6 @@ #include #include #include -#include #include "s10_reset_manager.h" void deassert_peripheral_reset(void) diff --git a/plat/intel/soc/stratix10/stratix10_image_load.c b/plat/intel/soc/stratix10/stratix10_image_load.c deleted file mode 100644 index 67c02bc..0000000 --- a/plat/intel/soc/stratix10/stratix10_image_load.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -/******************************************************************************* - * This function flushes the data structures so that they are visible - * in memory for the next BL image. - ******************************************************************************/ -void plat_flush_next_bl_params(void) -{ - flush_bl_params_desc(); -} - -/******************************************************************************* - * This function returns the list of loadable images. - ******************************************************************************/ -bl_load_info_t *plat_get_bl_image_load_info(void) -{ - return get_bl_load_info_from_mem_params_desc(); -} - -/******************************************************************************* - * This function returns the list of executable images. - ******************************************************************************/ -bl_params_t *plat_get_next_bl_params(void) -{ - return get_next_bl_params_from_mem_params_desc(); -}