diff --git a/Makefile b/Makefile
index ae9b41b..97fa0ac 100644
--- a/Makefile
+++ b/Makefile
@@ -97,6 +97,8 @@
 # Flag to introduce an infinite loop in BL1 just before it exits into the next
 # image. This is meant to help debugging the post-BL2 phase.
 SPIN_ON_BL1_EXIT		:= 0
+# Build PL011 UART driver in minimal generic UART mode
+PL011_GENERIC_UART		:= 0
 
 
 ################################################################################
@@ -371,6 +373,7 @@
 $(eval $(call assert_boolean,ERROR_DEPRECATED))
 $(eval $(call assert_boolean,ENABLE_PLAT_COMPAT))
 $(eval $(call assert_boolean,SPIN_ON_BL1_EXIT))
+$(eval $(call assert_boolean,PL011_GENERIC_UART))
 
 
 ################################################################################
@@ -399,6 +402,7 @@
 ifdef EL3_PAYLOAD_BASE
 $(eval $(call add_define,EL3_PAYLOAD_BASE))
 endif
+$(eval $(call add_define,PL011_GENERIC_UART))
 
 
 ################################################################################
diff --git a/docs/user-guide.md b/docs/user-guide.md
index 716ed7d..18f2204 100644
--- a/docs/user-guide.md
+++ b/docs/user-guide.md
@@ -391,6 +391,12 @@
     payload. Please refer to the "Booting an EL3 payload" section for more
     details.
 
+*   `PL011_GENERIC_UART`: Boolean option to indicate the PL011 driver that
+    the underlying hardware is not a full PL011 UART but a minimally compliant
+    generic UART, which is a subset of the PL011. The driver will not access
+    any register that is not part of the SBSA generic UART specification.
+    Default value is 0 (a full PL011 compliant UART is present).
+
 #### ARM development platform specific build options
 
 *   `ARM_TSP_RAM_LOCATION`: location of the TSP binary. Options:
diff --git a/drivers/arm/pl011/pl011_console.S b/drivers/arm/pl011/pl011_console.S
index ea41e5d..47608da 100644
--- a/drivers/arm/pl011/pl011_console.S
+++ b/drivers/arm/pl011/pl011_console.S
@@ -60,6 +60,7 @@
 func console_core_init
 	/* Check the input base address */
 	cbz	x0, core_init_fail
+#if !PL011_GENERIC_UART
 	/* Check baud rate and uart clock for sanity */
 	cbz	w1, core_init_fail
 	cbz	w2, core_init_fail
@@ -82,6 +83,7 @@
 	/* Enable tx, rx, and uart overall */
 	mov	w1, #(PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN)
 	str	w1, [x0, #UARTCR]
+#endif
 	mov	w0, #1
 	ret
 core_init_fail:
diff --git a/include/drivers/arm/pl011.h b/include/drivers/arm/pl011.h
index 7c4df62..d5ea890 100644
--- a/include/drivers/arm/pl011.h
+++ b/include/drivers/arm/pl011.h
@@ -36,17 +36,21 @@
 #define UARTRSR                   0x004
 #define UARTECR                   0x004
 #define UARTFR                    0x018
+#define UARTIMSC                  0x038
+#define UARTRIS                   0x03C
+#define UARTICR                   0x044
+
+/* PL011 registers (out of the SBSA specification) */
+#if !PL011_GENERIC_UART
 #define UARTILPR                  0x020
 #define UARTIBRD                  0x024
 #define UARTFBRD                  0x028
 #define UARTLCR_H                 0x02C
 #define UARTCR                    0x030
 #define UARTIFLS                  0x034
-#define UARTIMSC                  0x038
-#define UARTRIS                   0x03C
 #define UARTMIS                   0x040
-#define UARTICR                   0x044
 #define UARTDMACR                 0x048
+#endif /* !PL011_GENERIC_UART */
 
 /* Data status bits */
 #define UART_DATA_ERROR_MASK      0x0F00
@@ -69,6 +73,7 @@
 #define PL011_UARTFR_RXFE_BIT	4	/* Receive FIFO empty bit in UARTFR register */
 
 /* Control reg bits */
+#if !PL011_GENERIC_UART
 #define PL011_UARTCR_CTSEN        (1 << 15)	/* CTS hardware flow control enable */
 #define PL011_UARTCR_RTSEN        (1 << 14)	/* RTS hardware flow control enable */
 #define PL011_UARTCR_RTS          (1 << 11)	/* Request to send */
@@ -95,4 +100,6 @@
 #define PL011_UARTLCR_H_PEN       (1 << 1)	/* Parity Enable */
 #define PL011_UARTLCR_H_BRK       (1 << 0)	/* Send break */
 
+#endif /* !PL011_GENERIC_UART */
+
 #endif	/* __PL011_H__ */