diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index e1c89bf..493e07e 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -217,6 +217,18 @@ - ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. +- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 + CPU. This needs to be enabled only for revision <= r3p0 of the CPU. + +- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 + CPU. This needs to be enabled only for revision <= r3p0 of the CPU. + +- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 + CPU. This needs to be enabled only for revision <= r3p0 of the CPU. + +- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 + CPU. This needs to be enabled only for revision <= r3p0 of the CPU. + DSU Errata Workarounds ---------------------- diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index c3ce1c4..c173706 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h @@ -87,12 +87,13 @@ * TLB maintenance accessor prototypes ******************************************************************************/ -#if ERRATA_A57_813419 +#if ERRATA_A57_813419 || ERRATA_A76_1286807 /* * Define function for TLBI instruction with type specifier that implements - * the workaround for errata 813419 of Cortex-A57. + * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of + * Cortex-A76. */ -#define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(_type)\ +#define DEFINE_TLBIOP_ERRATA_TYPE_FUNC(_type)\ static inline void tlbi ## _type(void) \ { \ __asm__("tlbi " #_type "\n" \ @@ -102,9 +103,10 @@ /* * Define function for TLBI instruction with register parameter that implements - * the workaround for errata 813419 of Cortex-A57. + * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of + * Cortex-A76. */ -#define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(_type) \ +#define DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(_type) \ static inline void tlbi ## _type(uint64_t v) \ { \ __asm__("tlbi " #_type ", %0\n" \ @@ -125,27 +127,51 @@ } #endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */ +#if ERRATA_A57_813419 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) -#if ERRATA_A57_813419 -DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3) -DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3is) +DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3) +DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is) +DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) +#elif ERRATA_A76_1286807 +DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1) +DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1is) +DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2) +DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2is) +DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3) +DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is) +DEFINE_TLBIOP_ERRATA_TYPE_FUNC(vmalle1) #else +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3) DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is) -#endif DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) +#endif +#if ERRATA_A57_813419 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) -#if ERRATA_A57_813419 -DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vae3is) -DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vale3is) +DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is) +DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is) +#elif ERRATA_A76_1286807 +DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaae1is) +DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaale1is) +DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae2is) +DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale2is) +DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is) +DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is) #else +DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) +DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) +DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) +DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is) DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is) #endif diff --git a/include/arch/aarch64/asm_macros.S b/include/arch/aarch64/asm_macros.S index 387be4c..9b12185 100644 --- a/include/arch/aarch64/asm_macros.S +++ b/include/arch/aarch64/asm_macros.S @@ -12,9 +12,9 @@ /* * TLBI instruction with type specifier that implements the workaround for - * errata 813419 of Cortex-A57. + * errata 813419 of Cortex-A57 or errata 1286807 of Cortex-A76. */ -#if ERRATA_A57_813419 +#if ERRATA_A57_813419 || ERRATA_A76_1286807 #define TLB_INVALIDATE(_type) \ tlbi _type; \ dsb ish; \ diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h index c2af8ca..7dc7e06 100644 --- a/include/lib/cpus/aarch64/cortex_a76.h +++ b/include/lib/cpus/aarch64/cortex_a76.h @@ -19,6 +19,7 @@ #define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 #define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24) +#define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51) /******************************************************************************* * CPU Auxiliary Control register specific definitions. @@ -27,10 +28,17 @@ #define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6) +#define CORTEX_A76_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) + #define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16) +#define CORTEX_A76_CPUACTLR3_EL1 S3_0_C15_C1_2 + +#define CORTEX_A76_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) + + /* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */ #define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1) diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S index 6fe6afe..b48283c 100644 --- a/lib/cpus/aarch64/cortex_a76.S +++ b/lib/cpus/aarch64/cortex_a76.S @@ -213,7 +213,7 @@ isb 1: ret x17 - endfunc errata_a76_1073348_wa +endfunc errata_a76_1073348_wa func check_errata_1073348 mov x1, #0x10 @@ -276,6 +276,117 @@ b cpu_rev_var_ls endfunc check_errata_1220197 + /* -------------------------------------------------- + * Errata Workaround for Cortex A76 Errata #1257314. + * This applies only to revision <= r3p0 of Cortex A76. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a76_1257314_wa + /* + * Compare x0 against revision r3p0 + */ + mov x17, x30 + bl check_errata_1257314 + cbz x0, 1f + mrs x1, CORTEX_A76_CPUACTLR3_EL1 + orr x1, x1, CORTEX_A76_CPUACTLR3_EL1_BIT_10 + msr CORTEX_A76_CPUACTLR3_EL1, x1 + isb +1: + ret x17 +endfunc errata_a76_1257314_wa + +func check_errata_1257314 + mov x1, #0x30 + b cpu_rev_var_ls +endfunc check_errata_1257314 + + /* -------------------------------------------------- + * Errata Workaround for Cortex A76 Errata #1262888. + * This applies only to revision <= r3p0 of Cortex A76. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a76_1262888_wa + /* + * Compare x0 against revision r3p0 + */ + mov x17, x30 + bl check_errata_1262888 + cbz x0, 1f + mrs x1, CORTEX_A76_CPUECTLR_EL1 + orr x1, x1, CORTEX_A76_CPUECTLR_EL1_BIT_51 + msr CORTEX_A76_CPUECTLR_EL1, x1 + isb +1: + ret x17 +endfunc errata_a76_1262888_wa + +func check_errata_1262888 + mov x1, #0x30 + b cpu_rev_var_ls +endfunc check_errata_1262888 + + /* -------------------------------------------------- + * Errata Workaround for Cortex A76 Errata #1275112 + * and Errata #1262606. + * This applies only to revision <= r3p0 of Cortex A76. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a76_1275112_1262606_wa + /* + * Compare x0 against revision r3p0 + */ + mov x17, x30 + /* + * Since both errata #1275112 and #1262606 have the same check, we can + * invoke any one of them for the check here. + */ + bl check_errata_1275112 + cbz x0, 1f + mrs x1, CORTEX_A76_CPUACTLR_EL1 + orr x1, x1, CORTEX_A76_CPUACTLR_EL1_BIT_13 + msr CORTEX_A76_CPUACTLR_EL1, x1 + isb +1: + ret x17 +endfunc errata_a76_1275112_1262606_wa + +func check_errata_1262606 + mov x1, #0x30 + b cpu_rev_var_ls +endfunc check_errata_1262606 + +func check_errata_1275112 + mov x1, #0x30 + b cpu_rev_var_ls +endfunc check_errata_1275112 + + /* --------------------------------------------------- + * Errata Workaround for Cortex A76 Errata #1286807. + * This applies only to revision <= r3p0 of Cortex A76. + * Due to the nature of the errata it is applied unconditionally + * when built in, report it as applicable in this case + * --------------------------------------------------- + */ +func check_errata_1286807 +#if ERRATA_A76_1286807 + mov x0, #ERRATA_APPLIES + ret +#else + mov x1, #0x30 + b cpu_rev_var_ls +#endif +endfunc check_errata_1286807 + func check_errata_cve_2018_3639 #if WORKAROUND_CVE_2018_3639 mov x0, #ERRATA_APPLIES @@ -318,6 +429,21 @@ bl errata_a76_1220197_wa #endif +#if ERRATA_A76_1257314 + mov x0, x18 + bl errata_a76_1257314_wa +#endif + +#if ERRATA_A76_1262606 || ERRATA_A76_1275112 + mov x0, x18 + bl errata_a76_1275112_1262606_wa +#endif + +#if ERRATA_A76_1262888 + mov x0, x18 + bl errata_a76_1262888_wa +#endif + #if WORKAROUND_CVE_2018_3639 /* If the PE implements SSBS, we don't need the dynamic workaround */ mrs x0, id_aa64pfr1_el1 @@ -393,6 +519,11 @@ report_errata ERRATA_A76_1073348, cortex_a76, 1073348 report_errata ERRATA_A76_1130799, cortex_a76, 1130799 report_errata ERRATA_A76_1220197, cortex_a76, 1220197 + report_errata ERRATA_A76_1257314, cortex_a76, 1257314 + report_errata ERRATA_A76_1262606, cortex_a76, 1262606 + report_errata ERRATA_A76_1262888, cortex_a76, 1262888 + report_errata ERRATA_A76_1275112, cortex_a76, 1275112 + report_errata ERRATA_A76_1286807, cortex_a76, 1286807 report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639 report_errata ERRATA_DSU_798953, cortex_a76, dsu_798953 report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 4deb262..e45d79d 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -210,6 +210,26 @@ # only to revision <= r2p0 of the Cortex A76 cpu. ERRATA_A76_1220197 ?=0 +# Flag to apply erratum 1257314 workaround during reset. This erratum applies +# only to revision <= r3p0 of the Cortex A76 cpu. +ERRATA_A76_1257314 ?=0 + +# Flag to apply erratum 1262606 workaround during reset. This erratum applies +# only to revision <= r3p0 of the Cortex A76 cpu. +ERRATA_A76_1262606 ?=0 + +# Flag to apply erratum 1262888 workaround during reset. This erratum applies +# only to revision <= r3p0 of the Cortex A76 cpu. +ERRATA_A76_1262888 ?=0 + +# Flag to apply erratum 1275112 workaround during reset. This erratum applies +# only to revision <= r3p0 of the Cortex A76 cpu. +ERRATA_A76_1275112 ?=0 + +# Flag to apply erratum 1286807 workaround during reset. This erratum applies +# only to revision <= r3p0 of the Cortex A76 cpu. +ERRATA_A76_1286807 ?=0 + # Flag to apply T32 CLREX workaround during reset. This erratum applies # only to r0p0 and r1p0 of the Neoverse N1 cpu. ERRATA_N1_1043202 ?=1 @@ -375,6 +395,26 @@ $(eval $(call assert_boolean,ERRATA_A76_1220197)) $(eval $(call add_define,ERRATA_A76_1220197)) +# Process ERRATA_A76_1257314 flag +$(eval $(call assert_boolean,ERRATA_A76_1257314)) +$(eval $(call add_define,ERRATA_A76_1257314)) + +# Process ERRATA_A76_1262606 flag +$(eval $(call assert_boolean,ERRATA_A76_1262606)) +$(eval $(call add_define,ERRATA_A76_1262606)) + +# Process ERRATA_A76_1262888 flag +$(eval $(call assert_boolean,ERRATA_A76_1262888)) +$(eval $(call add_define,ERRATA_A76_1262888)) + +# Process ERRATA_A76_1275112 flag +$(eval $(call assert_boolean,ERRATA_A76_1275112)) +$(eval $(call add_define,ERRATA_A76_1275112)) + +# Process ERRATA_A76_1286807 flag +$(eval $(call assert_boolean,ERRATA_A76_1286807)) +$(eval $(call add_define,ERRATA_A76_1286807)) + # Process ERRATA_N1_1043202 flag $(eval $(call assert_boolean,ERRATA_N1_1043202)) $(eval $(call add_define,ERRATA_N1_1043202))