diff --git a/plat/arm/board/arm_fpga/fpga_def.h b/plat/arm/board/arm_fpga/fpga_def.h
index 0f817fe..56ee166 100644
--- a/plat/arm/board/arm_fpga/fpga_def.h
+++ b/plat/arm/board/arm_fpga/fpga_def.h
@@ -10,12 +10,17 @@
 #define FPGA_DEF_H
 
 /*
- * The initial FPGA image configures a system with 2 clusters, 1 core in each,
- * and multi-threading is unimplemented.
+ * These are set to large values to account for images describing systems with
+ * larger cluster configurations.
+ *
+ * For cases where the number of clusters, cores or threads is smaller than a
+ * maximum value below, this does not affect the PSCI functionality as any PEs
+ * that are present will still be indexed appropriately regardless of any empty
+ * entries in the array used to represent the topology.
  */
 #define FPGA_MAX_CLUSTER_COUNT			2
-#define FPGA_MAX_CPUS_PER_CLUSTER		1
-#define FPGA_MAX_PE_PER_CPU			1
+#define FPGA_MAX_CPUS_PER_CLUSTER		8
+#define FPGA_MAX_PE_PER_CPU			4
 
 #define FPGA_PRIMARY_CPU			0x0
 
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index 8ce0ae0..194c595 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -9,6 +9,10 @@
 $(error "This is a BL31-only port; RESET_TO_BL31 must be enabled")
 endif
 
+ifeq (${ENABLE_PIE}, 1)
+override SEPARATE_CODE_AND_RODATA := 1
+endif
+
 CTX_INCLUDE_AARCH32_REGS := 0
 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
 $(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")