diff --git a/drivers/marvell/mci.c b/drivers/marvell/mci.c
index bd62a30..2b54700 100644
--- a/drivers/marvell/mci.c
+++ b/drivers/marvell/mci.c
@@ -571,21 +571,21 @@
 
 	debug_enter();
 	/* ID assignment (assigning global ID offset to CP) */
-	mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(0),
+	mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index),
 			  MCI_DID_GLOBAL_ASSIGN_REQ_MCI_LOCAL_ID(2) |
 			  MCI_DID_GLOBAL_ASSIGN_REQ_MCI_COUNT(2) |
 			  MCI_DID_GLOBAL_ASSIGN_REQ_HOPS_NUM(2));
-	mci_mmio_write_32(MCI_ACCESS_CMD_REG(0),
+	mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
 			  MCI_INDIRECT_REG_CTRL_ADDR(
 				MCI_DID_GLOBAL_ASSIGNMENT_REQUEST_REG) |
 			  MCI_INDIRECT_CTRL_ASSIGN_CMD);
 	ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
 
 	/* Assigning dest. ID=3 to all transactions entering from AXI at AP */
-	mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(0),
+	mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index),
 			  MCI_HB_CTRL_WIN0_DEST_VALID_FLAG(1) |
 			  MCI_HB_CTRL_WIN0_DEST_ID(3));
-	mci_mmio_write_32(MCI_ACCESS_CMD_REG(0),
+	mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
 			  MCI_INDIRECT_REG_CTRL_ADDR(
 				MCI_HB_CTRL_WIN0_DESTINATION_REG_NUM) |
 			  MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB) |
@@ -593,10 +593,10 @@
 	ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
 
 	/* Assigning dest. ID=1 to all transactions entering from AXI at CP */
-	mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(0),
+	mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index),
 			  MCI_HB_CTRL_WIN0_DEST_VALID_FLAG(1) |
 			  MCI_HB_CTRL_WIN0_DEST_ID(1));
-	mci_mmio_write_32(MCI_ACCESS_CMD_REG(0),
+	mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
 			  MCI_INDIRECT_REG_CTRL_ADDR(
 				MCI_HB_CTRL_WIN0_DESTINATION_REG_NUM) |
 			  MCI_INDIRECT_CTRL_HOPID(GID_IHB_EXT) |
@@ -607,8 +607,8 @@
 	 * This will lead to get match for any AXI address
 	 * and receive destination ID=3
 	 */
-	mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(0), 0xffffffff);
-	mci_mmio_write_32(MCI_ACCESS_CMD_REG(0),
+	mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), 0xffffffff);
+	mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
 			  MCI_INDIRECT_REG_CTRL_ADDR(
 				MCI_HB_CTRL_WIN0_ADDRESS_MASK_REG_NUM) |
 			  MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB) |
@@ -619,8 +619,8 @@
 	 * This will lead to get match for any AXI address
 	 * and receive destination ID=1
 	 */
-	mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(0), 0xffffffff);
-	mci_mmio_write_32(MCI_ACCESS_CMD_REG(0),
+	mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), 0xffffffff);
+	mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
 			  MCI_INDIRECT_REG_CTRL_ADDR(
 				MCI_HB_CTRL_WIN0_ADDRESS_MASK_REG_NUM) |
 			  MCI_INDIRECT_CTRL_HOPID(GID_IHB_EXT) |
@@ -653,7 +653,7 @@
 	 * performed by BootROM.
 	 */
 	debug_enter();
-	mci_mmio_write_32(MCI_ACCESS_CMD_REG(0),
+	mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
 			  MCI_INDIRECT_REG_CTRL_ADDR(
 				MCI_HB_CTRL_WIN0_DESTINATION_REG_NUM) |
 			  MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB) |
@@ -697,7 +697,8 @@
 	 * wasn't already enabled in bootrom.
 	 */
 	if (mci_simulatenous_trans_missing(mci_index)) {
-		VERBOSE("Enabling MCI simultaneous transaction\n");
+		VERBOSE("Enabling MCI simultaneous transaction for mci%d\n",
+		       mci_index);
 		/* set MCI to support read/write transactions
 		 * to arrive at the same time
 		 */
diff --git a/plat/marvell/armada/a8k/common/plat_bl31_setup.c b/plat/marvell/armada/a8k/common/plat_bl31_setup.c
index 90e6672..621f43c 100644
--- a/plat/marvell/armada/a8k/common/plat_bl31_setup.c
+++ b/plat/marvell/armada/a8k/common/plat_bl31_setup.c
@@ -116,11 +116,8 @@
 		marvell_bl31_plat_arch_setup();
 
 	for (cp = 0; cp < CP_COUNT; cp++) {
-		if (cp >= 1) {
-			mci_link_tune(MVEBU_MCI0);
+		if (cp >= 1)
 			update_cp110_default_win(cp);
-		}
-
 
 		cp110_init(MVEBU_CP_REGS_BASE(cp),
 			   STREAM_ID_BASE + (cp * MAX_STREAM_ID_PER_CP));
@@ -134,6 +131,9 @@
 	 */
 	init_io_win(MVEBU_AP0);
 
+	for (cp = 1; cp < CP_COUNT; cp++)
+		mci_link_tune(cp - 1);
+
 	/* initialize IPC between MSS and ATF */
 	if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM ||
 	    mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE)