diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 591f2f8..264d0c6 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -227,6 +227,12 @@ - ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. +- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 + CPU. This needs to be enabled only for revision <= r4p0 of the CPU. + +- ``ERRATA_A76_1800710``: This applies errata 1800710 workaround to Cortex-A76 + CPU. This needs to be enabled only for revision <= r4p0 of the CPU. + For Cortex-A78, the following errata build flags are defined : - ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h index 7dc7e06..b522e8e 100644 --- a/include/lib/cpus/aarch64/cortex_a76.h +++ b/include/lib/cpus/aarch64/cortex_a76.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,6 +20,7 @@ #define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24) #define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51) +#define CORTEX_A76_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) /******************************************************************************* * CPU Auxiliary Control register specific definitions. @@ -32,6 +33,8 @@ #define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) + #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16) #define CORTEX_A76_CPUACTLR3_EL1 S3_0_C15_C1_2 diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S index baefa46..10011f7 100644 --- a/lib/cpus/aarch64/cortex_a76.S +++ b/lib/cpus/aarch64/cortex_a76.S @@ -392,6 +392,62 @@ #endif endfunc check_errata_1286807 + /* -------------------------------------------------- + * Errata workaround for Cortex A76 Errata #1791580. + * This applies to revisions <= r4p0 of Cortex A76. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a76_1791580_wa + /* Compare x0 against revision r4p0 */ + mov x17, x30 + bl check_errata_1791580 + cbz x0, 1f + mrs x1, CORTEX_A76_CPUACTLR2_EL1 + orr x1, x1, CORTEX_A76_CPUACTLR2_EL1_BIT_2 + msr CORTEX_A76_CPUACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_a76_1791580_wa + +func check_errata_1791580 + /* Applies to everything <=r4p0. */ + mov x1, #0x40 + b cpu_rev_var_ls +endfunc check_errata_1791580 + + /* -------------------------------------------------- + * Errata Workaround for Cortex A76 Errata #1800710. + * This applies to revision <= r4p0 of Cortex A76. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a76_1800710_wa + /* Compare x0 against revision <= r4p0 */ + mov x17, x30 + bl check_errata_1800710 + cbz x0, 1f + + /* Disable allocation of splintered pages in the L2 TLB */ + mrs x1, CORTEX_A76_CPUECTLR_EL1 + orr x1, x1, CORTEX_A76_CPUECTLR_EL1_BIT_53 + msr CORTEX_A76_CPUECTLR_EL1, x1 + isb +1: + ret x17 +endfunc errata_a76_1800710_wa + +func check_errata_1800710 + /* Applies to everything <= r4p0 */ + mov x1, #0x40 + b cpu_rev_var_ls +endfunc check_errata_1800710 + func check_errata_cve_2018_3639 #if WORKAROUND_CVE_2018_3639 mov x0, #ERRATA_APPLIES @@ -449,6 +505,16 @@ bl errata_a76_1262888_wa #endif +#if ERRATA_A76_1791580 + mov x0, x18 + bl errata_a76_1791580_wa +#endif + +#if ERRATA_A76_1800710 + mov x0, x18 + bl errata_a76_1800710_wa +#endif + #if WORKAROUND_CVE_2018_3639 /* If the PE implements SSBS, we don't need the dynamic workaround */ mrs x0, id_aa64pfr1_el1 @@ -529,6 +595,8 @@ report_errata ERRATA_A76_1262888, cortex_a76, 1262888 report_errata ERRATA_A76_1275112, cortex_a76, 1275112 report_errata ERRATA_A76_1286807, cortex_a76, 1286807 + report_errata ERRATA_A76_1791580, cortex_a76, 1791580 + report_errata ERRATA_A76_1800710, cortex_a76, 1800710 report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639 report_errata ERRATA_DSU_798953, cortex_a76, dsu_798953 report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 1bc082d..e809000 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -250,6 +250,14 @@ # only to revision <= r3p0 of the Cortex A76 cpu. ERRATA_A76_1286807 ?=0 +# Flag to apply erratum 1791580 workaround during reset. This erratum applies +# only to revision <= r4p0 of the Cortex A76 cpu. +ERRATA_A76_1791580 ?=0 + +# Flag to apply erratum 1800710 workaround during reset. This erratum applies +# only to revision <= r4p0 of the Cortex A76 cpu. +ERRATA_A76_1800710 ?=0 + # Flag to apply erratum 1688305 workaround during reset. This erratum applies # to revisions r0p0 - r1p0 of the A78 cpu. ERRATA_A78_1688305 ?=0 @@ -487,6 +495,14 @@ $(eval $(call assert_boolean,ERRATA_A76_1286807)) $(eval $(call add_define,ERRATA_A76_1286807)) +# Process ERRATA_A76_1791580 flag +$(eval $(call assert_boolean,ERRATA_A76_1791580)) +$(eval $(call add_define,ERRATA_A76_1791580)) + +# Process ERRATA_A76_1800710 flag +$(eval $(call assert_boolean,ERRATA_A76_1800710)) +$(eval $(call add_define,ERRATA_A76_1800710)) + # Process ERRATA_A78_1688305 flag $(eval $(call assert_boolean,ERRATA_A78_1688305)) $(eval $(call add_define,ERRATA_A78_1688305))