diff --git a/Makefile b/Makefile index af2ddd4..9b15c21 100644 --- a/Makefile +++ b/Makefile @@ -138,9 +138,10 @@ include plat/${PLAT}/platform.mk -# By default all CPU errata workarounds are disabled. This can be +# Include the CPU specific operations makefile. By default all CPU errata +# workarounds and CPU specifc optimisations are disabled. This can be # overridden by the platform. -include lib/cpus/cpu-errata.mk +include lib/cpus/cpu-ops.mk ifdef BL1_SOURCES NEED_BL1 := yes diff --git a/docs/cpu-errata-workarounds.md b/docs/cpu-errata-workarounds.md deleted file mode 100644 index 09f7c72..0000000 --- a/docs/cpu-errata-workarounds.md +++ /dev/null @@ -1,38 +0,0 @@ -ARM CPU Errata Workarounds -========================== - -ARM Trusted Firmware exports a series of build flags which control the -errata workarounds that are applied to each CPU by the reset handler. The -errata details can be found in the CPU specifc errata documents published -by ARM. The errata workarounds are implemented for a particular revision -or a set of processor revisions. This is checked by reset handler at runtime. -Each errata workaround is identified by its `ID` as specified in the processor's -errata notice document. The format of the define used to enable/disable the -errata is `ERRATA__` where the `Processor name` -is either `A57` for the `Cortex_A57` CPU or `A53` for `Cortex_A53` CPU. - -All workarounds are disabled by default. The platform is reponsible for -enabling these workarounds according to its requirement by defining the -errata workaround build flags in the platform specific makefile. In case -these workarounds are enabled for the wrong CPU revision then the errata -workaround is not applied. In the DEBUG build, this is indicated by -printing a warning to the crash console. - -In the current implementation, a platform which has more than 1 variant -with different revisions of a processor has no runtime mechanism available -for it to specify which errata workarounds should be enabled or not. - -The value of the build flags are 0 by default, that is, disabled. Any other -value will enable it. - -For Cortex-A57, following errata build flags are defined : - -* `ERRATA_A57_806969`: This applies errata 806969 workaround to Cortex-A57 - CPU. This needs to be enabled only for revision r0p0 of the CPU. - -* `ERRATA_A57_813420`: This applies errata 813420 workaround to Cortex-A57 - CPU. This needs to be enabled only for revision r0p0 of the CPU. - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -_Copyright (c) 2014, ARM Limited and Contributors. All rights reserved._ diff --git a/docs/cpu-specific-build-macros.md b/docs/cpu-specific-build-macros.md new file mode 100644 index 0000000..246381a --- /dev/null +++ b/docs/cpu-specific-build-macros.md @@ -0,0 +1,69 @@ +ARM CPU Specific Build Macros +============================= + +Contents +-------- + +1. Introduction +2. CPU Errata Workarounds +3. CPU Specific optimizations + +1. Introduction +---------------- + +This document describes the various build options present in the CPU specific +operations framework to enable errata workarounds and to enable optimizations +for a specific CPU on a platform. + +2. CPU Errata Workarounds +-------------------------- + +ARM Trusted Firmware exports a series of build flags which control the +errata workarounds that are applied to each CPU by the reset handler. The +errata details can be found in the CPU specifc errata documents published +by ARM. The errata workarounds are implemented for a particular revision +or a set of processor revisions. This is checked by reset handler at runtime. +Each errata workaround is identified by its `ID` as specified in the processor's +errata notice document. The format of the define used to enable/disable the +errata is `ERRATA__` where the `Processor name` +is either `A57` for the `Cortex_A57` CPU or `A53` for `Cortex_A53` CPU. + +All workarounds are disabled by default. The platform is reponsible for +enabling these workarounds according to its requirement by defining the +errata workaround build flags in the platform specific makefile. In case +these workarounds are enabled for the wrong CPU revision then the errata +workaround is not applied. In the DEBUG build, this is indicated by +printing a warning to the crash console. + +In the current implementation, a platform which has more than 1 variant +with different revisions of a processor has no runtime mechanism available +for it to specify which errata workarounds should be enabled or not. + +The value of the build flags are 0 by default, that is, disabled. Any other +value will enable it. + +For Cortex-A57, following errata build flags are defined : + +* `ERRATA_A57_806969`: This applies errata 806969 workaround to Cortex-A57 + CPU. This needs to be enabled only for revision r0p0 of the CPU. + +* `ERRATA_A57_813420`: This applies errata 813420 workaround to Cortex-A57 + CPU. This needs to be enabled only for revision r0p0 of the CPU. + +3. CPU Specific optimizations +------------------------------ + +This section describes some of the optimizations allowed by the CPU micro +architecture that can be enabled by the platform as desired. + +* `SKIP_A57_L1_FLUSH_PWR_DWN`: This flag enables an optimization in the + Cortex-A57 cluster power down sequence by not flushing the Level 1 data + cache. The L1 data cache and the L2 unified cache are inclusive. A flush + of the L2 by set/way flushes any dirty lines from the L1 as well. This + is a known safe deviation from the Cortex-A57 TRM defined power down + sequence. Each Cortex-A57 based platform must make its own decision on + whether to use the optimization. + +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2014, ARM Limited and Contributors. All rights reserved._ diff --git a/docs/firmware-design.md b/docs/firmware-design.md index fde61da..bc075da 100644 --- a/docs/firmware-design.md +++ b/docs/firmware-design.md @@ -982,9 +982,10 @@ The CPU specific operations framework scales to accommodate a large number of different CPUs during power down and reset handling. The platform can specify +any CPU optimization it wants to enable for each CPU. It can also specify the CPU errata workarounds to be applied for each CPU type during reset handling by defining CPU errata compile time macros. Details on these macros -can be found in the [cpu-errata-workarounds.md][ERRW] file. +can be found in the [cpu-specific-build-macros.md][CPUBM] file. The CPU specific operations framework depends on the `cpu_ops` structure which needs to be exported for each type of CPU in the platform. It is defined in @@ -1485,4 +1486,4 @@ [User Guide]: ./user-guide.md [Porting Guide]: ./porting-guide.md [INTRG]: ./interrupt-framework-design.md -[ERRW]: ./cpu-errata-workarounds.md +[CPUBM]: ./cpu-specific-build-macros.md.md diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index c2e11bd..dab16d7 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -222,13 +222,14 @@ */ bl cortex_a57_disable_l2_prefetch +#if !SKIP_A57_L1_FLUSH_PWR_DWN /* ------------------------------------------------- * Flush the L1 caches. * ------------------------------------------------- */ mov x0, #DCCISW bl dcsw_op_level1 - +#endif /* --------------------------------------------- * Disable the optional ACP. * --------------------------------------------- diff --git a/lib/cpus/cpu-errata.mk b/lib/cpus/cpu-errata.mk deleted file mode 100644 index 79f0156..0000000 --- a/lib/cpus/cpu-errata.mk +++ /dev/null @@ -1,48 +0,0 @@ -# -# Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# Neither the name of ARM nor the names of its contributors may be used -# to endorse or promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -# CPU Errata Build flags. These should be enabled by the -# platform if the errata needs to be applied. - -# Flag to apply errata 806969 during reset. This errata applies only to -# revision r0p0 of the Cortex A57 cpu. -ERRATA_A57_806969 ?=0 - -# Flag to apply errata 813420 during reset. This errata applies only to -# revision r0p0 of the Cortex A57 cpu. -ERRATA_A57_813420 ?=0 - -# Process ERRATA_A57_806969 flag -$(eval $(call assert_boolean,ERRATA_A57_806969)) -$(eval $(call add_define,ERRATA_A57_806969)) - -# Process ERRATA_A57_813420 flag -$(eval $(call assert_boolean,ERRATA_A57_813420)) -$(eval $(call add_define,ERRATA_A57_813420)) diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk new file mode 100644 index 0000000..1c5512e --- /dev/null +++ b/lib/cpus/cpu-ops.mk @@ -0,0 +1,57 @@ +# +# Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# Cortex A57 specific optimisation to skip L1 cache flush when +# cluster is powered down. +SKIP_A57_L1_FLUSH_PWR_DWN ?=0 + +# Process SKIP_A57_L1_FLUSH_PWR_DWN flag +$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN)) +$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN)) + + +# CPU Errata Build flags. These should be enabled by the +# platform if the errata needs to be applied. + +# Flag to apply errata 806969 during reset. This errata applies only to +# revision r0p0 of the Cortex A57 cpu. +ERRATA_A57_806969 ?=0 + +# Flag to apply errata 813420 during reset. This errata applies only to +# revision r0p0 of the Cortex A57 cpu. +ERRATA_A57_813420 ?=0 + +# Process ERRATA_A57_806969 flag +$(eval $(call assert_boolean,ERRATA_A57_806969)) +$(eval $(call add_define,ERRATA_A57_806969)) + +# Process ERRATA_A57_813420 flag +$(eval $(call assert_boolean,ERRATA_A57_813420)) +$(eval $(call add_define,ERRATA_A57_813420)) diff --git a/plat/juno/platform.mk b/plat/juno/platform.mk index 0637ef3..2800438 100644 --- a/plat/juno/platform.mk +++ b/plat/juno/platform.mk @@ -99,3 +99,7 @@ # Enable workarounds for selected Cortex-A57 erratas. ERRATA_A57_806969 := 1 ERRATA_A57_813420 := 1 + +# Enable option to skip L1 data cache flush during the Cortex-A57 cluster +# power down sequence +SKIP_A57_L1_FLUSH_PWR_DWN := 1