diff --git a/Makefile b/Makefile index f4b74fe..aa9b0a1 100644 --- a/Makefile +++ b/Makefile @@ -132,14 +132,20 @@ .SUFFIXES: -INCLUDES += -Ilib/include/ \ - -Idrivers/io \ - -Iinclude/${ARCH}/ \ - -Iinclude/ \ - -Iarch/system/gic \ - -Iservices/std_svc/psci \ +INCLUDES += -Iinclude/bl1 \ + -Iinclude/bl2 \ + -Iinclude/bl31 \ + -Iinclude/bl31/services \ + -Iinclude/bl32 \ + -Iinclude/bl32/payloads \ + -Iinclude/common \ + -Iinclude/drivers \ + -Iinclude/drivers/arm \ + -Iinclude/lib \ + -Iinclude/lib/aarch64 \ -Iinclude/stdlib \ -Iinclude/stdlib/sys \ + -Iservices/std_svc/psci \ -Iplat/${PLAT} \ ${PLAT_INCLUDES} \ ${SPD_INCLUDES} diff --git a/arch/aarch64/cpu/cpu_helpers.S b/arch/aarch64/cpu/cpu_helpers.S deleted file mode 100644 index 573d0b8..0000000 --- a/arch/aarch64/cpu/cpu_helpers.S +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - - .weak cpu_reset_handler - - -func cpu_reset_handler - mov x19, x30 // lr - - /* --------------------------------------------- - * As a bare minimal enable the SMP bit. - * --------------------------------------------- - */ - bl read_midr - lsr x0, x0, #MIDR_PN_SHIFT - and x0, x0, #MIDR_PN_MASK - cmp x0, #MIDR_PN_A57 - b.eq smp_setup_begin - cmp x0, #MIDR_PN_A53 - b.ne smp_setup_end -smp_setup_begin: - bl read_cpuectlr - orr x0, x0, #CPUECTLR_SMP_BIT - bl write_cpuectlr -smp_setup_end: - ret x19 diff --git a/arch/system/gic/aarch64/gic_v3_sysregs.S b/arch/system/gic/aarch64/gic_v3_sysregs.S deleted file mode 100644 index 2a96da7..0000000 --- a/arch/system/gic/aarch64/gic_v3_sysregs.S +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include - - .globl read_icc_sre_el1 - .globl read_icc_sre_el2 - .globl read_icc_sre_el3 - .globl write_icc_sre_el1 - .globl write_icc_sre_el2 - .globl write_icc_sre_el3 - .globl write_icc_pmr_el1 - - -/* - * Register definitions used by GCC for GICv3 access. - * These are defined by ARMCC, so keep them in the GCC specific code for now. - */ -#define ICC_SRE_EL1 S3_0_C12_C12_5 -#define ICC_SRE_EL2 S3_4_C12_C9_5 -#define ICC_SRE_EL3 S3_6_C12_C12_5 -#define ICC_CTLR_EL1 S3_0_C12_C12_4 -#define ICC_CTLR_EL3 S3_6_C12_C12_4 -#define ICC_PMR_EL1 S3_0_C4_C6_0 - -func read_icc_sre_el1 - mrs x0, ICC_SRE_EL1 - ret - - -func read_icc_sre_el2 - mrs x0, ICC_SRE_EL2 - ret - - -func read_icc_sre_el3 - mrs x0, ICC_SRE_EL3 - ret - - -func write_icc_sre_el1 - msr ICC_SRE_EL1, x0 - isb - ret - - -func write_icc_sre_el2 - msr ICC_SRE_EL2, x0 - isb - ret - - -func write_icc_sre_el3 - msr ICC_SRE_EL3, x0 - isb - ret - - -func write_icc_pmr_el1 - msr ICC_PMR_EL1, x0 - isb - ret diff --git a/arch/system/gic/gic.h b/arch/system/gic/gic.h deleted file mode 100644 index 3266043..0000000 --- a/arch/system/gic/gic.h +++ /dev/null @@ -1,210 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __GIC_H__ -#define __GIC_H__ - -#define MAX_SPIS 480 -#define MAX_PPIS 14 -#define MAX_SGIS 16 - -#define GRP0 0 -#define GRP1 1 -#define GIC_PRI_MASK 0xff -#define GIC_HIGHEST_SEC_PRIORITY 0 -#define GIC_LOWEST_SEC_PRIORITY 127 -#define GIC_HIGHEST_NS_PRIORITY 128 -#define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */ - -#define ENABLE_GRP0 (1 << 0) -#define ENABLE_GRP1 (1 << 1) - -/* Distributor interface definitions */ -#define GICD_CTLR 0x0 -#define GICD_TYPER 0x4 -#define GICD_IGROUPR 0x80 -#define GICD_ISENABLER 0x100 -#define GICD_ICENABLER 0x180 -#define GICD_ISPENDR 0x200 -#define GICD_ICPENDR 0x280 -#define GICD_ISACTIVER 0x300 -#define GICD_ICACTIVER 0x380 -#define GICD_IPRIORITYR 0x400 -#define GICD_ITARGETSR 0x800 -#define GICD_ICFGR 0xC00 -#define GICD_SGIR 0xF00 -#define GICD_CPENDSGIR 0xF10 -#define GICD_SPENDSGIR 0xF20 - -#define IGROUPR_SHIFT 5 -#define ISENABLER_SHIFT 5 -#define ICENABLER_SHIFT ISENABLER_SHIFT -#define ISPENDR_SHIFT 5 -#define ICPENDR_SHIFT ISPENDR_SHIFT -#define ISACTIVER_SHIFT 5 -#define ICACTIVER_SHIFT ISACTIVER_SHIFT -#define IPRIORITYR_SHIFT 2 -#define ITARGETSR_SHIFT 2 -#define ICFGR_SHIFT 4 -#define CPENDSGIR_SHIFT 2 -#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT - -/* GICD_TYPER bit definitions */ -#define IT_LINES_NO_MASK 0x1f - -/* Physical CPU Interface registers */ -#define GICC_CTLR 0x0 -#define GICC_PMR 0x4 -#define GICC_BPR 0x8 -#define GICC_IAR 0xC -#define GICC_EOIR 0x10 -#define GICC_RPR 0x14 -#define GICC_HPPIR 0x18 -#define GICC_IIDR 0xFC -#define GICC_DIR 0x1000 -#define GICC_PRIODROP GICC_EOIR - -/* GICC_CTLR bit definitions */ -#define EOI_MODE_NS (1 << 10) -#define EOI_MODE_S (1 << 9) -#define IRQ_BYP_DIS_GRP1 (1 << 8) -#define FIQ_BYP_DIS_GRP1 (1 << 7) -#define IRQ_BYP_DIS_GRP0 (1 << 6) -#define FIQ_BYP_DIS_GRP0 (1 << 5) -#define CBPR (1 << 4) -#define FIQ_EN (1 << 3) -#define ACK_CTL (1 << 2) - -/* GICC_IIDR bit masks and shifts */ -#define GICC_IIDR_PID_SHIFT 20 -#define GICC_IIDR_ARCH_SHIFT 16 -#define GICC_IIDR_REV_SHIFT 12 -#define GICC_IIDR_IMP_SHIFT 0 - -#define GICC_IIDR_PID_MASK 0xfff -#define GICC_IIDR_ARCH_MASK 0xf -#define GICC_IIDR_REV_MASK 0xf -#define GICC_IIDR_IMP_MASK 0xfff - -/* HYP view virtual CPU Interface registers */ -#define GICH_CTL 0x0 -#define GICH_VTR 0x4 -#define GICH_ELRSR0 0x30 -#define GICH_ELRSR1 0x34 -#define GICH_APR0 0xF0 -#define GICH_LR_BASE 0x100 - -/* Virtual CPU Interface registers */ -#define GICV_CTL 0x0 -#define GICV_PRIMASK 0x4 -#define GICV_BP 0x8 -#define GICV_INTACK 0xC -#define GICV_EOI 0x10 -#define GICV_RUNNINGPRI 0x14 -#define GICV_HIGHESTPEND 0x18 -#define GICV_DEACTIVATE 0x1000 - -/* GICv3 Re-distributor interface registers & shifts */ -#define GICR_PCPUBASE_SHIFT 0x11 -#define GICR_TYPER 0x08 -#define GICR_WAKER 0x14 - -/* GICR_WAKER bit definitions */ -#define WAKER_CA (1UL << 2) -#define WAKER_PS (1UL << 1) - -/* GICR_TYPER bit definitions */ -#define GICR_TYPER_AFF_SHIFT 32 -#define GICR_TYPER_AFF_MASK 0xffffffff -#define GICR_TYPER_LAST (1UL << 4) - -/* GICv3 ICC_SRE register bit definitions*/ -#define ICC_SRE_EN (1UL << 3) -#define ICC_SRE_SRE (1UL << 0) - -#ifndef __ASSEMBLY__ - -#include -#include - -/******************************************************************************* - * Function prototypes - ******************************************************************************/ - -extern unsigned int gicd_read_igroupr(unsigned int, unsigned int); -extern unsigned int gicd_read_isenabler(unsigned int, unsigned int); -extern unsigned int gicd_read_icenabler(unsigned int, unsigned int); -extern unsigned int gicd_read_ispendr(unsigned int, unsigned int); -extern unsigned int gicd_read_icpendr(unsigned int, unsigned int); -extern unsigned int gicd_read_isactiver(unsigned int, unsigned int); -extern unsigned int gicd_read_icactiver(unsigned int, unsigned int); -extern unsigned int gicd_read_ipriorityr(unsigned int, unsigned int); -extern unsigned int gicd_read_itargetsr(unsigned int, unsigned int); -extern unsigned int gicd_read_icfgr(unsigned int, unsigned int); -extern unsigned int gicd_read_cpendsgir(unsigned int, unsigned int); -extern unsigned int gicd_read_spendsgir(unsigned int, unsigned int); -extern void gicd_write_igroupr(unsigned int, unsigned int, unsigned int); -extern void gicd_write_isenabler(unsigned int, unsigned int, unsigned int); -extern void gicd_write_icenabler(unsigned int, unsigned int, unsigned int); -extern void gicd_write_ispendr(unsigned int, unsigned int, unsigned int); -extern void gicd_write_icpendr(unsigned int, unsigned int, unsigned int); -extern void gicd_write_isactiver(unsigned int, unsigned int, unsigned int); -extern void gicd_write_icactiver(unsigned int, unsigned int, unsigned int); -extern void gicd_write_ipriorityr(unsigned int, unsigned int, unsigned int); -extern void gicd_write_itargetsr(unsigned int, unsigned int, unsigned int); -extern void gicd_write_icfgr(unsigned int, unsigned int, unsigned int); -extern void gicd_write_cpendsgir(unsigned int, unsigned int, unsigned int); -extern void gicd_write_spendsgir(unsigned int, unsigned int, unsigned int); -extern unsigned int gicd_get_igroupr(unsigned int, unsigned int); -extern void gicd_set_igroupr(unsigned int, unsigned int); -extern void gicd_clr_igroupr(unsigned int, unsigned int); -extern void gicd_set_isenabler(unsigned int, unsigned int); -extern void gicd_set_icenabler(unsigned int, unsigned int); -extern void gicd_set_ispendr(unsigned int, unsigned int); -extern void gicd_set_icpendr(unsigned int, unsigned int); -extern void gicd_set_isactiver(unsigned int, unsigned int); -extern void gicd_set_icactiver(unsigned int, unsigned int); -extern void gicd_set_ipriorityr(unsigned int, unsigned int, unsigned int); -extern void gicd_set_itargetsr(unsigned int, unsigned int, unsigned int); - -/* GICv3 functions */ - -extern unsigned int read_icc_sre_el1(void); -extern unsigned int read_icc_sre_el2(void); -extern unsigned int read_icc_sre_el3(void); -extern void write_icc_sre_el1(unsigned int); -extern void write_icc_sre_el2(unsigned int); -extern void write_icc_sre_el3(unsigned int); -extern void write_icc_pmr_el1(unsigned int); - -#endif /*__ASSEMBLY__*/ - -#endif /* __GIC_H__ */ - diff --git a/arch/system/gic/gic_v2.c b/arch/system/gic/gic_v2.c deleted file mode 100644 index 6af0378..0000000 --- a/arch/system/gic/gic_v2.c +++ /dev/null @@ -1,298 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - -/******************************************************************************* - * GIC Distributor interface accessors for reading entire registers - ******************************************************************************/ - -unsigned int gicd_read_igroupr(unsigned int base, unsigned int id) -{ - unsigned n = id >> IGROUPR_SHIFT; - return mmio_read_32(base + GICD_IGROUPR + (n << 2)); -} - -unsigned int gicd_read_isenabler(unsigned int base, unsigned int id) -{ - unsigned n = id >> ISENABLER_SHIFT; - return mmio_read_32(base + GICD_ISENABLER + (n << 2)); -} - -unsigned int gicd_read_icenabler(unsigned int base, unsigned int id) -{ - unsigned n = id >> ICENABLER_SHIFT; - return mmio_read_32(base + GICD_ICENABLER + (n << 2)); -} - -unsigned int gicd_read_ispendr(unsigned int base, unsigned int id) -{ - unsigned n = id >> ISPENDR_SHIFT; - return mmio_read_32(base + GICD_ISPENDR + (n << 2)); -} - -unsigned int gicd_read_icpendr(unsigned int base, unsigned int id) -{ - unsigned n = id >> ICPENDR_SHIFT; - return mmio_read_32(base + GICD_ICPENDR + (n << 2)); -} - -unsigned int gicd_read_isactiver(unsigned int base, unsigned int id) -{ - unsigned n = id >> ISACTIVER_SHIFT; - return mmio_read_32(base + GICD_ISACTIVER + (n << 2)); -} - -unsigned int gicd_read_icactiver(unsigned int base, unsigned int id) -{ - unsigned n = id >> ICACTIVER_SHIFT; - return mmio_read_32(base + GICD_ICACTIVER + (n << 2)); -} - -unsigned int gicd_read_ipriorityr(unsigned int base, unsigned int id) -{ - unsigned n = id >> IPRIORITYR_SHIFT; - return mmio_read_32(base + GICD_IPRIORITYR + (n << 2)); -} - -unsigned int gicd_read_itargetsr(unsigned int base, unsigned int id) -{ - unsigned n = id >> ITARGETSR_SHIFT; - return mmio_read_32(base + GICD_ITARGETSR + (n << 2)); -} - -unsigned int gicd_read_icfgr(unsigned int base, unsigned int id) -{ - unsigned n = id >> ICFGR_SHIFT; - return mmio_read_32(base + GICD_ICFGR + (n << 2)); -} - -unsigned int gicd_read_cpendsgir(unsigned int base, unsigned int id) -{ - unsigned n = id >> CPENDSGIR_SHIFT; - return mmio_read_32(base + GICD_CPENDSGIR + (n << 2)); -} - -unsigned int gicd_read_spendsgir(unsigned int base, unsigned int id) -{ - unsigned n = id >> SPENDSGIR_SHIFT; - return mmio_read_32(base + GICD_SPENDSGIR + (n << 2)); -} - -/******************************************************************************* - * GIC Distributor interface accessors for writing entire registers - ******************************************************************************/ - -void gicd_write_igroupr(unsigned int base, unsigned int id, unsigned int val) -{ - unsigned n = id >> IGROUPR_SHIFT; - mmio_write_32(base + GICD_IGROUPR + (n << 2), val); -} - -void gicd_write_isenabler(unsigned int base, unsigned int id, unsigned int val) -{ - unsigned n = id >> ISENABLER_SHIFT; - mmio_write_32(base + GICD_ISENABLER + (n << 2), val); -} - -void gicd_write_icenabler(unsigned int base, unsigned int id, unsigned int val) -{ - unsigned n = id >> ICENABLER_SHIFT; - mmio_write_32(base + GICD_ICENABLER + (n << 2), val); -} - -void gicd_write_ispendr(unsigned int base, unsigned int id, unsigned int val) -{ - unsigned n = id >> ISPENDR_SHIFT; - mmio_write_32(base + GICD_ISPENDR + (n << 2), val); -} - -void gicd_write_icpendr(unsigned int base, unsigned int id, unsigned int val) -{ - unsigned n = id >> ICPENDR_SHIFT; - mmio_write_32(base + GICD_ICPENDR + (n << 2), val); -} - -void gicd_write_isactiver(unsigned int base, unsigned int id, unsigned int val) -{ - unsigned n = id >> ISACTIVER_SHIFT; - mmio_write_32(base + GICD_ISACTIVER + (n << 2), val); -} - -void gicd_write_icactiver(unsigned int base, unsigned int id, unsigned int val) -{ - unsigned n = id >> ICACTIVER_SHIFT; - mmio_write_32(base + GICD_ICACTIVER + (n << 2), val); -} - -void gicd_write_ipriorityr(unsigned int base, unsigned int id, unsigned int val) -{ - unsigned n = id >> IPRIORITYR_SHIFT; - mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val); -} - -void gicd_write_itargetsr(unsigned int base, unsigned int id, unsigned int val) -{ - unsigned n = id >> ITARGETSR_SHIFT; - mmio_write_32(base + GICD_ITARGETSR + (n << 2), val); -} - -void gicd_write_icfgr(unsigned int base, unsigned int id, unsigned int val) -{ - unsigned n = id >> ICFGR_SHIFT; - mmio_write_32(base + GICD_ICFGR + (n << 2), val); -} - -void gicd_write_cpendsgir(unsigned int base, unsigned int id, unsigned int val) -{ - unsigned n = id >> CPENDSGIR_SHIFT; - mmio_write_32(base + GICD_CPENDSGIR + (n << 2), val); -} - -void gicd_write_spendsgir(unsigned int base, unsigned int id, unsigned int val) -{ - unsigned n = id >> SPENDSGIR_SHIFT; - mmio_write_32(base + GICD_SPENDSGIR + (n << 2), val); -} - -/******************************************************************************* - * GIC Distributor interface accessors for individual interrupt manipulation - ******************************************************************************/ -unsigned int gicd_get_igroupr(unsigned int base, unsigned int id) -{ - unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); - unsigned int reg_val = gicd_read_igroupr(base, id); - - return (reg_val >> bit_num) & 0x1; -} - -void gicd_set_igroupr(unsigned int base, unsigned int id) -{ - unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); - unsigned int reg_val = gicd_read_igroupr(base, id); - - gicd_write_igroupr(base, id, reg_val | (1 << bit_num)); -} - -void gicd_clr_igroupr(unsigned int base, unsigned int id) -{ - unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); - unsigned int reg_val = gicd_read_igroupr(base, id); - - gicd_write_igroupr(base, id, reg_val & ~(1 << bit_num)); -} - -void gicd_set_isenabler(unsigned int base, unsigned int id) -{ - unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1); - unsigned int reg_val = gicd_read_isenabler(base, id); - - gicd_write_isenabler(base, id, reg_val | (1 << bit_num)); -} - -void gicd_set_icenabler(unsigned int base, unsigned int id) -{ - unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1); - unsigned int reg_val = gicd_read_icenabler(base, id); - - gicd_write_icenabler(base, id, reg_val & ~(1 << bit_num)); -} - -void gicd_set_ispendr(unsigned int base, unsigned int id) -{ - unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1); - unsigned int reg_val = gicd_read_ispendr(base, id); - - gicd_write_ispendr(base, id, reg_val | (1 << bit_num)); -} - -void gicd_set_icpendr(unsigned int base, unsigned int id) -{ - unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1); - unsigned int reg_val = gicd_read_icpendr(base, id); - - gicd_write_icpendr(base, id, reg_val & ~(1 << bit_num)); -} - -void gicd_set_isactiver(unsigned int base, unsigned int id) -{ - unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1); - unsigned int reg_val = gicd_read_isactiver(base, id); - - gicd_write_isactiver(base, id, reg_val | (1 << bit_num)); -} - -void gicd_set_icactiver(unsigned int base, unsigned int id) -{ - unsigned bit_num = id & ((1 << ICACTIVER_SHIFT) - 1); - unsigned int reg_val = gicd_read_icactiver(base, id); - - gicd_write_icactiver(base, id, reg_val & ~(1 << bit_num)); -} - -/* - * Make sure that the interrupt's group is set before expecting - * this function to do its job correctly. - */ -void gicd_set_ipriorityr(unsigned int base, unsigned int id, unsigned int pri) -{ - unsigned int reg = base + GICD_IPRIORITYR + (id & ~3); - unsigned int shift = (id & 3) << 3; - unsigned int reg_val = mmio_read_32(reg); - - /* - * Enforce ARM recommendation to manage priority values such - * that group1 interrupts always have a lower priority than - * group0 interrupts. - * Note, lower numerical values are higher priorities so the comparison - * checks below are reversed from what might be expected. - */ - assert(gicd_get_igroupr(base, id) == GRP1 ? - pri >= GIC_HIGHEST_NS_PRIORITY && - pri <= GIC_LOWEST_NS_PRIORITY : - pri >= GIC_HIGHEST_SEC_PRIORITY && - pri <= GIC_LOWEST_SEC_PRIORITY); - - reg_val &= ~(GIC_PRI_MASK << shift); - reg_val |= (pri & GIC_PRI_MASK) << shift; - mmio_write_32(reg, reg_val); -} - -void gicd_set_itargetsr(unsigned int base, unsigned int id, unsigned int iface) -{ - unsigned byte_off = id & ((1 << ITARGETSR_SHIFT) - 1); - unsigned int reg_val = gicd_read_itargetsr(base, id); - - gicd_write_itargetsr(base, id, reg_val | - (1 << iface) << (byte_off << 3)); -} - diff --git a/arch/system/gic/gic_v2.h b/arch/system/gic/gic_v2.h deleted file mode 100644 index 30bd4fc..0000000 --- a/arch/system/gic/gic_v2.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __GIC_V2_H__ -#define __GIC_V2_H__ - -#include - -/******************************************************************************* - * GIC Distributor interface accessors for reading entire registers - ******************************************************************************/ - -static inline unsigned int gicd_read_ctlr(unsigned int base) -{ - return mmio_read_32(base + GICD_CTLR); -} - -static inline unsigned int gicd_read_typer(unsigned int base) -{ - return mmio_read_32(base + GICD_TYPER); -} - -static inline unsigned int gicd_read_sgir(unsigned int base) -{ - return mmio_read_32(base + GICD_SGIR); -} - - -/******************************************************************************* - * GIC Distributor interface accessors for writing entire registers - ******************************************************************************/ - -static inline void gicd_write_ctlr(unsigned int base, unsigned int val) -{ - mmio_write_32(base + GICD_CTLR, val); -} - -static inline void gicd_write_sgir(unsigned int base, unsigned int val) -{ - mmio_write_32(base + GICD_SGIR, val); -} - - -/******************************************************************************* - * GIC CPU interface accessors for reading entire registers - ******************************************************************************/ - -static inline unsigned int gicc_read_ctlr(unsigned int base) -{ - return mmio_read_32(base + GICC_CTLR); -} - -static inline unsigned int gicc_read_pmr(unsigned int base) -{ - return mmio_read_32(base + GICC_PMR); -} - -static inline unsigned int gicc_read_BPR(unsigned int base) -{ - return mmio_read_32(base + GICC_BPR); -} - -static inline unsigned int gicc_read_IAR(unsigned int base) -{ - return mmio_read_32(base + GICC_IAR); -} - -static inline unsigned int gicc_read_EOIR(unsigned int base) -{ - return mmio_read_32(base + GICC_EOIR); -} - -static inline unsigned int gicc_read_hppir(unsigned int base) -{ - return mmio_read_32(base + GICC_HPPIR); -} - -static inline unsigned int gicc_read_dir(unsigned int base) -{ - return mmio_read_32(base + GICC_DIR); -} - -static inline unsigned int gicc_read_iidr(unsigned int base) -{ - return mmio_read_32(base + GICC_IIDR); -} - - -/******************************************************************************* - * GIC CPU interface accessors for writing entire registers - ******************************************************************************/ - -static inline void gicc_write_ctlr(unsigned int base, unsigned int val) -{ - mmio_write_32(base + GICC_CTLR, val); -} - -static inline void gicc_write_pmr(unsigned int base, unsigned int val) -{ - mmio_write_32(base + GICC_PMR, val); -} - -static inline void gicc_write_BPR(unsigned int base, unsigned int val) -{ - mmio_write_32(base + GICC_BPR, val); -} - - -static inline void gicc_write_IAR(unsigned int base, unsigned int val) -{ - mmio_write_32(base + GICC_IAR, val); -} - -static inline void gicc_write_EOIR(unsigned int base, unsigned int val) -{ - mmio_write_32(base + GICC_EOIR, val); -} - -static inline void gicc_write_hppir(unsigned int base, unsigned int val) -{ - mmio_write_32(base + GICC_HPPIR, val); -} - -static inline void gicc_write_dir(unsigned int base, unsigned int val) -{ - mmio_write_32(base + GICC_DIR, val); -} - -#endif /* __GIC_V2_H__ */ diff --git a/arch/system/gic/gic_v3.c b/arch/system/gic/gic_v3.c deleted file mode 100644 index b7db1f0..0000000 --- a/arch/system/gic/gic_v3.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include - -uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr) -{ - uint32_t cpu_aff, gicr_aff; - uint64_t gicr_typer; - uintptr_t addr; - - /* Construct the affinity as used by GICv3. MPIDR and GIC affinity level - * mask is the same. - */ - cpu_aff = ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) << - GICV3_AFF0_SHIFT; - cpu_aff |= ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) << - GICV3_AFF1_SHIFT; - cpu_aff |= ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) << - GICV3_AFF2_SHIFT; - cpu_aff |= ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) << - GICV3_AFF3_SHIFT; - - addr = gicr_base; - do { - gicr_typer = gicr_read_typer(addr); - - gicr_aff = (gicr_typer >> GICR_TYPER_AFF_SHIFT) & - GICR_TYPER_AFF_MASK; - if (cpu_aff == gicr_aff) { - /* Disable this print for now as it appears every time - * when using PSCI CPU_SUSPEND. - * TODO: Print this only the first time for each CPU. - * INFO("GICv3 - Found RDIST for MPIDR(0x%lx) at 0x%lx\n", - * mpidr, addr); - */ - return addr; - } - - /* TODO: - * For GICv4 we need to adjust the Base address based on - * GICR_TYPER.VLPIS - */ - addr += (1 << GICR_PCPUBASE_SHIFT); - - } while (!(gicr_typer & GICR_TYPER_LAST)); - - /* If we get here we did not find a match. */ - ERROR("GICv3 - Did not find RDIST for CPU with MPIDR 0x%lx\n", mpidr); - return (uintptr_t)NULL; -} diff --git a/arch/system/gic/gic_v3.h b/arch/system/gic/gic_v3.h deleted file mode 100644 index df7e7fd..0000000 --- a/arch/system/gic/gic_v3.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __GIC_V3_H__ -#define __GIC_V3_H__ - -#include -#include - -#define GICV3_AFFLVL_MASK 0xff -#define GICV3_AFF0_SHIFT 0 -#define GICV3_AFF1_SHIFT 8 -#define GICV3_AFF2_SHIFT 16 -#define GICV3_AFF3_SHIFT 24 -#define GICV3_AFFINITY_MASK 0xffffffff - -uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr); - -/******************************************************************************* - * GIC Redistributor interface accessors - ******************************************************************************/ -static inline uint32_t gicr_read_waker(uintptr_t base) -{ - return mmio_read_32(base + GICR_WAKER); -} - -static inline void gicr_write_waker(uintptr_t base, uint32_t val) -{ - mmio_write_32(base + GICR_WAKER, val); -} - -static inline uint64_t gicr_read_typer(uintptr_t base) -{ - return mmio_read_64(base + GICR_TYPER); -} - - -#endif /* __GIC_V3_H__ */ diff --git a/bl1/bl1.mk b/bl1/bl1.mk index c2101b0..60609ea 100644 --- a/bl1/bl1.mk +++ b/bl1/bl1.mk @@ -32,15 +32,12 @@ plat/${PLAT}/${ARCH} \ common \ lib \ - arch/${ARCH} \ - lib/arch/${ARCH} \ + lib/${ARCH} \ ${PLAT_BL1_C_VPATH} -vpath %.S arch/${ARCH}/cpu \ - plat/common/${ARCH} \ +vpath %.S plat/common/${ARCH} \ plat/${PLAT}/${ARCH} \ - include \ - lib/arch/${ARCH} \ + lib/${ARCH} \ ${PLAT_BL1_S_VPATH} BL1_SOURCES += bl1_arch_setup.c \ diff --git a/bl2/bl2.mk b/bl2/bl2.mk index d53c1aa..3ecaff9 100644 --- a/bl2/bl2.mk +++ b/bl2/bl2.mk @@ -32,12 +32,10 @@ lib \ plat/${PLAT} \ plat/${PLAT}/${ARCH} \ - arch/${ARCH} \ ${PLAT_BL2_C_VPATH} -vpath %.S lib/arch/${ARCH} \ - include \ - lib/sync/locks/exclusive \ +vpath %.S lib/${ARCH} \ + lib/locks/exclusive \ common/${ARCH} \ ${PLAT_BL2_S_VPATH} diff --git a/bl31/bl31.mk b/bl31/bl31.mk index 38765bc..420597c 100644 --- a/bl31/bl31.mk +++ b/bl31/bl31.mk @@ -30,23 +30,21 @@ vpath %.c common \ lib \ - arch/system/gic \ + drivers/arm/gic \ plat/${PLAT} \ - arch/${ARCH} \ services/std_svc \ services/std_svc/psci \ - lib/sync/locks/bakery \ + lib/locks/bakery \ plat/${PLAT}/${ARCH} \ ${PLAT_BL31_C_VPATH} -vpath %.S lib/arch/${ARCH} \ +vpath %.S lib/${ARCH} \ services/std_svc \ services/std_svc/psci \ - include \ plat/${PLAT}/${ARCH} \ - lib/sync/locks/exclusive \ + lib/locks/exclusive \ plat/common/${ARCH} \ - arch/system/gic/${ARCH} \ + drivers/arm/gic/${ARCH} \ common/${ARCH} \ ${PLAT_BL31_S_VPATH} diff --git a/bl31/runtime_svc.c b/bl31/runtime_svc.c new file mode 100644 index 0000000..1628e8d --- /dev/null +++ b/bl31/runtime_svc.c @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * The 'rt_svc_descs' array holds the runtime service descriptors exported by + * services by placing them in the 'rt_svc_descs' linker section. + * The 'rt_svc_descs_indices' array holds the index of a descriptor in the + * 'rt_svc_descs' array. When an SMC arrives, the OEN[29:24] bits and the call + * type[31] bit in the function id are combined to get an index into the + * 'rt_svc_descs_indices' array. This gives the index of the descriptor in the + * 'rt_svc_descs' array which contains the SMC handler. + ******************************************************************************/ +#define RT_SVC_DESCS_START ((uint64_t) (&__RT_SVC_DESCS_START__)) +#define RT_SVC_DESCS_END ((uint64_t) (&__RT_SVC_DESCS_END__)) +uint8_t rt_svc_descs_indices[MAX_RT_SVCS]; +static rt_svc_desc *rt_svc_descs; + +/******************************************************************************* + * Simple routine to sanity check a runtime service descriptor before using it + ******************************************************************************/ +static int32_t validate_rt_svc_desc(rt_svc_desc *desc) +{ + if (desc == NULL) + return -EINVAL; + + if (desc->start_oen > desc->end_oen) + return -EINVAL; + + if (desc->end_oen >= OEN_LIMIT) + return -EINVAL; + + if (desc->call_type != SMC_TYPE_FAST && desc->call_type != SMC_TYPE_STD) + return -EINVAL; + + /* A runtime service having no init or handle function doesn't make sense */ + if (desc->init == NULL && desc->handle == NULL) + return -EINVAL; + + return 0; +} + +/******************************************************************************* + * This function calls the initialisation routine in the descriptor exported by + * a runtime service. Once a descriptor has been validated, its start & end + * owning entity numbers and the call type are combined to form a unique oen. + * The unique oen is used as an index into the 'rt_svc_descs_indices' array. + * The index of the runtime service descriptor is stored at this index. + ******************************************************************************/ +void runtime_svc_init() +{ + int32_t rc = 0; + uint32_t index, start_idx, end_idx; + uint64_t rt_svc_descs_num; + + /* If no runtime services are implemented then simply bail out */ + rt_svc_descs_num = RT_SVC_DESCS_END - RT_SVC_DESCS_START; + rt_svc_descs_num /= sizeof(rt_svc_desc); + if (rt_svc_descs_num == 0) + return; + + /* Initialise internal variables to invalid state */ + memset(rt_svc_descs_indices, -1, sizeof(rt_svc_descs_indices)); + + rt_svc_descs = (rt_svc_desc *) RT_SVC_DESCS_START; + for (index = 0; index < rt_svc_descs_num; index++) { + + /* + * An invalid descriptor is an error condition since it is + * difficult to predict the system behaviour in the absence + * of this service. + */ + rc = validate_rt_svc_desc(&rt_svc_descs[index]); + if (rc) { + ERROR("Invalid runtime service descriptor 0x%x (%s)\n", + &rt_svc_descs[index], + rt_svc_descs[index].name); + goto error; + } + + /* Call the initialisation routine for this runtime service */ + rc = rt_svc_descs[index].init(); + if (rc) { + ERROR("Error initializing runtime service %s\n", + rt_svc_descs[index].name); + } else { + /* + * Fill the indices corresponding to the start and end + * owning entity numbers with the index of the + * descriptor which will handle the SMCs for this owning + * entity range. + */ + start_idx = get_unique_oen(rt_svc_descs[index].start_oen, + rt_svc_descs[index].call_type); + end_idx = get_unique_oen(rt_svc_descs[index].end_oen, + rt_svc_descs[index].call_type); + + for (; start_idx <= end_idx; start_idx++) + rt_svc_descs_indices[start_idx] = index; + } + } + + return; +error: + panic(); +} + +void fault_handler(void *handle) +{ + gp_regs *gpregs_ctx = get_gpregs_ctx(handle); + ERROR("Unhandled synchronous fault. Register dump @ 0x%x \n", + gpregs_ctx); + panic(); +} diff --git a/bl32/tsp/tsp.mk b/bl32/tsp/tsp.mk index 2aedf61..d07b18b 100644 --- a/bl32/tsp/tsp.mk +++ b/bl32/tsp/tsp.mk @@ -32,11 +32,9 @@ lib \ plat/${PLAT} \ plat/${PLAT}/${ARCH} \ - arch/${ARCH} -vpath %.S lib/arch/${ARCH} \ - include \ - lib/sync/locks/exclusive \ +vpath %.S lib/${ARCH} \ + lib/locks/exclusive \ common/${ARCH} BL32_SOURCES += tsp_entrypoint.S \ diff --git a/common/runtime_svc.c b/common/runtime_svc.c deleted file mode 100644 index 1628e8d..0000000 --- a/common/runtime_svc.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/******************************************************************************* - * The 'rt_svc_descs' array holds the runtime service descriptors exported by - * services by placing them in the 'rt_svc_descs' linker section. - * The 'rt_svc_descs_indices' array holds the index of a descriptor in the - * 'rt_svc_descs' array. When an SMC arrives, the OEN[29:24] bits and the call - * type[31] bit in the function id are combined to get an index into the - * 'rt_svc_descs_indices' array. This gives the index of the descriptor in the - * 'rt_svc_descs' array which contains the SMC handler. - ******************************************************************************/ -#define RT_SVC_DESCS_START ((uint64_t) (&__RT_SVC_DESCS_START__)) -#define RT_SVC_DESCS_END ((uint64_t) (&__RT_SVC_DESCS_END__)) -uint8_t rt_svc_descs_indices[MAX_RT_SVCS]; -static rt_svc_desc *rt_svc_descs; - -/******************************************************************************* - * Simple routine to sanity check a runtime service descriptor before using it - ******************************************************************************/ -static int32_t validate_rt_svc_desc(rt_svc_desc *desc) -{ - if (desc == NULL) - return -EINVAL; - - if (desc->start_oen > desc->end_oen) - return -EINVAL; - - if (desc->end_oen >= OEN_LIMIT) - return -EINVAL; - - if (desc->call_type != SMC_TYPE_FAST && desc->call_type != SMC_TYPE_STD) - return -EINVAL; - - /* A runtime service having no init or handle function doesn't make sense */ - if (desc->init == NULL && desc->handle == NULL) - return -EINVAL; - - return 0; -} - -/******************************************************************************* - * This function calls the initialisation routine in the descriptor exported by - * a runtime service. Once a descriptor has been validated, its start & end - * owning entity numbers and the call type are combined to form a unique oen. - * The unique oen is used as an index into the 'rt_svc_descs_indices' array. - * The index of the runtime service descriptor is stored at this index. - ******************************************************************************/ -void runtime_svc_init() -{ - int32_t rc = 0; - uint32_t index, start_idx, end_idx; - uint64_t rt_svc_descs_num; - - /* If no runtime services are implemented then simply bail out */ - rt_svc_descs_num = RT_SVC_DESCS_END - RT_SVC_DESCS_START; - rt_svc_descs_num /= sizeof(rt_svc_desc); - if (rt_svc_descs_num == 0) - return; - - /* Initialise internal variables to invalid state */ - memset(rt_svc_descs_indices, -1, sizeof(rt_svc_descs_indices)); - - rt_svc_descs = (rt_svc_desc *) RT_SVC_DESCS_START; - for (index = 0; index < rt_svc_descs_num; index++) { - - /* - * An invalid descriptor is an error condition since it is - * difficult to predict the system behaviour in the absence - * of this service. - */ - rc = validate_rt_svc_desc(&rt_svc_descs[index]); - if (rc) { - ERROR("Invalid runtime service descriptor 0x%x (%s)\n", - &rt_svc_descs[index], - rt_svc_descs[index].name); - goto error; - } - - /* Call the initialisation routine for this runtime service */ - rc = rt_svc_descs[index].init(); - if (rc) { - ERROR("Error initializing runtime service %s\n", - rt_svc_descs[index].name); - } else { - /* - * Fill the indices corresponding to the start and end - * owning entity numbers with the index of the - * descriptor which will handle the SMCs for this owning - * entity range. - */ - start_idx = get_unique_oen(rt_svc_descs[index].start_oen, - rt_svc_descs[index].call_type); - end_idx = get_unique_oen(rt_svc_descs[index].end_oen, - rt_svc_descs[index].call_type); - - for (; start_idx <= end_idx; start_idx++) - rt_svc_descs_indices[start_idx] = index; - } - } - - return; -error: - panic(); -} - -void fault_handler(void *handle) -{ - gp_regs *gpregs_ctx = get_gpregs_ctx(handle); - ERROR("Unhandled synchronous fault. Register dump @ 0x%x \n", - gpregs_ctx); - panic(); -} diff --git a/drivers/arm/cci400/cci400.c b/drivers/arm/cci400/cci400.c new file mode 100644 index 0000000..4ca55b1 --- /dev/null +++ b/drivers/arm/cci400/cci400.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +static inline unsigned long get_slave_iface_base(unsigned long mpidr) +{ + return CCI400_BASE + SLAVE_IFACE_OFFSET(CCI400_SL_IFACE_INDEX(mpidr)); +} + +void cci_enable_coherency(unsigned long mpidr) +{ + /* Enable Snoops and DVM messages */ + mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG, + DVM_EN_BIT | SNOOP_EN_BIT); + + /* Wait for the dust to settle down */ + while (mmio_read_32(CCI400_BASE + STATUS_REG) & CHANGE_PENDING_BIT) + ; +} + +void cci_disable_coherency(unsigned long mpidr) +{ + /* Disable Snoops and DVM messages */ + mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG, + ~(DVM_EN_BIT | SNOOP_EN_BIT)); + + /* Wait for the dust to settle down */ + while (mmio_read_32(CCI400_BASE + STATUS_REG) & CHANGE_PENDING_BIT) + ; +} + diff --git a/drivers/arm/gic/aarch64/gic_v3_sysregs.S b/drivers/arm/gic/aarch64/gic_v3_sysregs.S new file mode 100644 index 0000000..2a96da7 --- /dev/null +++ b/drivers/arm/gic/aarch64/gic_v3_sysregs.S @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + + .globl read_icc_sre_el1 + .globl read_icc_sre_el2 + .globl read_icc_sre_el3 + .globl write_icc_sre_el1 + .globl write_icc_sre_el2 + .globl write_icc_sre_el3 + .globl write_icc_pmr_el1 + + +/* + * Register definitions used by GCC for GICv3 access. + * These are defined by ARMCC, so keep them in the GCC specific code for now. + */ +#define ICC_SRE_EL1 S3_0_C12_C12_5 +#define ICC_SRE_EL2 S3_4_C12_C9_5 +#define ICC_SRE_EL3 S3_6_C12_C12_5 +#define ICC_CTLR_EL1 S3_0_C12_C12_4 +#define ICC_CTLR_EL3 S3_6_C12_C12_4 +#define ICC_PMR_EL1 S3_0_C4_C6_0 + +func read_icc_sre_el1 + mrs x0, ICC_SRE_EL1 + ret + + +func read_icc_sre_el2 + mrs x0, ICC_SRE_EL2 + ret + + +func read_icc_sre_el3 + mrs x0, ICC_SRE_EL3 + ret + + +func write_icc_sre_el1 + msr ICC_SRE_EL1, x0 + isb + ret + + +func write_icc_sre_el2 + msr ICC_SRE_EL2, x0 + isb + ret + + +func write_icc_sre_el3 + msr ICC_SRE_EL3, x0 + isb + ret + + +func write_icc_pmr_el1 + msr ICC_PMR_EL1, x0 + isb + ret diff --git a/drivers/arm/gic/gic_v2.c b/drivers/arm/gic/gic_v2.c new file mode 100644 index 0000000..6af0378 --- /dev/null +++ b/drivers/arm/gic/gic_v2.c @@ -0,0 +1,298 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/******************************************************************************* + * GIC Distributor interface accessors for reading entire registers + ******************************************************************************/ + +unsigned int gicd_read_igroupr(unsigned int base, unsigned int id) +{ + unsigned n = id >> IGROUPR_SHIFT; + return mmio_read_32(base + GICD_IGROUPR + (n << 2)); +} + +unsigned int gicd_read_isenabler(unsigned int base, unsigned int id) +{ + unsigned n = id >> ISENABLER_SHIFT; + return mmio_read_32(base + GICD_ISENABLER + (n << 2)); +} + +unsigned int gicd_read_icenabler(unsigned int base, unsigned int id) +{ + unsigned n = id >> ICENABLER_SHIFT; + return mmio_read_32(base + GICD_ICENABLER + (n << 2)); +} + +unsigned int gicd_read_ispendr(unsigned int base, unsigned int id) +{ + unsigned n = id >> ISPENDR_SHIFT; + return mmio_read_32(base + GICD_ISPENDR + (n << 2)); +} + +unsigned int gicd_read_icpendr(unsigned int base, unsigned int id) +{ + unsigned n = id >> ICPENDR_SHIFT; + return mmio_read_32(base + GICD_ICPENDR + (n << 2)); +} + +unsigned int gicd_read_isactiver(unsigned int base, unsigned int id) +{ + unsigned n = id >> ISACTIVER_SHIFT; + return mmio_read_32(base + GICD_ISACTIVER + (n << 2)); +} + +unsigned int gicd_read_icactiver(unsigned int base, unsigned int id) +{ + unsigned n = id >> ICACTIVER_SHIFT; + return mmio_read_32(base + GICD_ICACTIVER + (n << 2)); +} + +unsigned int gicd_read_ipriorityr(unsigned int base, unsigned int id) +{ + unsigned n = id >> IPRIORITYR_SHIFT; + return mmio_read_32(base + GICD_IPRIORITYR + (n << 2)); +} + +unsigned int gicd_read_itargetsr(unsigned int base, unsigned int id) +{ + unsigned n = id >> ITARGETSR_SHIFT; + return mmio_read_32(base + GICD_ITARGETSR + (n << 2)); +} + +unsigned int gicd_read_icfgr(unsigned int base, unsigned int id) +{ + unsigned n = id >> ICFGR_SHIFT; + return mmio_read_32(base + GICD_ICFGR + (n << 2)); +} + +unsigned int gicd_read_cpendsgir(unsigned int base, unsigned int id) +{ + unsigned n = id >> CPENDSGIR_SHIFT; + return mmio_read_32(base + GICD_CPENDSGIR + (n << 2)); +} + +unsigned int gicd_read_spendsgir(unsigned int base, unsigned int id) +{ + unsigned n = id >> SPENDSGIR_SHIFT; + return mmio_read_32(base + GICD_SPENDSGIR + (n << 2)); +} + +/******************************************************************************* + * GIC Distributor interface accessors for writing entire registers + ******************************************************************************/ + +void gicd_write_igroupr(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> IGROUPR_SHIFT; + mmio_write_32(base + GICD_IGROUPR + (n << 2), val); +} + +void gicd_write_isenabler(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ISENABLER_SHIFT; + mmio_write_32(base + GICD_ISENABLER + (n << 2), val); +} + +void gicd_write_icenabler(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICENABLER_SHIFT; + mmio_write_32(base + GICD_ICENABLER + (n << 2), val); +} + +void gicd_write_ispendr(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ISPENDR_SHIFT; + mmio_write_32(base + GICD_ISPENDR + (n << 2), val); +} + +void gicd_write_icpendr(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICPENDR_SHIFT; + mmio_write_32(base + GICD_ICPENDR + (n << 2), val); +} + +void gicd_write_isactiver(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ISACTIVER_SHIFT; + mmio_write_32(base + GICD_ISACTIVER + (n << 2), val); +} + +void gicd_write_icactiver(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICACTIVER_SHIFT; + mmio_write_32(base + GICD_ICACTIVER + (n << 2), val); +} + +void gicd_write_ipriorityr(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> IPRIORITYR_SHIFT; + mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val); +} + +void gicd_write_itargetsr(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ITARGETSR_SHIFT; + mmio_write_32(base + GICD_ITARGETSR + (n << 2), val); +} + +void gicd_write_icfgr(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICFGR_SHIFT; + mmio_write_32(base + GICD_ICFGR + (n << 2), val); +} + +void gicd_write_cpendsgir(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> CPENDSGIR_SHIFT; + mmio_write_32(base + GICD_CPENDSGIR + (n << 2), val); +} + +void gicd_write_spendsgir(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> SPENDSGIR_SHIFT; + mmio_write_32(base + GICD_SPENDSGIR + (n << 2), val); +} + +/******************************************************************************* + * GIC Distributor interface accessors for individual interrupt manipulation + ******************************************************************************/ +unsigned int gicd_get_igroupr(unsigned int base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igroupr(base, id); + + return (reg_val >> bit_num) & 0x1; +} + +void gicd_set_igroupr(unsigned int base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igroupr(base, id); + + gicd_write_igroupr(base, id, reg_val | (1 << bit_num)); +} + +void gicd_clr_igroupr(unsigned int base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igroupr(base, id); + + gicd_write_igroupr(base, id, reg_val & ~(1 << bit_num)); +} + +void gicd_set_isenabler(unsigned int base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1); + unsigned int reg_val = gicd_read_isenabler(base, id); + + gicd_write_isenabler(base, id, reg_val | (1 << bit_num)); +} + +void gicd_set_icenabler(unsigned int base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1); + unsigned int reg_val = gicd_read_icenabler(base, id); + + gicd_write_icenabler(base, id, reg_val & ~(1 << bit_num)); +} + +void gicd_set_ispendr(unsigned int base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1); + unsigned int reg_val = gicd_read_ispendr(base, id); + + gicd_write_ispendr(base, id, reg_val | (1 << bit_num)); +} + +void gicd_set_icpendr(unsigned int base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1); + unsigned int reg_val = gicd_read_icpendr(base, id); + + gicd_write_icpendr(base, id, reg_val & ~(1 << bit_num)); +} + +void gicd_set_isactiver(unsigned int base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1); + unsigned int reg_val = gicd_read_isactiver(base, id); + + gicd_write_isactiver(base, id, reg_val | (1 << bit_num)); +} + +void gicd_set_icactiver(unsigned int base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ICACTIVER_SHIFT) - 1); + unsigned int reg_val = gicd_read_icactiver(base, id); + + gicd_write_icactiver(base, id, reg_val & ~(1 << bit_num)); +} + +/* + * Make sure that the interrupt's group is set before expecting + * this function to do its job correctly. + */ +void gicd_set_ipriorityr(unsigned int base, unsigned int id, unsigned int pri) +{ + unsigned int reg = base + GICD_IPRIORITYR + (id & ~3); + unsigned int shift = (id & 3) << 3; + unsigned int reg_val = mmio_read_32(reg); + + /* + * Enforce ARM recommendation to manage priority values such + * that group1 interrupts always have a lower priority than + * group0 interrupts. + * Note, lower numerical values are higher priorities so the comparison + * checks below are reversed from what might be expected. + */ + assert(gicd_get_igroupr(base, id) == GRP1 ? + pri >= GIC_HIGHEST_NS_PRIORITY && + pri <= GIC_LOWEST_NS_PRIORITY : + pri >= GIC_HIGHEST_SEC_PRIORITY && + pri <= GIC_LOWEST_SEC_PRIORITY); + + reg_val &= ~(GIC_PRI_MASK << shift); + reg_val |= (pri & GIC_PRI_MASK) << shift; + mmio_write_32(reg, reg_val); +} + +void gicd_set_itargetsr(unsigned int base, unsigned int id, unsigned int iface) +{ + unsigned byte_off = id & ((1 << ITARGETSR_SHIFT) - 1); + unsigned int reg_val = gicd_read_itargetsr(base, id); + + gicd_write_itargetsr(base, id, reg_val | + (1 << iface) << (byte_off << 3)); +} + diff --git a/drivers/arm/gic/gic_v3.c b/drivers/arm/gic/gic_v3.c new file mode 100644 index 0000000..b7db1f0 --- /dev/null +++ b/drivers/arm/gic/gic_v3.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr) +{ + uint32_t cpu_aff, gicr_aff; + uint64_t gicr_typer; + uintptr_t addr; + + /* Construct the affinity as used by GICv3. MPIDR and GIC affinity level + * mask is the same. + */ + cpu_aff = ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) << + GICV3_AFF0_SHIFT; + cpu_aff |= ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) << + GICV3_AFF1_SHIFT; + cpu_aff |= ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) << + GICV3_AFF2_SHIFT; + cpu_aff |= ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) << + GICV3_AFF3_SHIFT; + + addr = gicr_base; + do { + gicr_typer = gicr_read_typer(addr); + + gicr_aff = (gicr_typer >> GICR_TYPER_AFF_SHIFT) & + GICR_TYPER_AFF_MASK; + if (cpu_aff == gicr_aff) { + /* Disable this print for now as it appears every time + * when using PSCI CPU_SUSPEND. + * TODO: Print this only the first time for each CPU. + * INFO("GICv3 - Found RDIST for MPIDR(0x%lx) at 0x%lx\n", + * mpidr, addr); + */ + return addr; + } + + /* TODO: + * For GICv4 we need to adjust the Base address based on + * GICR_TYPER.VLPIS + */ + addr += (1 << GICR_PCPUBASE_SHIFT); + + } while (!(gicr_typer & GICR_TYPER_LAST)); + + /* If we get here we did not find a match. */ + ERROR("GICv3 - Did not find RDIST for CPU with MPIDR 0x%lx\n", mpidr); + return (uintptr_t)NULL; +} diff --git a/drivers/arm/interconnect/cci-400/cci400.c b/drivers/arm/interconnect/cci-400/cci400.c deleted file mode 100644 index cd5446f..0000000 --- a/drivers/arm/interconnect/cci-400/cci400.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - -static inline unsigned long get_slave_iface_base(unsigned long mpidr) -{ - return CCI400_BASE + SLAVE_IFACE_OFFSET(CCI400_SL_IFACE_INDEX(mpidr)); -} - -void cci_enable_coherency(unsigned long mpidr) -{ - /* Enable Snoops and DVM messages */ - mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG, - DVM_EN_BIT | SNOOP_EN_BIT); - - /* Wait for the dust to settle down */ - while (mmio_read_32(CCI400_BASE + STATUS_REG) & CHANGE_PENDING_BIT); -} - -void cci_disable_coherency(unsigned long mpidr) -{ - /* Disable Snoops and DVM messages */ - mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG, - ~(DVM_EN_BIT | SNOOP_EN_BIT)); - - /* Wait for the dust to settle down */ - while (mmio_read_32(CCI400_BASE + STATUS_REG) & CHANGE_PENDING_BIT); -} - diff --git a/drivers/arm/interconnect/cci-400/cci400.h b/drivers/arm/interconnect/cci-400/cci400.h deleted file mode 100644 index 3921675..0000000 --- a/drivers/arm/interconnect/cci-400/cci400.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __CCI_400_H__ -#define __CCI_400_H__ - -/* Slave interface offsets from PERIPHBASE */ -#define SLAVE_IFACE4_OFFSET 0x5000 -#define SLAVE_IFACE3_OFFSET 0x4000 -#define SLAVE_IFACE2_OFFSET 0x3000 -#define SLAVE_IFACE1_OFFSET 0x2000 -#define SLAVE_IFACE0_OFFSET 0x1000 -#define SLAVE_IFACE_OFFSET(index) SLAVE_IFACE0_OFFSET + (0x1000 * index) - -/* Control and ID register offsets */ -#define CTRL_OVERRIDE_REG 0x0 -#define SPEC_CTRL_REG 0x4 -#define SECURE_ACCESS_REG 0x8 -#define STATUS_REG 0xc -#define IMPRECISE_ERR_REG 0x10 -#define PERFMON_CTRL_REG 0x100 - -/* Slave interface register offsets */ -#define SNOOP_CTRL_REG 0x0 -#define SH_OVERRIDE_REG 0x4 -#define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100 -#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104 -#define QOS_CTRL_REG 0x10c -#define MAX_OT_REG 0x110 -#define TARGET_LATENCY_REG 0x130 -#define LATENCY_REGULATION_REG 0x134 -#define QOS_RANGE_REG 0x138 - -/* Snoop Control register bit definitions */ -#define DVM_EN_BIT (1 << 1) -#define SNOOP_EN_BIT (1 << 0) - -/* Status register bit definitions */ -#define CHANGE_PENDING_BIT (1 << 0) - -/* Function declarations */ -extern void cci_enable_coherency(unsigned long mpidr); -extern void cci_disable_coherency(unsigned long mpidr); - -#endif /* __CCI_400_H__ */ diff --git a/drivers/arm/interconnect/tzc-400/tzc400.c b/drivers/arm/interconnect/tzc-400/tzc400.c deleted file mode 100644 index b88e34a..0000000 --- a/drivers/arm/interconnect/tzc-400/tzc400.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include "arch_helpers.h" -#include "tzc400.h" -#include "mmio.h" -#include "debug.h" - -static uint32_t tzc_read_build_config(uint64_t base) -{ - return mmio_read_32(base + BUILD_CONFIG_OFF); -} - -static uint32_t tzc_read_gate_keeper(uint64_t base) -{ - return mmio_read_32(base + GATE_KEEPER_OFF); -} - -static void tzc_write_gate_keeper(uint64_t base, uint32_t val) -{ - mmio_write_32(base + GATE_KEEPER_OFF, val); -} - -static void tzc_write_action(uint64_t base, enum tzc_action action) -{ - mmio_write_32(base + ACTION_OFF, action); -} - -static void tzc_write_region_base_low(uint64_t base, uint32_t region, uint32_t val) -{ - mmio_write_32(base + REGION_BASE_LOW_OFF + REGION_NUM_OFF(region), val); -} - -static void tzc_write_region_base_high(uint64_t base, uint32_t region, uint32_t val) -{ - mmio_write_32(base + REGION_BASE_HIGH_OFF + REGION_NUM_OFF(region), val); -} - -static void tzc_write_region_top_low(uint64_t base, uint32_t region, uint32_t val) -{ - mmio_write_32(base + REGION_TOP_LOW_OFF + REGION_NUM_OFF(region), val); -} - -static void tzc_write_region_top_high(uint64_t base, uint32_t region, uint32_t val) -{ - mmio_write_32(base + REGION_TOP_HIGH_OFF + REGION_NUM_OFF(region), val); -} - -static void tzc_write_region_attributes(uint64_t base, uint32_t region, uint32_t val) -{ - mmio_write_32(base + REGION_ATTRIBUTES_OFF + REGION_NUM_OFF(region), val); -} - -static void tzc_write_region_id_access(uint64_t base, uint32_t region, uint32_t val) -{ - mmio_write_32(base + REGION_ID_ACCESS_OFF + REGION_NUM_OFF(region), val); -} - -static uint32_t tzc_read_component_id(uint64_t base) -{ - uint32_t id; - - id = mmio_read_8(base + CID0_OFF); - id |= (mmio_read_8(base + CID1_OFF) << 8); - id |= (mmio_read_8(base + CID2_OFF) << 16); - id |= (mmio_read_8(base + CID3_OFF) << 24); - - return id; -} - -static uint32_t tzc_get_gate_keeper(uint64_t base, uint8_t filter) -{ - uint32_t tmp; - - tmp = (tzc_read_gate_keeper(base) >> GATE_KEEPER_OS_SHIFT) & - GATE_KEEPER_OS_MASK; - - return tmp >> filter; -} - -/* This function is not MP safe. */ -static void tzc_set_gate_keeper(uint64_t base, uint8_t filter, uint32_t val) -{ - uint32_t tmp; - - /* Upper half is current state. Lower half is requested state. */ - tmp = (tzc_read_gate_keeper(base) >> GATE_KEEPER_OS_SHIFT) & - GATE_KEEPER_OS_MASK; - - if (val) - tmp |= (1 << filter); - else - tmp &= ~(1 << filter); - - tzc_write_gate_keeper(base, (tmp & GATE_KEEPER_OR_MASK) << - GATE_KEEPER_OR_SHIFT); - - /* Wait here until we see the change reflected in the TZC status. */ - while (((tzc_read_gate_keeper(base) >> GATE_KEEPER_OS_SHIFT) & - GATE_KEEPER_OS_MASK) != tmp) - ; -} - - -void tzc_init(struct tzc_instance *controller) -{ - uint32_t tzc_id, tzc_build; - - assert(controller != NULL); - - /* - * We expect to see a tzc400. Check component ID. The TZC-400 TRM shows - * component ID is expected to be "0xB105F00D". - */ - tzc_id = tzc_read_component_id(controller->base); - if (tzc_id != TZC400_COMPONENT_ID) { - ERROR("TZC : Wrong device ID (0x%x).\n", tzc_id); - panic(); - } - - /* Save values we will use later. */ - tzc_build = tzc_read_build_config(controller->base); - controller->num_filters = ((tzc_build >> BUILD_CONFIG_NF_SHIFT) & - BUILD_CONFIG_NF_MASK) + 1; - controller->addr_width = ((tzc_build >> BUILD_CONFIG_AW_SHIFT) & - BUILD_CONFIG_AW_MASK) + 1; - controller->num_regions = ((tzc_build >> BUILD_CONFIG_NR_SHIFT) & - BUILD_CONFIG_NR_MASK) + 1; -} - - -/* - * `tzc_configure_region` is used to program regions into the TrustZone - * controller. A region can be associated with more than one filter. The - * associated filters are passed in as a bitmap (bit0 = filter0). - * NOTE: - * The region 0 covers the whole address space and is enabled on all filters, - * this cannot be changed. It is, however, possible to change some region 0 - * permissions. - */ -void tzc_configure_region(const struct tzc_instance *controller, - uint32_t filters, - uint8_t region, - uint64_t region_base, - uint64_t region_top, - enum tzc_region_attributes sec_attr, - uint32_t ns_device_access) -{ - uint64_t max_addr; - - assert(controller != NULL); - - /* Do range checks on filters and regions. */ - assert(((filters >> controller->num_filters) == 0) && - (region < controller->num_regions)); - - /* - * Do address range check based on TZC configuration. A 64bit address is - * the max and expected case. - */ - max_addr = UINT64_MAX >> (64 - controller->addr_width); - if ((region_top > max_addr) || (region_base >= region_top)) - assert(0); - - /* region_base and (region_top + 1) must be 4KB aligned */ - assert(((region_base | (region_top + 1)) & (4096 - 1)) == 0); - - assert(sec_attr <= TZC_REGION_S_RDWR); - - /* - * Inputs look ok, start programming registers. - * All the address registers are 32 bits wide and have a LOW and HIGH - * component used to construct a up to a 64bit address. - */ - tzc_write_region_base_low(controller->base, region, (uint32_t)(region_base)); - tzc_write_region_base_high(controller->base, region, (uint32_t)(region_base >> 32)); - - tzc_write_region_top_low(controller->base, region, (uint32_t)(region_top)); - tzc_write_region_top_high(controller->base, region, (uint32_t)(region_top >> 32)); - - /* Assign the region to a filter and set secure attributes */ - tzc_write_region_attributes(controller->base, region, - (sec_attr << REGION_ATTRIBUTES_SEC_SHIFT) | filters); - - /* - * Specify which non-secure devices have permission to access this - * region. - */ - tzc_write_region_id_access(controller->base, region, ns_device_access); -} - - -void tzc_set_action(const struct tzc_instance *controller, enum tzc_action action) -{ - assert(controller != NULL); - - /* - * - Currently no handler is provided to trap an error via interrupt - * or exception. - * - The interrupt action has not been tested. - */ - tzc_write_action(controller->base, action); -} - - -void tzc_enable_filters(const struct tzc_instance *controller) -{ - uint32_t state; - uint32_t filter; - - assert(controller != NULL); - - for (filter = 0; filter < controller->num_filters; filter++) { - state = tzc_get_gate_keeper(controller->base, filter); - if (state) { - ERROR("TZC : Filter %d Gatekeeper already enabled.\n", - filter); - panic(); - } - tzc_set_gate_keeper(controller->base, filter, 1); - } -} - - -void tzc_disable_filters(const struct tzc_instance *controller) -{ - uint32_t filter; - - assert(controller != NULL); - - /* - * We don't do the same state check as above as the Gatekeepers are - * disabled after reset. - */ - for (filter = 0; filter < controller->num_filters; filter++) - tzc_set_gate_keeper(controller->base, filter, 0); -} diff --git a/drivers/arm/interconnect/tzc-400/tzc400.h b/drivers/arm/interconnect/tzc-400/tzc400.h deleted file mode 100644 index 7eaafd2..0000000 --- a/drivers/arm/interconnect/tzc-400/tzc400.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __TZC400_H__ -#define __TZC400_H__ - -#include - -#define BUILD_CONFIG_OFF 0x000 -#define ACTION_OFF 0x004 -#define GATE_KEEPER_OFF 0x008 -#define SPECULATION_CTRL_OFF 0x00c -#define INT_STATUS 0x010 -#define INT_CLEAR 0x014 - -#define FAIL_ADDRESS_LOW_OFF 0x020 -#define FAIL_ADDRESS_HIGH_OFF 0x024 -#define FAIL_CONTROL_OFF 0x028 -#define FAIL_ID 0x02c - -#define REGION_BASE_LOW_OFF 0x100 -#define REGION_BASE_HIGH_OFF 0x104 -#define REGION_TOP_LOW_OFF 0x108 -#define REGION_TOP_HIGH_OFF 0x10c -#define REGION_ATTRIBUTES_OFF 0x110 -#define REGION_ID_ACCESS_OFF 0x114 -#define REGION_NUM_OFF(region) (0x20 * region) - -/* ID Registers */ -#define PID0_OFF 0xfe0 -#define PID1_OFF 0xfe4 -#define PID2_OFF 0xfe8 -#define PID3_OFF 0xfec -#define PID4_OFF 0xfd0 -#define PID5_OFF 0xfd4 -#define PID6_OFF 0xfd8 -#define PID7_OFF 0xfdc -#define CID0_OFF 0xff0 -#define CID1_OFF 0xff4 -#define CID2_OFF 0xff8 -#define CID3_OFF 0xffc - -#define BUILD_CONFIG_NF_SHIFT 24 -#define BUILD_CONFIG_NF_MASK 0x3 -#define BUILD_CONFIG_AW_SHIFT 8 -#define BUILD_CONFIG_AW_MASK 0x3f -#define BUILD_CONFIG_NR_SHIFT 0 -#define BUILD_CONFIG_NR_MASK 0x1f - -/* Not describing the case where regions 1 to 8 overlap */ -#define ACTION_RV_SHIFT 0 -#define ACTION_RV_MASK 0x3 -#define ACTION_RV_LOWOK 0x0 -#define ACTION_RV_LOWERR 0x1 -#define ACTION_RV_HIGHOK 0x2 -#define ACTION_RV_HIGHERR 0x3 - -/* - * Number of gate keepers is implementation defined. But we know the max for - * this device is 4. Get implementation details from BUILD_CONFIG. - */ -#define GATE_KEEPER_OS_SHIFT 16 -#define GATE_KEEPER_OS_MASK 0xf -#define GATE_KEEPER_OR_SHIFT 0 -#define GATE_KEEPER_OR_MASK 0xf - -/* Speculation is enabled by default. */ -#define SPECULATION_CTRL_WRITE_DISABLE (1 << 1) -#define SPECULATION_CTRL_READ_DISABLE (1 << 0) - -/* Max number of filters allowed is 4. */ -#define INT_STATUS_OVERLAP_SHIFT 16 -#define INT_STATUS_OVERLAP_MASK 0xf -#define INT_STATUS_OVERRUN_SHIFT 8 -#define INT_STATUS_OVERRUN_MASK 0xf -#define INT_STATUS_STATUS_SHIFT 0 -#define INT_STATUS_STATUS_MASK 0xf - -#define INT_CLEAR_CLEAR_SHIFT 0 -#define INT_CLEAR_CLEAR_MASK 0xf - -#define FAIL_CONTROL_DIR_SHIFT (1 << 24) -#define FAIL_CONTROL_DIR_READ 0x0 -#define FAIL_CONTROL_DIR_WRITE 0x1 -#define FAIL_CONTROL_NS_SHIFT (1 << 21) -#define FAIL_CONTROL_NS_SECURE 0x0 -#define FAIL_CONTROL_NS_NONSECURE 0x1 -#define FAIL_CONTROL_PRIV_SHIFT (1 << 20) -#define FAIL_CONTROL_PRIV_PRIV 0x0 -#define FAIL_CONTROL_PRIV_UNPRIV 0x1 - -/* - * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific. - * Platform should provide the value on initialisation. - */ -#define FAIL_ID_VNET_SHIFT 24 -#define FAIL_ID_VNET_MASK 0xf -#define FAIL_ID_ID_SHIFT 0 - -/* Used along with 'tzc_region_attributes_t' below */ -#define REGION_ATTRIBUTES_SEC_SHIFT 30 -#define REGION_ATTRIBUTES_F_EN_SHIFT 0 -#define REGION_ATTRIBUTES_F_EN_MASK 0xf - -#define REGION_ID_ACCESS_NSAID_WR_EN_SHIFT 16 -#define REGION_ID_ACCESS_NSAID_RD_EN_SHIFT 0 -#define REGION_ID_ACCESS_NSAID_ID_MASK 0xf - - -/* Macros for setting Region ID access permissions based on NSAID */ -#define TZC_REGION_ACCESS_RD(id) \ - ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \ - REGION_ID_ACCESS_NSAID_RD_EN_SHIFT) -#define TZC_REGION_ACCESS_WR(id) \ - ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \ - REGION_ID_ACCESS_NSAID_WR_EN_SHIFT) -#define TZC_REGION_ACCESS_RDWR(id) \ - (TZC_REGION_ACCESS_RD(id) | TZC_REGION_ACCESS_WR(id)) - -/* Filters are bit mapped 0 to 3. */ -#define TZC400_COMPONENT_ID 0xb105f00d - -#ifndef __ASSEMBLY__ - -/******************************************************************************* - * Function & variable prototypes - ******************************************************************************/ - -/* - * What type of action is expected when an access violation occurs. - * The memory requested is zeroed. But we can also raise and event to - * let the system know it happened. - * We can raise an interrupt(INT) and/or cause an exception(ERR). - * TZC_ACTION_NONE - No interrupt, no Exception - * TZC_ACTION_ERR - No interrupt, raise exception -> sync external - * data abort - * TZC_ACTION_INT - Raise interrupt, no exception - * TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync - * external data abort - */ -enum tzc_action { - TZC_ACTION_NONE = 0, - TZC_ACTION_ERR = 1, - TZC_ACTION_INT = 2, - TZC_ACTION_ERR_INT = (TZC_ACTION_ERR | TZC_ACTION_INT) -}; - -/* - * Controls secure access to a region. If not enabled secure access is not - * allowed to region. - */ -enum tzc_region_attributes { - TZC_REGION_S_NONE = 0, - TZC_REGION_S_RD = 1, - TZC_REGION_S_WR = 2, - TZC_REGION_S_RDWR = (TZC_REGION_S_RD | TZC_REGION_S_WR) -}; - -/* - * Implementation defined values used to validate inputs later. - * Filters : max of 4 ; 0 to 3 - * Regions : max of 9 ; 0 to 8 - * Address width : Values between 32 to 64 - */ -struct tzc_instance { - uint64_t base; - uint32_t aid_width; - uint8_t addr_width; - uint8_t num_filters; - uint8_t num_regions; -}; - -void tzc_init(struct tzc_instance *controller); -void tzc_configure_region(const struct tzc_instance *controller, uint32_t filters, - uint8_t region, uint64_t region_base, uint64_t region_top, - enum tzc_region_attributes sec_attr, uint32_t ns_device_access); -void tzc_enable_filters(const struct tzc_instance *controller); -void tzc_disable_filters(const struct tzc_instance *controller); -void tzc_set_action(const struct tzc_instance *controller, - enum tzc_action action); - -#endif /*__ASSEMBLY__*/ - -#endif /* __TZC400__ */ diff --git a/drivers/arm/peripherals/pl011/pl011.c b/drivers/arm/peripherals/pl011/pl011.c deleted file mode 100644 index 8288cd8..0000000 --- a/drivers/arm/peripherals/pl011/pl011.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - -void pl011_setbaudrate(unsigned long base_addr, unsigned int baudrate) -{ - unsigned int divisor; - assert(baudrate); - divisor = (PL011_CLK_IN_HZ * 4) / baudrate; - pl011_write_ibrd(base_addr, divisor >> 6); - pl011_write_fbrd(base_addr, divisor & 0x3F); -} diff --git a/drivers/arm/peripherals/pl011/pl011.h b/drivers/arm/peripherals/pl011/pl011.h deleted file mode 100644 index 5ad2fc7..0000000 --- a/drivers/arm/peripherals/pl011/pl011.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __PL011_H__ -#define __PL011_H__ - -/* PL011 Registers */ -#define UARTDR 0x000 -#define UARTRSR 0x004 -#define UARTECR 0x004 -#define UARTFR 0x018 -#define UARTILPR 0x020 -#define UARTIBRD 0x024 -#define UARTFBRD 0x028 -#define UARTLCR_H 0x02C -#define UARTCR 0x030 -#define UARTIFLS 0x034 -#define UARTIMSC 0x038 -#define UARTRIS 0x03C -#define UARTMIS 0x040 -#define UARTICR 0x044 -#define UARTDMACR 0x048 - -/* Data status bits */ -#define UART_DATA_ERROR_MASK 0x0F00 - -/* Status reg bits */ -#define UART_STATUS_ERROR_MASK 0x0F - -/* Flag reg bits */ -#define PL011_UARTFR_RI (1 << 8) /* Ring indicator */ -#define PL011_UARTFR_TXFE (1 << 7) /* Transmit FIFO empty */ -#define PL011_UARTFR_RXFF (1 << 6) /* Receive FIFO full */ -#define PL011_UARTFR_TXFF (1 << 5) /* Transmit FIFO full */ -#define PL011_UARTFR_RXFE (1 << 4) /* Receive FIFO empty */ -#define PL011_UARTFR_BUSY (1 << 3) /* UART busy */ -#define PL011_UARTFR_DCD (1 << 2) /* Data carrier detect */ -#define PL011_UARTFR_DSR (1 << 1) /* Data set ready */ -#define PL011_UARTFR_CTS (1 << 0) /* Clear to send */ - -/* Control reg bits */ -#define PL011_UARTCR_CTSEN (1 << 15) /* CTS hardware flow control enable */ -#define PL011_UARTCR_RTSEN (1 << 14) /* RTS hardware flow control enable */ -#define PL011_UARTCR_RTS (1 << 11) /* Request to send */ -#define PL011_UARTCR_DTR (1 << 10) /* Data transmit ready. */ -#define PL011_UARTCR_RXE (1 << 9) /* Receive enable */ -#define PL011_UARTCR_TXE (1 << 8) /* Transmit enable */ -#define PL011_UARTCR_LBE (1 << 7) /* Loopback enable */ -#define PL011_UARTCR_UARTEN (1 << 0) /* UART Enable */ - -#if !defined(PL011_BASE) -#error "The PL011_BASE macro must be defined." -#endif - -#if !defined(PL011_BAUDRATE) -#define PL011_BAUDRATE 115200 -#endif - -#if !defined(PL011_CLK_IN_HZ) -#define PL011_CLK_IN_HZ 24000000 -#endif - -#if !defined(PL011_LINE_CONTROL) -/* FIFO Enabled / No Parity / 8 Data bit / One Stop Bit */ -#define PL011_LINE_CONTROL (PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8) -#endif - -/* Line Control Register Bits */ -#define PL011_UARTLCR_H_SPS (1 << 7) /* Stick parity select */ -#define PL011_UARTLCR_H_WLEN_8 (3 << 5) -#define PL011_UARTLCR_H_WLEN_7 (2 << 5) -#define PL011_UARTLCR_H_WLEN_6 (1 << 5) -#define PL011_UARTLCR_H_WLEN_5 (0 << 5) -#define PL011_UARTLCR_H_FEN (1 << 4) /* FIFOs Enable */ -#define PL011_UARTLCR_H_STP2 (1 << 3) /* Two stop bits select */ -#define PL011_UARTLCR_H_EPS (1 << 2) /* Even parity select */ -#define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */ -#define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */ - -/******************************************************************************* - * Pl011 CPU interface accessors for writing registers - ******************************************************************************/ - -static inline void pl011_write_ibrd(unsigned int base, unsigned int val) -{ - mmio_write_32(base + UARTIBRD, val); -} - -static inline void pl011_write_fbrd(unsigned int base, unsigned int val) -{ - mmio_write_32(base + UARTFBRD, val); -} - -static inline void pl011_write_lcr_h(unsigned int base, unsigned int val) -{ - mmio_write_32(base + UARTLCR_H, val); -} - -static inline void pl011_write_ecr(unsigned int base, unsigned int val) -{ - mmio_write_32(base + UARTECR, val); -} - -static inline void pl011_write_cr(unsigned int base, unsigned int val) -{ - mmio_write_32(base + UARTCR, val); -} - -static inline void pl011_write_dr(unsigned int base, unsigned int val) -{ - mmio_write_32(base + UARTDR, val); -} - -/******************************************************************************* - * Pl011 CPU interface accessors for reading registers - ******************************************************************************/ - -static inline unsigned int pl011_read_fr(unsigned int base) -{ - return mmio_read_32(base + UARTFR); -} - -static inline unsigned int pl011_read_dr(unsigned int base) -{ - return mmio_read_32(base + UARTDR); -} - -/******************************************************************************* - * Function prototypes - ******************************************************************************/ - -void pl011_setbaudrate(unsigned long base_addr, unsigned int baudrate); - -#endif /* __PL011_H__ */ diff --git a/drivers/arm/peripherals/pl011/pl011_console.c b/drivers/arm/peripherals/pl011/pl011_console.c deleted file mode 100644 index 1a684ff..0000000 --- a/drivers/arm/peripherals/pl011/pl011_console.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include - -static unsigned long uart_base; - -void console_init(unsigned long base_addr) -{ - /* TODO: assert() internally calls printf() and will result in - * an infinite loop. This needs to be fixed with some kind of - * exception mechanism or early panic support. This also applies - * to the other assert() calls below. - */ - assert(base_addr); - - /* Initialise internal base address variable */ - uart_base = base_addr; - - /* Baud Rate */ -#if defined(PL011_INTEGER) && defined(PL011_FRACTIONAL) - pl011_write_ibrd(uart_base, PL011_INTEGER); - pl011_write_fbrd(uart_base, PL011_FRACTIONAL); -#else - pl011_setbaudrate(uart_base, PL011_BAUDRATE); -#endif - - pl011_write_lcr_h(uart_base, PL011_LINE_CONTROL); - - /* Clear any pending errors */ - pl011_write_ecr(uart_base, 0); - - /* Enable tx, rx, and uart overall */ - pl011_write_cr(uart_base, PL011_UARTCR_RXE | PL011_UARTCR_TXE | - PL011_UARTCR_UARTEN); - -} - -int console_putc(int c) -{ - assert(uart_base); - - if (c == '\n') - console_putc('\r'); - - while ((pl011_read_fr(uart_base) & PL011_UARTFR_TXFF) == 1) - ; - pl011_write_dr(uart_base, c); - return c; -} - -int console_getc(void) -{ - assert(uart_base); - - while ((pl011_read_fr(uart_base) & PL011_UARTFR_RXFE) != 0) - ; - return pl011_read_dr(uart_base); -} diff --git a/drivers/arm/pl011/pl011.c b/drivers/arm/pl011/pl011.c new file mode 100644 index 0000000..8288cd8 --- /dev/null +++ b/drivers/arm/pl011/pl011.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +void pl011_setbaudrate(unsigned long base_addr, unsigned int baudrate) +{ + unsigned int divisor; + assert(baudrate); + divisor = (PL011_CLK_IN_HZ * 4) / baudrate; + pl011_write_ibrd(base_addr, divisor >> 6); + pl011_write_fbrd(base_addr, divisor & 0x3F); +} diff --git a/drivers/arm/pl011/pl011_console.c b/drivers/arm/pl011/pl011_console.c new file mode 100644 index 0000000..1a684ff --- /dev/null +++ b/drivers/arm/pl011/pl011_console.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +static unsigned long uart_base; + +void console_init(unsigned long base_addr) +{ + /* TODO: assert() internally calls printf() and will result in + * an infinite loop. This needs to be fixed with some kind of + * exception mechanism or early panic support. This also applies + * to the other assert() calls below. + */ + assert(base_addr); + + /* Initialise internal base address variable */ + uart_base = base_addr; + + /* Baud Rate */ +#if defined(PL011_INTEGER) && defined(PL011_FRACTIONAL) + pl011_write_ibrd(uart_base, PL011_INTEGER); + pl011_write_fbrd(uart_base, PL011_FRACTIONAL); +#else + pl011_setbaudrate(uart_base, PL011_BAUDRATE); +#endif + + pl011_write_lcr_h(uart_base, PL011_LINE_CONTROL); + + /* Clear any pending errors */ + pl011_write_ecr(uart_base, 0); + + /* Enable tx, rx, and uart overall */ + pl011_write_cr(uart_base, PL011_UARTCR_RXE | PL011_UARTCR_TXE | + PL011_UARTCR_UARTEN); + +} + +int console_putc(int c) +{ + assert(uart_base); + + if (c == '\n') + console_putc('\r'); + + while ((pl011_read_fr(uart_base) & PL011_UARTFR_TXFF) == 1) + ; + pl011_write_dr(uart_base, c); + return c; +} + +int console_getc(void) +{ + assert(uart_base); + + while ((pl011_read_fr(uart_base) & PL011_UARTFR_RXFE) != 0) + ; + return pl011_read_dr(uart_base); +} diff --git a/drivers/arm/tzc400/tzc400.c b/drivers/arm/tzc400/tzc400.c new file mode 100644 index 0000000..b88e34a --- /dev/null +++ b/drivers/arm/tzc400/tzc400.c @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "arch_helpers.h" +#include "tzc400.h" +#include "mmio.h" +#include "debug.h" + +static uint32_t tzc_read_build_config(uint64_t base) +{ + return mmio_read_32(base + BUILD_CONFIG_OFF); +} + +static uint32_t tzc_read_gate_keeper(uint64_t base) +{ + return mmio_read_32(base + GATE_KEEPER_OFF); +} + +static void tzc_write_gate_keeper(uint64_t base, uint32_t val) +{ + mmio_write_32(base + GATE_KEEPER_OFF, val); +} + +static void tzc_write_action(uint64_t base, enum tzc_action action) +{ + mmio_write_32(base + ACTION_OFF, action); +} + +static void tzc_write_region_base_low(uint64_t base, uint32_t region, uint32_t val) +{ + mmio_write_32(base + REGION_BASE_LOW_OFF + REGION_NUM_OFF(region), val); +} + +static void tzc_write_region_base_high(uint64_t base, uint32_t region, uint32_t val) +{ + mmio_write_32(base + REGION_BASE_HIGH_OFF + REGION_NUM_OFF(region), val); +} + +static void tzc_write_region_top_low(uint64_t base, uint32_t region, uint32_t val) +{ + mmio_write_32(base + REGION_TOP_LOW_OFF + REGION_NUM_OFF(region), val); +} + +static void tzc_write_region_top_high(uint64_t base, uint32_t region, uint32_t val) +{ + mmio_write_32(base + REGION_TOP_HIGH_OFF + REGION_NUM_OFF(region), val); +} + +static void tzc_write_region_attributes(uint64_t base, uint32_t region, uint32_t val) +{ + mmio_write_32(base + REGION_ATTRIBUTES_OFF + REGION_NUM_OFF(region), val); +} + +static void tzc_write_region_id_access(uint64_t base, uint32_t region, uint32_t val) +{ + mmio_write_32(base + REGION_ID_ACCESS_OFF + REGION_NUM_OFF(region), val); +} + +static uint32_t tzc_read_component_id(uint64_t base) +{ + uint32_t id; + + id = mmio_read_8(base + CID0_OFF); + id |= (mmio_read_8(base + CID1_OFF) << 8); + id |= (mmio_read_8(base + CID2_OFF) << 16); + id |= (mmio_read_8(base + CID3_OFF) << 24); + + return id; +} + +static uint32_t tzc_get_gate_keeper(uint64_t base, uint8_t filter) +{ + uint32_t tmp; + + tmp = (tzc_read_gate_keeper(base) >> GATE_KEEPER_OS_SHIFT) & + GATE_KEEPER_OS_MASK; + + return tmp >> filter; +} + +/* This function is not MP safe. */ +static void tzc_set_gate_keeper(uint64_t base, uint8_t filter, uint32_t val) +{ + uint32_t tmp; + + /* Upper half is current state. Lower half is requested state. */ + tmp = (tzc_read_gate_keeper(base) >> GATE_KEEPER_OS_SHIFT) & + GATE_KEEPER_OS_MASK; + + if (val) + tmp |= (1 << filter); + else + tmp &= ~(1 << filter); + + tzc_write_gate_keeper(base, (tmp & GATE_KEEPER_OR_MASK) << + GATE_KEEPER_OR_SHIFT); + + /* Wait here until we see the change reflected in the TZC status. */ + while (((tzc_read_gate_keeper(base) >> GATE_KEEPER_OS_SHIFT) & + GATE_KEEPER_OS_MASK) != tmp) + ; +} + + +void tzc_init(struct tzc_instance *controller) +{ + uint32_t tzc_id, tzc_build; + + assert(controller != NULL); + + /* + * We expect to see a tzc400. Check component ID. The TZC-400 TRM shows + * component ID is expected to be "0xB105F00D". + */ + tzc_id = tzc_read_component_id(controller->base); + if (tzc_id != TZC400_COMPONENT_ID) { + ERROR("TZC : Wrong device ID (0x%x).\n", tzc_id); + panic(); + } + + /* Save values we will use later. */ + tzc_build = tzc_read_build_config(controller->base); + controller->num_filters = ((tzc_build >> BUILD_CONFIG_NF_SHIFT) & + BUILD_CONFIG_NF_MASK) + 1; + controller->addr_width = ((tzc_build >> BUILD_CONFIG_AW_SHIFT) & + BUILD_CONFIG_AW_MASK) + 1; + controller->num_regions = ((tzc_build >> BUILD_CONFIG_NR_SHIFT) & + BUILD_CONFIG_NR_MASK) + 1; +} + + +/* + * `tzc_configure_region` is used to program regions into the TrustZone + * controller. A region can be associated with more than one filter. The + * associated filters are passed in as a bitmap (bit0 = filter0). + * NOTE: + * The region 0 covers the whole address space and is enabled on all filters, + * this cannot be changed. It is, however, possible to change some region 0 + * permissions. + */ +void tzc_configure_region(const struct tzc_instance *controller, + uint32_t filters, + uint8_t region, + uint64_t region_base, + uint64_t region_top, + enum tzc_region_attributes sec_attr, + uint32_t ns_device_access) +{ + uint64_t max_addr; + + assert(controller != NULL); + + /* Do range checks on filters and regions. */ + assert(((filters >> controller->num_filters) == 0) && + (region < controller->num_regions)); + + /* + * Do address range check based on TZC configuration. A 64bit address is + * the max and expected case. + */ + max_addr = UINT64_MAX >> (64 - controller->addr_width); + if ((region_top > max_addr) || (region_base >= region_top)) + assert(0); + + /* region_base and (region_top + 1) must be 4KB aligned */ + assert(((region_base | (region_top + 1)) & (4096 - 1)) == 0); + + assert(sec_attr <= TZC_REGION_S_RDWR); + + /* + * Inputs look ok, start programming registers. + * All the address registers are 32 bits wide and have a LOW and HIGH + * component used to construct a up to a 64bit address. + */ + tzc_write_region_base_low(controller->base, region, (uint32_t)(region_base)); + tzc_write_region_base_high(controller->base, region, (uint32_t)(region_base >> 32)); + + tzc_write_region_top_low(controller->base, region, (uint32_t)(region_top)); + tzc_write_region_top_high(controller->base, region, (uint32_t)(region_top >> 32)); + + /* Assign the region to a filter and set secure attributes */ + tzc_write_region_attributes(controller->base, region, + (sec_attr << REGION_ATTRIBUTES_SEC_SHIFT) | filters); + + /* + * Specify which non-secure devices have permission to access this + * region. + */ + tzc_write_region_id_access(controller->base, region, ns_device_access); +} + + +void tzc_set_action(const struct tzc_instance *controller, enum tzc_action action) +{ + assert(controller != NULL); + + /* + * - Currently no handler is provided to trap an error via interrupt + * or exception. + * - The interrupt action has not been tested. + */ + tzc_write_action(controller->base, action); +} + + +void tzc_enable_filters(const struct tzc_instance *controller) +{ + uint32_t state; + uint32_t filter; + + assert(controller != NULL); + + for (filter = 0; filter < controller->num_filters; filter++) { + state = tzc_get_gate_keeper(controller->base, filter); + if (state) { + ERROR("TZC : Filter %d Gatekeeper already enabled.\n", + filter); + panic(); + } + tzc_set_gate_keeper(controller->base, filter, 1); + } +} + + +void tzc_disable_filters(const struct tzc_instance *controller) +{ + uint32_t filter; + + assert(controller != NULL); + + /* + * We don't do the same state check as above as the Gatekeepers are + * disabled after reset. + */ + for (filter = 0; filter < controller->num_filters; filter++) + tzc_set_gate_keeper(controller->base, filter, 0); +} diff --git a/drivers/console/console.h b/drivers/console/console.h deleted file mode 100644 index e285909..0000000 --- a/drivers/console/console.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __CONSOLE_H__ -#define __CONSOLE_H__ - -void console_init(unsigned long base_addr); -int console_putc(int c); -int console_getc(void); - -#endif /* __CONSOLE_H__ */ - diff --git a/drivers/io/io_driver.h b/drivers/io/io_driver.h deleted file mode 100644 index 82dbbf1..0000000 --- a/drivers/io/io_driver.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __IO_DRIVER_H__ -#define __IO_DRIVER_H__ - -#include "platform.h" /* For MAX_IO_DEVICES */ - - -/* Generic IO entity structure,representing an accessible IO construct on the - * device, such as a file */ -struct io_entity { - io_dev_handle dev_handle; - uintptr_t info; -}; - - -/* Device info structure, providing device-specific functions and a means of - * adding driver-specific state */ -struct io_dev_info { - struct io_dev_funcs *funcs; - uintptr_t info; -}; - - -/* Structure used to create a connection to a type of device */ -struct io_dev_connector { - /* dev_open opens a connection to a particular device driver */ - int (*dev_open)(void *spec, struct io_dev_info **dev_info); -}; - - -/* Structure to hold device driver function pointers */ -struct io_dev_funcs { - io_type (*type)(void); - int (*open)(struct io_dev_info *dev_info, const void *spec, - struct io_entity *entity); - int (*seek)(struct io_entity *entity, int mode, ssize_t offset); - int (*size)(struct io_entity *entity, size_t *length); - int (*read)(struct io_entity *entity, void *buffer, size_t length, - size_t *length_read); - int (*write)(struct io_entity *entity, const void *buffer, - size_t length, size_t *length_written); - int (*close)(struct io_entity *entity); - int (*dev_init)(struct io_dev_info *dev_info, const void *init_params); - int (*dev_close)(struct io_dev_info *dev_info); -}; - - -/* IO platform data - used to track devices registered for a specific - * platform */ -struct io_plat_data { - struct io_dev_info *devices[MAX_IO_DEVICES]; - unsigned int dev_count; -}; - - -/* Operations intended to be performed during platform initialisation */ - -/* Initialise the IO layer */ -void io_init(struct io_plat_data *data); - -/* Register a device driver */ -int io_register_device(struct io_dev_info *dev_info); - -#endif /* __IO_DRIVER_H__ */ diff --git a/drivers/io/io_fip.h b/drivers/io/io_fip.h deleted file mode 100644 index 56dd1e0..0000000 --- a/drivers/io/io_fip.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2014 ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __IO_FIP_H__ -#define __IO_FIP_H__ - -int register_io_dev_fip(struct io_dev_connector **dev_con); - -#endif /* __IO_FIP_H__ */ diff --git a/drivers/io/io_memmap.h b/drivers/io/io_memmap.h deleted file mode 100644 index 5fa7bc9..0000000 --- a/drivers/io/io_memmap.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __IO_MEMMAP_H__ -#define __IO_MEMMAP_H__ - -int register_io_dev_memmap(struct io_dev_connector **dev_con); - -#endif /* __IO_MEMMAP_H__ */ diff --git a/drivers/io/io_semihosting.h b/drivers/io/io_semihosting.h deleted file mode 100644 index 7dc632d..0000000 --- a/drivers/io/io_semihosting.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __IO_SH_H__ -#define __IO_SH_H__ - -int register_io_dev_sh(struct io_dev_connector **dev_con); - -#endif /* __IO_SH_H__ */ diff --git a/drivers/power/fvp_pwrc.h b/drivers/power/fvp_pwrc.h deleted file mode 100644 index f600a24..0000000 --- a/drivers/power/fvp_pwrc.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __FVP_PWRC_H__ -#define __FVP_PWRC_H__ - -/* FVP Power controller register offset etc */ -#define PPOFFR_OFF 0x0 -#define PPONR_OFF 0x4 -#define PCOFFR_OFF 0x8 -#define PWKUPR_OFF 0xc -#define PSYSR_OFF 0x10 - -#define PWKUPR_WEN (1ull << 31) - -#define PSYSR_AFF_L2 (1 << 31) -#define PSYSR_AFF_L1 (1 << 30) -#define PSYSR_AFF_L0 (1 << 29) -#define PSYSR_WEN (1 << 28) -#define PSYSR_PC (1 << 27) -#define PSYSR_PP (1 << 26) - -#define PSYSR_WK_SHIFT 24 -#define PSYSR_WK_MASK 0x3 -#define PSYSR_WK(x) (x >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK - -#define WKUP_COLD 0x0 -#define WKUP_RESET 0x1 -#define WKUP_PPONR 0x2 -#define WKUP_GICREQ 0x3 - -#define PSYSR_INVALID 0xffffffff - -#ifndef __ASSEMBLY__ - -/******************************************************************************* - * Function & variable prototypes - ******************************************************************************/ -extern int fvp_pwrc_setup(void); -extern void fvp_pwrc_write_pcoffr(unsigned long); -extern void fvp_pwrc_write_ppoffr(unsigned long); -extern void fvp_pwrc_write_pponr(unsigned long); -extern void fvp_pwrc_set_wen(unsigned long); -extern void fvp_pwrc_clr_wen(unsigned long); -extern unsigned int fvp_pwrc_read_psysr(unsigned long); -extern unsigned int fvp_pwrc_get_cpu_wkr(unsigned long); - -#endif /*__ASSEMBLY__*/ - -#endif /* __FVP_PWRC_H__ */ diff --git a/include/aarch64/arch.h b/include/aarch64/arch.h deleted file mode 100644 index a41e82b..0000000 --- a/include/aarch64/arch.h +++ /dev/null @@ -1,345 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __ARCH_H__ -#define __ARCH_H__ - -#include - -/******************************************************************************* - * MIDR bit definitions - ******************************************************************************/ -#define MIDR_PN_MASK 0xfff -#define MIDR_PN_SHIFT 0x4 -#define MIDR_PN_AEM 0xd0f -#define MIDR_PN_A57 0xd07 -#define MIDR_PN_A53 0xd03 - -/******************************************************************************* - * MPIDR macros - ******************************************************************************/ -#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK -#define MPIDR_CLUSTER_MASK MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS -#define MPIDR_AFFINITY_BITS 8 -#define MPIDR_AFFLVL_MASK 0xff -#define MPIDR_AFF0_SHIFT 0 -#define MPIDR_AFF1_SHIFT 8 -#define MPIDR_AFF2_SHIFT 16 -#define MPIDR_AFF3_SHIFT 32 -#define MPIDR_AFFINITY_MASK 0xff00ffffff -#define MPIDR_AFFLVL_SHIFT 3 -#define MPIDR_AFFLVL0 0 -#define MPIDR_AFFLVL1 1 -#define MPIDR_AFFLVL2 2 -#define MPIDR_AFFLVL3 3 -/* TODO: Support only the first 3 affinity levels for now */ -#define MPIDR_MAX_AFFLVL 2 - -/* Constant to highlight the assumption that MPIDR allocation starts from 0 */ -#define FIRST_MPIDR 0 - -/******************************************************************************* - * Implementation defined sysreg encodings - ******************************************************************************/ -#define CPUECTLR_EL1 S3_1_C15_C2_1 - -/******************************************************************************* - * Generic timer memory mapped registers & offsets - ******************************************************************************/ -#define CNTCR_OFF 0x000 -#define CNTFID_OFF 0x020 - -#define CNTCR_EN (1 << 0) -#define CNTCR_HDBG (1 << 1) -#define CNTCR_FCREQ(x) ((x) << 8) - -/******************************************************************************* - * System register bit definitions - ******************************************************************************/ -/* CLIDR definitions */ -#define LOUIS_SHIFT 21 -#define LOC_SHIFT 24 -#define CLIDR_FIELD_WIDTH 3 - -/* CSSELR definitions */ -#define LEVEL_SHIFT 1 - -/* D$ set/way op type defines */ -#define DCISW 0x0 -#define DCCISW 0x1 -#define DCCSW 0x2 - -/* ID_AA64PFR0_EL1 definitions */ -#define ID_AA64PFR0_EL0_SHIFT 0 -#define ID_AA64PFR0_EL1_SHIFT 4 -#define ID_AA64PFR0_EL2_SHIFT 8 -#define ID_AA64PFR0_EL3_SHIFT 12 -#define ID_AA64PFR0_ELX_MASK 0xf - -/* ID_PFR1_EL1 definitions */ -#define ID_PFR1_VIRTEXT_SHIFT 12 -#define ID_PFR1_VIRTEXT_MASK 0xf -#define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \ - & ID_PFR1_VIRTEXT_MASK) - -/* SCTLR definitions */ -#define SCTLR_EL2_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \ - (1 << 18) | (1 << 16) | (1 << 11) | (1 << 5) | \ - (1 << 4)) - -#define SCTLR_EL1_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \ - (1 << 11)) -#define SCTLR_M_BIT (1 << 0) -#define SCTLR_A_BIT (1 << 1) -#define SCTLR_C_BIT (1 << 2) -#define SCTLR_SA_BIT (1 << 3) -#define SCTLR_B_BIT (1 << 7) -#define SCTLR_Z_BIT (1 << 11) -#define SCTLR_I_BIT (1 << 12) -#define SCTLR_WXN_BIT (1 << 19) -#define SCTLR_EXCEPTION_BITS (0x3 << 6) -#define SCTLR_EE_BIT (1 << 25) - -/* CPUECTLR definitions */ -#define CPUECTLR_SMP_BIT (1 << 6) - -/* CPACR_El1 definitions */ -#define CPACR_EL1_FPEN(x) (x << 20) -#define CPACR_EL1_FP_TRAP_EL0 0x1 -#define CPACR_EL1_FP_TRAP_ALL 0x2 -#define CPACR_EL1_FP_TRAP_NONE 0x3 - -/* SCR definitions */ -#define SCR_RES1_BITS ((1 << 4) | (1 << 5)) -#define SCR_TWE_BIT (1 << 13) -#define SCR_TWI_BIT (1 << 12) -#define SCR_ST_BIT (1 << 11) -#define SCR_RW_BIT (1 << 10) -#define SCR_SIF_BIT (1 << 9) -#define SCR_HCE_BIT (1 << 8) -#define SCR_SMD_BIT (1 << 7) -#define SCR_EA_BIT (1 << 3) -#define SCR_FIQ_BIT (1 << 2) -#define SCR_IRQ_BIT (1 << 1) -#define SCR_NS_BIT (1 << 0) - -/* HCR definitions */ -#define HCR_RW_BIT (1ull << 31) -#define HCR_AMO_BIT (1 << 5) -#define HCR_IMO_BIT (1 << 4) -#define HCR_FMO_BIT (1 << 3) - -/* CNTHCTL_EL2 definitions */ -#define EL1PCEN_BIT (1 << 1) -#define EL1PCTEN_BIT (1 << 0) - -/* CNTKCTL_EL1 definitions */ -#define EL0PTEN_BIT (1 << 9) -#define EL0VTEN_BIT (1 << 8) -#define EL0PCTEN_BIT (1 << 0) -#define EL0VCTEN_BIT (1 << 1) - -/* CPTR_EL3 definitions */ -#define TCPAC_BIT (1 << 31) -#define TTA_BIT (1 << 20) -#define TFP_BIT (1 << 10) - -/* CPSR/SPSR definitions */ -#define DAIF_FIQ_BIT (1 << 0) -#define DAIF_IRQ_BIT (1 << 1) -#define DAIF_ABT_BIT (1 << 2) -#define DAIF_DBG_BIT (1 << 3) -#define PSR_DAIF_SHIFT 0x6 - -/* - * TCR defintions - */ -#define TCR_EL3_RES1 ((1UL << 31) | (1UL << 23)) - -#define TCR_T0SZ_4GB 32 - -#define TCR_RGN_INNER_NC (0x0 << 8) -#define TCR_RGN_INNER_WBA (0x1 << 8) -#define TCR_RGN_INNER_WT (0x2 << 8) -#define TCR_RGN_INNER_WBNA (0x3 << 8) - -#define TCR_RGN_OUTER_NC (0x0 << 10) -#define TCR_RGN_OUTER_WBA (0x1 << 10) -#define TCR_RGN_OUTER_WT (0x2 << 10) -#define TCR_RGN_OUTER_WBNA (0x3 << 10) - -#define TCR_SH_NON_SHAREABLE (0x0 << 12) -#define TCR_SH_OUTER_SHAREABLE (0x2 << 12) -#define TCR_SH_INNER_SHAREABLE (0x3 << 12) - -#define MODE_RW_64 0x0 -#define MODE_RW_32 0x1 -#define MODE_SP_EL0 0x0 -#define MODE_SP_ELX 0x1 -#define MODE_EL3 0x3 -#define MODE_EL2 0x2 -#define MODE_EL1 0x1 -#define MODE_EL0 0x0 - -#define MODE_RW_SHIFT 0x4 -#define MODE_EL_SHIFT 0x2 -#define MODE_SP_SHIFT 0x0 - -#define GET_RW(mode) ((mode >> MODE_RW_SHIFT) & 0x1) -#define GET_EL(mode) ((mode >> MODE_EL_SHIFT) & 0x3) -#define PSR_MODE(rw, el, sp) (rw << MODE_RW_SHIFT | el << MODE_EL_SHIFT \ - | sp << MODE_SP_SHIFT) - -#define SPSR32_EE_BIT (1 << 9) -#define SPSR32_T_BIT (1 << 5) - -#define AARCH32_MODE_SVC 0x13 -#define AARCH32_MODE_HYP 0x1a - -/* Miscellaneous MMU related constants */ -#define NUM_2MB_IN_GB (1 << 9) -#define NUM_4K_IN_2MB (1 << 9) -#define NUM_GB_IN_4GB (1 << 2) - -#define TWO_MB_SHIFT 21 -#define ONE_GB_SHIFT 30 -#define FOUR_KB_SHIFT 12 - -#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT) -#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT) -#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT) - -#define INVALID_DESC 0x0 -#define BLOCK_DESC 0x1 -#define TABLE_DESC 0x3 - -#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT -#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT -#define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT - -#define LEVEL1 1 -#define LEVEL2 2 -#define LEVEL3 3 - -#define XN (1ull << 2) -#define PXN (1ull << 1) -#define CONT_HINT (1ull << 0) - -#define UPPER_ATTRS(x) (x & 0x7) << 52 -#define NON_GLOBAL (1 << 9) -#define ACCESS_FLAG (1 << 8) -#define NSH (0x0 << 6) -#define OSH (0x2 << 6) -#define ISH (0x3 << 6) - -#define PAGE_SIZE_SHIFT FOUR_KB_SHIFT -#define PAGE_SIZE (1 << PAGE_SIZE_SHIFT) -#define PAGE_SIZE_MASK (PAGE_SIZE - 1) -#define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0) - -#define XLAT_ENTRY_SIZE_SHIFT 3 /* Each MMU table entry is 8 bytes (1 << 3) */ -#define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SIZE_SHIFT) - -#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT -#define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT) - -/* Values for number of entries in each MMU translation table */ -#define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT) -#define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT) -#define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1) - -/* Values to convert a memory address to an index into a translation table */ -#define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT -#define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) -#define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) - -/* - * AP[1] bit is ignored by hardware and is - * treated as if it is One in EL2/EL3 - */ -#define AP_RO (0x1 << 5) -#define AP_RW (0x0 << 5) - -#define NS (0x1 << 3) -#define ATTR_SO_INDEX 0x2 -#define ATTR_DEVICE_INDEX 0x1 -#define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0 -#define LOWER_ATTRS(x) (((x) & 0xfff) << 2) -#define ATTR_SO (0x0) -#define ATTR_DEVICE (0x4) -#define ATTR_IWBWA_OWBWA_NTR (0xff) -#define MAIR_ATTR_SET(attr, index) (attr << (index << 3)) - -/* Exception Syndrome register bits and bobs */ -#define ESR_EC_SHIFT 26 -#define ESR_EC_MASK 0x3f -#define ESR_EC_LENGTH 6 -#define EC_UNKNOWN 0x0 -#define EC_WFE_WFI 0x1 -#define EC_AARCH32_CP15_MRC_MCR 0x3 -#define EC_AARCH32_CP15_MRRC_MCRR 0x4 -#define EC_AARCH32_CP14_MRC_MCR 0x5 -#define EC_AARCH32_CP14_LDC_STC 0x6 -#define EC_FP_SIMD 0x7 -#define EC_AARCH32_CP10_MRC 0x8 -#define EC_AARCH32_CP14_MRRC_MCRR 0xc -#define EC_ILLEGAL 0xe -#define EC_AARCH32_SVC 0x11 -#define EC_AARCH32_HVC 0x12 -#define EC_AARCH32_SMC 0x13 -#define EC_AARCH64_SVC 0x15 -#define EC_AARCH64_HVC 0x16 -#define EC_AARCH64_SMC 0x17 -#define EC_AARCH64_SYS 0x18 -#define EC_IABORT_LOWER_EL 0x20 -#define EC_IABORT_CUR_EL 0x21 -#define EC_PC_ALIGN 0x22 -#define EC_DABORT_LOWER_EL 0x24 -#define EC_DABORT_CUR_EL 0x25 -#define EC_SP_ALIGN 0x26 -#define EC_AARCH32_FP 0x28 -#define EC_AARCH64_FP 0x2c -#define EC_SERROR 0x2f - -#define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK - -#ifndef __ASSEMBLY__ -/******************************************************************************* - * Function prototypes - ******************************************************************************/ - -extern void early_exceptions(void); -extern void runtime_exceptions(void); -extern void bl1_arch_setup(void); -extern void bl2_arch_setup(void); -extern void bl31_arch_setup(void); -#endif /*__ASSEMBLY__*/ - -#endif /* __ARCH_H__ */ diff --git a/include/aarch64/arch_helpers.h b/include/aarch64/arch_helpers.h deleted file mode 100644 index f55c003..0000000 --- a/include/aarch64/arch_helpers.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __ARCH_HELPERS_H__ -#define __ARCH_HELPERS_H__ - -#include - -#ifndef __ASSEMBLY__ -#include - -/******************************************************************************* - * Aarch64 translation tables manipulation helper prototypes - ******************************************************************************/ -extern unsigned long create_table_desc(unsigned long *next_table_ptr); -extern unsigned long create_block_desc(unsigned long desc, - unsigned long addr, - unsigned int level); -extern unsigned long create_device_block(unsigned long output_addr, - unsigned int level, - unsigned int ns); -extern unsigned long create_romem_block(unsigned long output_addr, - unsigned int level, - unsigned int ns); -extern unsigned long create_rwmem_block(unsigned long output_addr, - unsigned int level, - unsigned int ns); - -/******************************************************************************* - * TLB maintenance accessor prototypes - ******************************************************************************/ -extern void tlbialle1(void); -extern void tlbialle1is(void); -extern void tlbialle2(void); -extern void tlbialle2is(void); -extern void tlbialle3(void); -extern void tlbialle3is(void); -extern void tlbivmalle1(void); - -/******************************************************************************* - * Cache maintenance accessor prototypes - ******************************************************************************/ -extern void dcisw(unsigned long); -extern void dccisw(unsigned long); -extern void dccsw(unsigned long); -extern void dccvac(unsigned long); -extern void dcivac(unsigned long); -extern void dccivac(unsigned long); -extern void dccvau(unsigned long); -extern void dczva(unsigned long); -extern void flush_dcache_range(unsigned long, unsigned long); -extern void inv_dcache_range(unsigned long, unsigned long); -extern void dcsw_op_louis(unsigned int); -extern void dcsw_op_all(unsigned int); - -/******************************************************************************* - * Misc. accessor prototypes - ******************************************************************************/ -extern void enable_irq(void); -extern void enable_fiq(void); -extern void enable_serror(void); -extern void enable_debug_exceptions(void); - -extern void disable_irq(void); -extern void disable_fiq(void); -extern void disable_serror(void); -extern void disable_debug_exceptions(void); - -extern unsigned long read_id_pfr1_el1(void); -extern unsigned long read_id_aa64pfr0_el1(void); -extern unsigned long read_current_el(void); -extern unsigned long read_daif(void); -extern unsigned long read_spsr_el1(void); -extern unsigned long read_spsr_el2(void); -extern unsigned long read_spsr_el3(void); -extern unsigned long read_elr_el1(void); -extern unsigned long read_elr_el2(void); -extern unsigned long read_elr_el3(void); - -extern void write_daif(unsigned long); -extern void write_spsr_el1(unsigned long); -extern void write_spsr_el2(unsigned long); -extern void write_spsr_el3(unsigned long); -extern void write_elr_el1(unsigned long); -extern void write_elr_el2(unsigned long); -extern void write_elr_el3(unsigned long); - -extern void wfi(void); -extern void wfe(void); -extern void rfe(void); -extern void sev(void); -extern void dsb(void); -extern void isb(void); - -extern unsigned int get_afflvl_shift(unsigned int); -extern unsigned int mpidr_mask_lower_afflvls(unsigned long, unsigned int); - -extern void __dead2 eret(unsigned long, unsigned long, - unsigned long, unsigned long, - unsigned long, unsigned long, - unsigned long, unsigned long); - -extern void __dead2 smc(unsigned long, unsigned long, - unsigned long, unsigned long, - unsigned long, unsigned long, - unsigned long, unsigned long); - -/******************************************************************************* - * System register accessor prototypes - ******************************************************************************/ -extern unsigned long read_midr(void); -extern unsigned long read_mpidr(void); - -extern unsigned long read_scr(void); -extern unsigned long read_hcr(void); - -extern unsigned long read_vbar_el1(void); -extern unsigned long read_vbar_el2(void); -extern unsigned long read_vbar_el3(void); - -extern unsigned long read_sctlr_el1(void); -extern unsigned long read_sctlr_el2(void); -extern unsigned long read_sctlr_el3(void); - -extern unsigned long read_actlr_el1(void); -extern unsigned long read_actlr_el2(void); -extern unsigned long read_actlr_el3(void); - -extern unsigned long read_esr_el1(void); -extern unsigned long read_esr_el2(void); -extern unsigned long read_esr_el3(void); - -extern unsigned long read_afsr0_el1(void); -extern unsigned long read_afsr0_el2(void); -extern unsigned long read_afsr0_el3(void); - -extern unsigned long read_afsr1_el1(void); -extern unsigned long read_afsr1_el2(void); -extern unsigned long read_afsr1_el3(void); - -extern unsigned long read_far_el1(void); -extern unsigned long read_far_el2(void); -extern unsigned long read_far_el3(void); - -extern unsigned long read_mair_el1(void); -extern unsigned long read_mair_el2(void); -extern unsigned long read_mair_el3(void); - -extern unsigned long read_amair_el1(void); -extern unsigned long read_amair_el2(void); -extern unsigned long read_amair_el3(void); - -extern unsigned long read_rvbar_el1(void); -extern unsigned long read_rvbar_el2(void); -extern unsigned long read_rvbar_el3(void); - -extern unsigned long read_rmr_el1(void); -extern unsigned long read_rmr_el2(void); -extern unsigned long read_rmr_el3(void); - -extern unsigned long read_tcr_el1(void); -extern unsigned long read_tcr_el2(void); -extern unsigned long read_tcr_el3(void); - -extern unsigned long read_ttbr0_el1(void); -extern unsigned long read_ttbr0_el2(void); -extern unsigned long read_ttbr0_el3(void); - -extern unsigned long read_ttbr1(void); -extern unsigned long read_ttbr1_el1(void); -extern unsigned long read_ttbr1_el2(void); - -extern unsigned long read_cptr_el2(void); -extern unsigned long read_cptr_el3(void); - -extern unsigned long read_cpacr(void); -extern unsigned long read_cpuectlr(void); -extern unsigned int read_cntfrq_el0(void); -extern unsigned long read_cnthctl_el2(void); - -extern void write_scr(unsigned long); -extern void write_hcr(unsigned long); -extern void write_cpacr(unsigned long); -extern void write_cntfrq_el0(unsigned int); -extern void write_cnthctl_el2(unsigned long); - -extern void write_vbar_el1(unsigned long); -extern void write_vbar_el2(unsigned long); -extern void write_vbar_el3(unsigned long); - -extern void write_sctlr_el1(unsigned long); -extern void write_sctlr_el2(unsigned long); -extern void write_sctlr_el3(unsigned long); - -extern void write_actlr_el1(unsigned long); -extern void write_actlr_el2(unsigned long); -extern void write_actlr_el3(unsigned long); - -extern void write_esr_el1(unsigned long); -extern void write_esr_el2(unsigned long); -extern void write_esr_el3(unsigned long); - -extern void write_afsr0(unsigned long); -extern void write_afsr0_el1(unsigned long); -extern void write_afsr0_el2(unsigned long); -extern void write_afsr0_el3(unsigned long); - -extern void write_afsr1(unsigned long); -extern void write_afsr1_el1(unsigned long); -extern void write_afsr1_el2(unsigned long); -extern void write_afsr1_el3(unsigned long); - -extern void write_far_el1(unsigned long); -extern void write_far_el2(unsigned long); -extern void write_far_el3(unsigned long); - -extern void write_mair_el1(unsigned long); -extern void write_mair_el2(unsigned long); -extern void write_mair_el3(unsigned long); - -extern void write_amair_el1(unsigned long); -extern void write_amair_el2(unsigned long); -extern void write_amair_el3(unsigned long); - -extern void write_rmr_el1(unsigned long); -extern void write_rmr_el2(unsigned long); -extern void write_rmr_el3(unsigned long); - -extern void write_tcr_el1(unsigned long); -extern void write_tcr_el2(unsigned long); -extern void write_tcr_el3(unsigned long); - -extern void write_ttbr0_el1(unsigned long); -extern void write_ttbr0_el2(unsigned long); -extern void write_ttbr0_el3(unsigned long); - -extern void write_ttbr1_el1(unsigned long); -extern void write_ttbr1_el2(unsigned long); - -extern void write_cpuectlr(unsigned long); -extern void write_cptr_el2(unsigned long); -extern void write_cptr_el3(unsigned long); - -#endif /*__ASSEMBLY__*/ - -#endif /* __ARCH_HELPERS_H__ */ diff --git a/include/aarch64/xlat_tables.h b/include/aarch64/xlat_tables.h deleted file mode 100644 index 01b1afe..0000000 --- a/include/aarch64/xlat_tables.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __XLAT_TABLES_H__ -#define __XLAT_TABLES_H__ - -#include - -/* - * Flags for building up memory mapping attributes. - * These are organised so that a clear bit gives a more restrictive mapping - * that a set bit, that way a bitwise-and two sets of attributes will never give - * an attribute which has greater access rights that any of the original - * attributes. - */ -typedef enum { - MT_DEVICE = 0 << 0, - MT_MEMORY = 1 << 0, - - MT_RO = 0 << 1, - MT_RW = 1 << 1, - - MT_SECURE = 0 << 2, - MT_NS = 1 << 2 -} mmap_attr; - -/* - * Structure for specifying a single region of memory. - */ -typedef struct { - unsigned long base; - unsigned long size; - mmap_attr attr; -} mmap_region; - -extern void mmap_add_region(unsigned long base, unsigned long size, - unsigned attr); -extern void mmap_add(const mmap_region *mm); - -extern void init_xlat_tables(void); - -extern uint64_t l1_xlation_table[]; - -#endif /* __XLAT_TABLES_H__ */ diff --git a/include/asm_macros.S b/include/asm_macros.S deleted file mode 100644 index 8bcb7d2..0000000 --- a/include/asm_macros.S +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - - .macro func_prologue - stp x29, x30, [sp, #-0x10]! - mov x29,sp - .endm - - .macro func_epilogue - ldp x29, x30, [sp], #0x10 - .endm - - - .macro dcache_line_size reg, tmp - mrs \tmp, ctr_el0 - ubfx \tmp, \tmp, #16, #4 - mov \reg, #4 - lsl \reg, \reg, \tmp - .endm - - - .macro icache_line_size reg, tmp - mrs \tmp, ctr_el0 - and \tmp, \tmp, #0xf - mov \reg, #4 - lsl \reg, \reg, \tmp - .endm - - - .macro smc_check label - bl read_esr - ubfx x0, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH - cmp x0, #EC_AARCH64_SMC - b.ne $label - .endm - - - .macro setup_dcsw_op_args start_level, end_level, clidr, shift, fw, ls - mrs \clidr, clidr_el1 - mov \start_level, xzr - ubfx \end_level, \clidr, \shift, \fw - lsl \end_level, \end_level, \ls - .endm - - /* - * This macro verifies that the a given vector doesn't exceed the - * architectural limit of 32 instructions. This is meant to be placed - * immedately after the last instruction in the vector. It takes the - * vector entry as the parameter - */ - .macro check_vector_size since - .if (. - \since) > (32 * 4) - .error "Vector exceeds 32 instructions" - .endif - .endm - - /* - * This macro is used to create a function label and place the - * code into a separate text section based on the function name - * to enable elimination of unused code during linking - */ - .macro func _name - .section .text.\_name, "ax" - .type \_name, %function - \_name: - .endm - - /* - * This macro declares an array of 1 or more stacks, properly - * aligned and in the requested section - */ -#define STACK_ALIGN 6 - - .macro declare_stack _name, _section, _size, _count - .if ((\_size & ((1 << STACK_ALIGN) - 1)) <> 0) - .error "Stack size not correctly aligned" - .endif - .section \_section, "aw", %nobits - .align STACK_ALIGN - \_name: - .space ((\_count) * (\_size)), 0 - .endm - - /* - * This macro calculates the base address of an MP stack using the - * platform_get_core_pos() index, the name of the stack storage and - * the size of each stack - * In: X0 = MPIDR of CPU whose stack is wanted - * Out: X0 = physical address of stack base - * Clobber: X30, X1, X2 - */ - .macro get_mp_stack _name, _size - bl platform_get_core_pos - ldr x2, =(\_name + \_size) - mov x1, #\_size - madd x0, x0, x1, x2 - .endm - - /* - * This macro calculates the base address of a UP stack using the - * name of the stack storage and the size of the stack - * Out: X0 = physical address of stack base - */ - .macro get_up_stack _name, _size - ldr x0, =(\_name + \_size) - .endm diff --git a/include/bakery_lock.h b/include/bakery_lock.h deleted file mode 100644 index da5d9dd..0000000 --- a/include/bakery_lock.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __BAKERY_LOCK_H__ -#define __BAKERY_LOCK_H__ - -#include - -#define BAKERY_LOCK_MAX_CPUS PLATFORM_CORE_COUNT - -#ifndef __ASSEMBLY__ -typedef struct { - int owner; - volatile char entering[BAKERY_LOCK_MAX_CPUS]; - volatile unsigned number[BAKERY_LOCK_MAX_CPUS]; -} bakery_lock; - -#define NO_OWNER (-1) - -void bakery_lock_init(bakery_lock* bakery); -void bakery_lock_get(unsigned long mpidr, bakery_lock* bakery); -void bakery_lock_release(unsigned long mpidr, bakery_lock* bakery); -int bakery_lock_try(unsigned long mpidr, bakery_lock* bakery); -#endif /*__ASSEMBLY__*/ - -#endif /* __BAKERY_LOCK_H__ */ diff --git a/include/bl1.h b/include/bl1.h deleted file mode 100644 index e1d50c0..0000000 --- a/include/bl1.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __BL1_H__ -#define __BL1_H__ - -#include - -#ifndef __ASSEMBLY__ - -/****************************************** - * Function prototypes - *****************************************/ -extern void bl1_platform_setup(void); -extern meminfo *bl1_plat_sec_mem_layout(void); - -#endif /*__ASSEMBLY__*/ - -#endif /* __BL1_H__ */ diff --git a/include/bl1/bl1.h b/include/bl1/bl1.h new file mode 100644 index 0000000..e1d50c0 --- /dev/null +++ b/include/bl1/bl1.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BL1_H__ +#define __BL1_H__ + +#include + +#ifndef __ASSEMBLY__ + +/****************************************** + * Function prototypes + *****************************************/ +extern void bl1_platform_setup(void); +extern meminfo *bl1_plat_sec_mem_layout(void); + +#endif /*__ASSEMBLY__*/ + +#endif /* __BL1_H__ */ diff --git a/include/bl2.h b/include/bl2.h deleted file mode 100644 index d0ff69b..0000000 --- a/include/bl2.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __BL2_H__ -#define __BL2_H__ - -#include - -/****************************************** - * Data declarations - *****************************************/ -extern unsigned long long bl2_entrypoint; - -/****************************************** - * Function prototypes - *****************************************/ -extern void bl2_platform_setup(void); -extern meminfo *bl2_plat_sec_mem_layout(void); -extern bl31_args *bl2_get_bl31_args_ptr(void); - -#endif /* __BL2_H__ */ diff --git a/include/bl2/bl2.h b/include/bl2/bl2.h new file mode 100644 index 0000000..d0ff69b --- /dev/null +++ b/include/bl2/bl2.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BL2_H__ +#define __BL2_H__ + +#include + +/****************************************** + * Data declarations + *****************************************/ +extern unsigned long long bl2_entrypoint; + +/****************************************** + * Function prototypes + *****************************************/ +extern void bl2_platform_setup(void); +extern meminfo *bl2_plat_sec_mem_layout(void); +extern bl31_args *bl2_get_bl31_args_ptr(void); + +#endif /* __BL2_H__ */ diff --git a/include/bl31.h b/include/bl31.h deleted file mode 100644 index b8c603a..0000000 --- a/include/bl31.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __BL31_H__ -#define __BL31_H__ - -#include - -/******************************************************************************* - * Data declarations - ******************************************************************************/ -extern unsigned long bl31_entrypoint; - -/******************************************************************************* - * Function prototypes - ******************************************************************************/ -extern void bl31_next_el_arch_setup(uint32_t security_state); -extern void bl31_set_next_image_type(uint32_t type); -extern uint32_t bl31_get_next_image_type(void); -extern void bl31_prepare_next_image_entry(); -extern el_change_info *bl31_get_next_image_info(uint32_t type); -extern void bl31_platform_setup(void); -extern meminfo *bl31_plat_get_bl32_mem_layout(void); -extern meminfo *bl31_plat_sec_mem_layout(void); -extern void bl31_register_bl32_init(int32_t (*)(meminfo *)); -#endif /* __BL31_H__ */ diff --git a/include/bl31/bl31.h b/include/bl31/bl31.h new file mode 100644 index 0000000..b8c603a --- /dev/null +++ b/include/bl31/bl31.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BL31_H__ +#define __BL31_H__ + +#include + +/******************************************************************************* + * Data declarations + ******************************************************************************/ +extern unsigned long bl31_entrypoint; + +/******************************************************************************* + * Function prototypes + ******************************************************************************/ +extern void bl31_next_el_arch_setup(uint32_t security_state); +extern void bl31_set_next_image_type(uint32_t type); +extern uint32_t bl31_get_next_image_type(void); +extern void bl31_prepare_next_image_entry(); +extern el_change_info *bl31_get_next_image_info(uint32_t type); +extern void bl31_platform_setup(void); +extern meminfo *bl31_plat_get_bl32_mem_layout(void); +extern meminfo *bl31_plat_sec_mem_layout(void); +extern void bl31_register_bl32_init(int32_t (*)(meminfo *)); +#endif /* __BL31_H__ */ diff --git a/include/bl31/cm_macros.S b/include/bl31/cm_macros.S new file mode 100644 index 0000000..9eeec18 --- /dev/null +++ b/include/bl31/cm_macros.S @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + /* --------------------------------------------- + * Zero out the callee saved register to prevent + * leakage of secure state into the normal world + * during the first ERET after a cold/warm boot. + * --------------------------------------------- + */ + .macro zero_callee_saved_regs + mov x19, xzr + mov x20, xzr + mov x21, xzr + mov x22, xzr + mov x23, xzr + mov x24, xzr + mov x25, xzr + mov x26, xzr + mov x27, xzr + mov x28, xzr + mov x29, xzr + .endm + + .macro switch_to_exception_stack reg1 reg2 + mov \reg1 , sp + ldr \reg2, [\reg1, #CTX_EL3STATE_OFFSET + CTX_EXCEPTION_SP] + mov sp, \reg2 + .endm + + /* ----------------------------------------------------- + * Handle SMC exceptions seperately from other sync. + * exceptions. + * ----------------------------------------------------- + */ + .macro handle_sync_exception + stp x30, xzr, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + mrs x30, esr_el3 + ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH + + cmp x30, #EC_AARCH32_SMC + b.eq smc_handler32 + + cmp x30, #EC_AARCH64_SMC + b.eq smc_handler64 + + /* ----------------------------------------------------- + * The following code handles any synchronous exception + * that is not an SMC. SP_EL3 is pointing to a context + * structure where all the scratch registers are saved. + * An exception stack is also retrieved from the context + * Currently, a register dump is printed since BL31 does + * not expect any such exceptions. + * ----------------------------------------------------- + */ + bl save_scratch_registers + switch_to_exception_stack x0 x1 + + /* Save the core_context pointer for handled faults */ + stp x0, xzr, [sp, #-0x10]! + bl fault_handler + ldp x0, xzr, [sp], #0x10 + + mov sp, x0 + bl restore_scratch_registers + ldp x30, xzr, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + eret + .endm + + /* ----------------------------------------------------- + * Use a platform defined mechanism to report an async. + * exception. + * ----------------------------------------------------- + */ + .macro handle_async_exception type + stp x30, xzr, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + bl save_scratch_registers + switch_to_exception_stack x0 x1 + + /* Save the core_context pointer */ + stp x0, xzr, [sp, #-0x10]! + mov x0, \type + bl plat_report_exception + ldp x0, xzr, [sp], #0x10 + + mov sp, x0 + bl restore_scratch_registers + ldp x30, xzr, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + .endm + diff --git a/include/bl31/context.h b/include/bl31/context.h new file mode 100644 index 0000000..cb4cd8e --- /dev/null +++ b/include/bl31/context.h @@ -0,0 +1,315 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CONTEXT_H__ +#define __CONTEXT_H__ + +#include +#include + +/******************************************************************************* + * Constants that allow assembler code to access members of and the 'gp_regs' + * structure at their correct offsets. + ******************************************************************************/ +#define CTX_GPREGS_OFFSET 0x0 +#define CTX_GPREG_X0 0x0 +#define CTX_GPREG_X1 0x8 +#define CTX_GPREG_X2 0x10 +#define CTX_GPREG_X3 0x18 +#define CTX_GPREG_X4 0x20 +#define CTX_GPREG_X5 0x28 +#define CTX_GPREG_X6 0x30 +#define CTX_GPREG_X7 0x38 +#define CTX_GPREG_X8 0x40 +#define CTX_GPREG_X9 0x48 +#define CTX_GPREG_X10 0x50 +#define CTX_GPREG_X11 0x58 +#define CTX_GPREG_X12 0x60 +#define CTX_GPREG_X13 0x68 +#define CTX_GPREG_X14 0x70 +#define CTX_GPREG_X15 0x78 +#define CTX_GPREG_X16 0x80 +#define CTX_GPREG_X17 0x88 +#define CTX_GPREG_X18 0x90 +#define CTX_GPREG_SP_EL0 0x98 +#define CTX_GPREG_LR 0xa0 +/* Unused space to allow registers to be stored as pairs */ +#define CTX_GPREGS_END 0xb0 + +/******************************************************************************* + * Constants that allow assembler code to access members of and the 'el3_state' + * structure at their correct offsets. Note that some of the registers are only + * 32-bits wide but are stored as 64-bit values for convenience + ******************************************************************************/ +#define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) +#define CTX_EXCEPTION_SP 0x0 +#define CTX_RUNTIME_SP 0x8 +#define CTX_SPSR_EL3 0x10 +#define CTX_ELR_EL3 0x18 +#define CTX_SCR_EL3 0x20 +#define CTX_SCTLR_EL3 0x28 +#define CTX_CPTR_EL3 0x30 +/* Unused space to allow registers to be stored as pairs */ +#define CTX_CNTFRQ_EL0 0x40 +#define CTX_MAIR_EL3 0x48 +#define CTX_TCR_EL3 0x50 +#define CTX_TTBR0_EL3 0x58 +#define CTX_DAIF_EL3 0x60 +#define CTX_VBAR_EL3 0x68 /* Currently unused */ +#define CTX_EL3STATE_END 0x70 + +/******************************************************************************* + * Constants that allow assembler code to access members of and the + * 'el1_sys_regs' structure at their correct offsets. Note that some of the + * registers are only 32-bits wide but are stored as 64-bit values for + * convenience + ******************************************************************************/ +#define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) +#define CTX_SPSR_EL1 0x0 +#define CTX_ELR_EL1 0x8 +#define CTX_SPSR_ABT 0x10 +#define CTX_SPSR_UND 0x18 +#define CTX_SPSR_IRQ 0x20 +#define CTX_SPSR_FIQ 0x28 +#define CTX_SCTLR_EL1 0x30 +#define CTX_ACTLR_EL1 0x38 +#define CTX_CPACR_EL1 0x40 +#define CTX_CSSELR_EL1 0x48 +#define CTX_SP_EL1 0x50 +#define CTX_ESR_EL1 0x58 +#define CTX_TTBR0_EL1 0x60 +#define CTX_TTBR1_EL1 0x68 +#define CTX_MAIR_EL1 0x70 +#define CTX_AMAIR_EL1 0x78 +#define CTX_TCR_EL1 0x80 +#define CTX_TPIDR_EL1 0x88 +#define CTX_TPIDR_EL0 0x90 +#define CTX_TPIDRRO_EL0 0x98 +#define CTX_DACR32_EL2 0xa0 +#define CTX_IFSR32_EL2 0xa8 +#define CTX_PAR_EL1 0xb0 +#define CTX_FAR_EL1 0xb8 +#define CTX_AFSR0_EL1 0xc0 +#define CTX_AFSR1_EL1 0xc8 +#define CTX_CONTEXTIDR_EL1 0xd0 +#define CTX_VBAR_EL1 0xd8 +#define CTX_CNTP_CTL_EL0 0xe0 +#define CTX_CNTP_CVAL_EL0 0xe8 +#define CTX_CNTV_CTL_EL0 0xf0 +#define CTX_CNTV_CVAL_EL0 0xf8 +#define CTX_CNTKCTL_EL1 0x100 +#define CTX_FP_FPEXC32_EL2 0x108 +#define CTX_SYSREGS_END 0x110 + +/******************************************************************************* + * Constants that allow assembler code to access members of and the 'fp_regs' + * structure at their correct offsets. + ******************************************************************************/ +#define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END) +#define CTX_FP_Q0 0x0 +#define CTX_FP_Q1 0x10 +#define CTX_FP_Q2 0x20 +#define CTX_FP_Q3 0x30 +#define CTX_FP_Q4 0x40 +#define CTX_FP_Q5 0x50 +#define CTX_FP_Q6 0x60 +#define CTX_FP_Q7 0x70 +#define CTX_FP_Q8 0x80 +#define CTX_FP_Q9 0x90 +#define CTX_FP_Q10 0xa0 +#define CTX_FP_Q11 0xb0 +#define CTX_FP_Q12 0xc0 +#define CTX_FP_Q13 0xd0 +#define CTX_FP_Q14 0xe0 +#define CTX_FP_Q15 0xf0 +#define CTX_FP_Q16 0x100 +#define CTX_FP_Q17 0x110 +#define CTX_FP_Q18 0x120 +#define CTX_FP_Q19 0x130 +#define CTX_FP_Q20 0x140 +#define CTX_FP_Q21 0x150 +#define CTX_FP_Q22 0x160 +#define CTX_FP_Q23 0x170 +#define CTX_FP_Q24 0x180 +#define CTX_FP_Q25 0x190 +#define CTX_FP_Q26 0x1a0 +#define CTX_FP_Q27 0x1b0 +#define CTX_FP_Q28 0x1c0 +#define CTX_FP_Q29 0x1d0 +#define CTX_FP_Q30 0x1e0 +#define CTX_FP_Q31 0x1f0 +#define CTX_FP_FPSR 0x200 +#define CTX_FP_FPCR 0x208 +#define CTX_FPREGS_END 0x210 + +#ifndef __ASSEMBLY__ + +/* + * Common constants to help define the 'cpu_context' structure and its + * members below. + */ +#define DWORD_SHIFT 3 +#define DEFINE_REG_STRUCT(name, num_regs) \ + typedef struct { \ + uint64_t _regs[num_regs]; \ + } __aligned(16) name + +/* Constants to determine the size of individual context structures */ +#define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) +#define CTX_SYSREG_ALL (CTX_SYSREGS_END >> DWORD_SHIFT) +#define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) +#define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) + +/* + * AArch64 general purpose register context structure. Only x0-x18, lr + * are saved as the compiler is expected to preserve the remaining + * callee saved registers if used by the C runtime and the assembler + * does not touch the remaining. + */ +DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); + +/* + * AArch64 EL1 system register context structure for preserving the + * architectural state during switches from one security state to + * another in EL1. + */ +DEFINE_REG_STRUCT(el1_sys_regs, CTX_SYSREG_ALL); + +/* + * AArch64 floating point register context structure for preserving + * the floating point state during switches from one security state to + * another. + */ +DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL); + +/* + * Miscellaneous registers used by EL3 firmware to maintain its state + * across exception entries and exits + */ +DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); + +/* + * Macros to access members of any of the above structures using their + * offsets + */ +#define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> DWORD_SHIFT]) +#define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[offset >> DWORD_SHIFT]) \ + = val) + +/* + * Top-level context structure which is used by EL3 firmware to + * preserve the state of a core at EL1 in one of the two security + * states and save enough EL3 meta data to be able to return to that + * EL and security state. The context management library will be used + * to ensure that SP_EL3 always points to an instance of this + * structure at exception entry and exit. Each instance will + * correspond to either the secure or the non-secure state. + */ +typedef struct { + gp_regs gpregs_ctx; + el3_state el3state_ctx; + el1_sys_regs sysregs_ctx; + fp_regs fpregs_ctx; +} cpu_context; + +/* Macros to access members of the 'cpu_context' structure */ +#define get_el3state_ctx(h) (&((cpu_context *) h)->el3state_ctx) +#define get_fpregs_ctx(h) (&((cpu_context *) h)->fpregs_ctx) +#define get_sysregs_ctx(h) (&((cpu_context *) h)->sysregs_ctx) +#define get_gpregs_ctx(h) (&((cpu_context *) h)->gpregs_ctx) + +/* + * Compile time assertions related to the 'cpu_context' structure to + * ensure that the assembler and the compiler view of the offsets of + * the structure members is the same. + */ +CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context, gpregs_ctx), \ + assert_core_context_gp_offset_mismatch); +CASSERT(CTX_SYSREGS_OFFSET == __builtin_offsetof(cpu_context, sysregs_ctx), \ + assert_core_context_sys_offset_mismatch); +CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context, fpregs_ctx), \ + assert_core_context_fp_offset_mismatch); +CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context, el3state_ctx), \ + assert_core_context_el3state_offset_mismatch); + +/* + * Helper macro to set the general purpose registers that correspond to + * parameters in an aapcs_64 call i.e. x0-x7 + */ +#define set_aapcs_args0(ctx, x0) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \ + } while (0); +#define set_aapcs_args1(ctx, x0, x1) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \ + set_aapcs_args0(ctx, x0); \ + } while (0); +#define set_aapcs_args2(ctx, x0, x1, x2) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \ + set_aapcs_args1(ctx, x0, x1); \ + } while (0); +#define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \ + set_aapcs_args2(ctx, x0, x1, x2); \ + } while (0); +#define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \ + set_aapcs_args3(ctx, x0, x1, x2, x3); \ + } while (0); +#define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \ + set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \ + } while (0); +#define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \ + set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \ + } while (0); +#define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \ + set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \ + } while (0); + +/******************************************************************************* + * Function prototypes + ******************************************************************************/ +void el3_sysregs_context_save(el3_state *regs); +void el3_sysregs_context_restore(el3_state *regs); +void el1_sysregs_context_save(el1_sys_regs *regs); +void el1_sysregs_context_restore(el1_sys_regs *regs); +void fpregs_context_save(fp_regs *regs); +void fpregs_context_restore(fp_regs *regs); + +#undef CTX_SYSREG_ALL +#undef CTX_FP_ALL +#undef CTX_GPREG_ALL +#undef CTX_EL3STATE_ALL + +#endif /* __ASSEMBLY__ */ + +#endif /* __CONTEXT_H__ */ diff --git a/include/bl31/context_mgmt.h b/include/bl31/context_mgmt.h new file mode 100644 index 0000000..35f7c8c --- /dev/null +++ b/include/bl31/context_mgmt.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CM_H__ +#define __CM_H__ + +#include + +#ifndef __ASSEMBLY__ +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +extern void cm_init(void); +extern void *cm_get_context(uint64_t mpidr, uint32_t security_state); +extern void cm_set_context(uint64_t mpidr, + void *context, + uint32_t security_state); +extern void cm_el3_sysregs_context_save(uint32_t security_state); +extern void cm_el3_sysregs_context_restore(uint32_t security_state); +extern void cm_el1_sysregs_context_save(uint32_t security_state); +extern void cm_el1_sysregs_context_restore(uint32_t security_state); +extern void cm_set_el3_eret_context(uint32_t security_state, uint64_t entrypoint, + uint32_t spsr, uint32_t scr); +extern void cm_set_el3_elr(uint32_t security_state, uint64_t entrypoint); +extern void cm_set_next_eret_context(uint32_t security_state); +extern void cm_init_exception_stack(uint64_t mpidr, uint32_t security_state); +#endif /*__ASSEMBLY__*/ +#endif /* __CM_H__ */ diff --git a/include/bl31/runtime_svc.h b/include/bl31/runtime_svc.h new file mode 100644 index 0000000..148c0bc --- /dev/null +++ b/include/bl31/runtime_svc.h @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __RUNTIME_SVC_H__ +#define __RUNTIME_SVC_H__ +#include +#include + +/******************************************************************************* + * Bit definitions inside the function id as per the SMC calling convention + ******************************************************************************/ +#define FUNCID_TYPE_SHIFT 31 +#define FUNCID_CC_SHIFT 30 +#define FUNCID_OEN_SHIFT 24 +#define FUNCID_NUM_SHIFT 0 + +#define FUNCID_TYPE_MASK 0x1 +#define FUNCID_CC_MASK 0x1 +#define FUNCID_OEN_MASK 0x3f +#define FUNCID_NUM_MASK 0xffff + +#define FUNCID_TYPE_WIDTH 1 +#define FUNCID_CC_WIDTH 1 +#define FUNCID_OEN_WIDTH 6 +#define FUNCID_NUM_WIDTH 16 + +#define GET_SMC_CC(id) ((id >> FUNCID_CC_SHIFT) & \ + FUNCID_CC_MASK) + +#define SMC_64 1 +#define SMC_32 0 +#define SMC_UNK 0xffffffff +#define SMC_TYPE_FAST 1 +#define SMC_TYPE_STD 0 + +/******************************************************************************* + * Owning entity number definitions inside the function id as per the SMC + * calling convention + ******************************************************************************/ +#define OEN_ARM_START 0 +#define OEN_ARM_END 0 +#define OEN_CPU_START 1 +#define OEN_CPU_END 1 +#define OEN_SIP_START 2 +#define OEN_SIP_END 2 +#define OEN_OEM_START 3 +#define OEN_OEM_END 3 +#define OEN_STD_START 4 /* Standard Calls */ +#define OEN_STD_END 4 +#define OEN_TAP_START 48 /* Trusted Applications */ +#define OEN_TAP_END 49 +#define OEN_TOS_START 50 /* Trusted OS */ +#define OEN_TOS_END 63 +#define OEN_LIMIT 64 + +/******************************************************************************* + * Constants to indicate type of exception to the common exception handler. + ******************************************************************************/ +#define SYNC_EXCEPTION_SP_EL0 0x0 +#define IRQ_SP_EL0 0x1 +#define FIQ_SP_EL0 0x2 +#define SERROR_SP_EL0 0x3 +#define SYNC_EXCEPTION_SP_ELX 0x4 +#define IRQ_SP_ELX 0x5 +#define FIQ_SP_ELX 0x6 +#define SERROR_SP_ELX 0x7 +#define SYNC_EXCEPTION_AARCH64 0x8 +#define IRQ_AARCH64 0x9 +#define FIQ_AARCH64 0xa +#define SERROR_AARCH64 0xb +#define SYNC_EXCEPTION_AARCH32 0xc +#define IRQ_AARCH32 0xd +#define FIQ_AARCH32 0xe +#define SERROR_AARCH32 0xf + +/******************************************************************************* + * Structure definition, typedefs & constants for the runtime service framework + ******************************************************************************/ + +/* + * Constants to allow the assembler access a runtime service + * descriptor + */ +#define RT_SVC_SIZE_LOG2 5 +#define SIZEOF_RT_SVC_DESC (1 << RT_SVC_SIZE_LOG2) +#define RT_SVC_DESC_INIT 16 +#define RT_SVC_DESC_HANDLE 24 + +/* + * The function identifier has 6 bits for the owning entity number and + * single bit for the type of smc call. When taken together these + * values limit the maximum number of runtime services to 128. + */ +#define MAX_RT_SVCS 128 + +#ifndef __ASSEMBLY__ + +/* Various flags passed to SMC handlers */ +#define SMC_FROM_SECURE (0 << 0) +#define SMC_FROM_NON_SECURE (1 << 0) + +#define is_caller_non_secure(_f) (!!(_f & SMC_FROM_NON_SECURE)) +#define is_caller_secure(_f) (!(is_caller_non_secure(_f))) + +/* Prototype for runtime service initializing function */ +typedef int32_t (*rt_svc_init)(void); + +/* Convenience macros to return from SMC handler */ +#define SMC_RET1(_h, _x0) { \ + write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X0, (_x0)); \ + return _x0; \ +} +#define SMC_RET2(_h, _x0, _x1) { \ + write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X1, (_x1)); \ + SMC_RET1(_h, (_x0)); \ +} +#define SMC_RET3(_h, _x0, _x1, _x2) { \ + write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X2, (_x2)); \ + SMC_RET2(_h, (_x0), (_x1)); \ +} +#define SMC_RET4(_h, _x0, _x1, _x2, _x3) { \ + write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X3, (_x3)); \ + SMC_RET3(_h, (_x0), (_x1), (_x2)); \ +} + + +/* + * Convenience macros to access general purpose registers using handle provided + * to SMC handler. These takes the offset values defined in context.h + */ +#define SMC_GET_GP(_h, _g) \ + read_ctx_reg(get_gpregs_ctx(_h), (_g)); +#define SMC_SET_GP(_h, _g, _v) \ + write_ctx_reg(get_gpregs_ctx(_h), (_g), (_v)); + +/* + * Convenience macros to access EL3 context registers using handle provided to + * SMC handler. These takes the offset values defined in context.h + */ +#define SMC_GET_EL3(_h, _e) \ + read_ctx_reg(get_el3state_ctx(_h), (_e)); +#define SMC_SET_EL3(_h, _e, _v) \ + write_ctx_reg(get_el3state_ctx(_h), (_e), (_v)); + +/* + * Prototype for runtime service SMC handler function. x0 (SMC Function ID) to + * x4 are as passed by the caller. Rest of the arguments to SMC and the context + * can be accessed using the handle pointer. The cookie parameter is reserved + * for future use + */ +typedef uint64_t (*rt_svc_handle)(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags); +typedef struct { + uint8_t start_oen; + uint8_t end_oen; + uint8_t call_type; + const char *name; + rt_svc_init init; + rt_svc_handle handle; +} rt_svc_desc; + +/* + * Convenience macro to declare a service descriptor + */ +#define DECLARE_RT_SVC(_name, _start, _end, _type, _setup, _smch) \ + static const rt_svc_desc __svc_desc_ ## _name \ + __attribute__ ((section("rt_svc_descs"), used)) = { \ + _start, \ + _end, \ + _type, \ + #_name, \ + _setup, \ + _smch } + +/* + * Compile time assertions related to the 'rt_svc_desc' structure to: + * 1. ensure that the assembler and the compiler view of the size + * of the structure are the same. + * 2. ensure that the assembler and the compiler see the initialisation + * routine at the same offset. + * 3. ensure that the assembler and the compiler see the handler + * routine at the same offset. + */ +CASSERT((sizeof(rt_svc_desc) == SIZEOF_RT_SVC_DESC), \ + assert_sizeof_rt_svc_desc_mismatch); +CASSERT(RT_SVC_DESC_INIT == __builtin_offsetof(rt_svc_desc, init), \ + assert_rt_svc_desc_init_offset_mismatch); +CASSERT(RT_SVC_DESC_HANDLE == __builtin_offsetof(rt_svc_desc, handle), \ + assert_rt_svc_desc_handle_offset_mismatch); + + +/* + * This macro combines the call type and the owning entity number corresponding + * to a runtime service to generate a unique owning entity number. This unique + * oen is used to access an entry in the 'rt_svc_descs_indices' array. The entry + * contains the index of the service descriptor in the 'rt_svc_descs' array. + */ +#define get_unique_oen(oen, call_type) ((oen & FUNCID_OEN_MASK) | \ + ((call_type & FUNCID_TYPE_MASK) \ + << FUNCID_OEN_WIDTH)) + + +/* + * Macro to define UUID for services. Apart from defining and initializing a + * uuid_t structure, this macro verifies that the first word of the defined UUID + * does not equal SMC_UNK. This is to ensure that the caller won't mistake the + * returned UUID in x0 for an invalid SMC error return + */ +#define DEFINE_SVC_UUID(_name, _tl, _tm, _th, _cl, _ch, \ + _n0, _n1, _n2, _n3, _n4, _n5) \ + CASSERT(_tl != SMC_UNK, invalid_svc_uuid);\ + static const uuid_t _name = { \ + _tl, _tm, _th, _cl, _ch, \ + { _n0, _n1, _n2, _n3, _n4, _n5 } \ + } + +/* Return a UUID in the SMC return registers */ +#define SMC_UUID_RET(_h, _uuid) \ + SMC_RET4(handle, ((const uint32_t *) &(_uuid))[0], \ + ((const uint32_t *) &(_uuid))[1], \ + ((const uint32_t *) &(_uuid))[2], \ + ((const uint32_t *) &(_uuid))[3]) + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +extern void runtime_svc_init(); +extern uint64_t __RT_SVC_DESCS_START__; +extern uint64_t __RT_SVC_DESCS_END__; +extern uint64_t get_exception_stack(uint64_t mpidr); +extern void fault_handler(void *handle); +#endif /*__ASSEMBLY__*/ +#endif /* __RUNTIME_SVC_H__ */ diff --git a/include/bl31/services/psci.h b/include/bl31/services/psci.h new file mode 100644 index 0000000..e290793 --- /dev/null +++ b/include/bl31/services/psci.h @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PSCI_H__ +#define __PSCI_H__ + +/******************************************************************************* + * Defines for runtime services func ids + ******************************************************************************/ +#define PSCI_VERSION 0x84000000 +#define PSCI_CPU_SUSPEND_AARCH32 0x84000001 +#define PSCI_CPU_SUSPEND_AARCH64 0xc4000001 +#define PSCI_CPU_OFF 0x84000002 +#define PSCI_CPU_ON_AARCH32 0x84000003 +#define PSCI_CPU_ON_AARCH64 0xc4000003 +#define PSCI_AFFINITY_INFO_AARCH32 0x84000004 +#define PSCI_AFFINITY_INFO_AARCH64 0xc4000004 +#define PSCI_MIG_AARCH32 0x84000005 +#define PSCI_MIG_AARCH64 0xc4000005 +#define PSCI_MIG_INFO_TYPE 0x84000006 +#define PSCI_MIG_INFO_UP_CPU_AARCH32 0x84000007 +#define PSCI_MIG_INFO_UP_CPU_AARCH64 0xc4000007 +#define PSCI_SYSTEM_OFF 0x84000008 +#define PSCI_SYSTEM_RESET 0x84000009 + +/* + * Number of PSCI calls (above) implemented. System off and reset aren't + * implemented as yet + */ +#define PSCI_NUM_CALLS 13 + +/******************************************************************************* + * PSCI Migrate and friends + ******************************************************************************/ +#define PSCI_TOS_UP_MIG_CAP 0 +#define PSCI_TOS_NOT_UP_MIG_CAP 1 +#define PSCI_TOS_NOT_PRESENT_MP 2 + +/******************************************************************************* + * PSCI CPU_SUSPEND 'power_state' parameter specific defines + ******************************************************************************/ +#define PSTATE_ID_SHIFT 0 +#define PSTATE_TYPE_SHIFT 16 +#define PSTATE_AFF_LVL_SHIFT 24 + +#define PSTATE_ID_MASK 0xffff +#define PSTATE_TYPE_MASK 0x1 +#define PSTATE_AFF_LVL_MASK 0x3 +#define PSTATE_VALID_MASK 0xFCFE0000 + +#define PSTATE_TYPE_STANDBY 0x0 +#define PSTATE_TYPE_POWERDOWN 0x1 + +#define psci_get_pstate_id(pstate) (pstate >> PSTATE_ID_SHIFT) & \ + PSTATE_ID_MASK +#define psci_get_pstate_type(pstate) (pstate >> PSTATE_TYPE_SHIFT) & \ + PSTATE_TYPE_MASK +#define psci_get_pstate_afflvl(pstate) (pstate >> PSTATE_AFF_LVL_SHIFT) & \ + PSTATE_AFF_LVL_MASK + +/******************************************************************************* + * PSCI version + ******************************************************************************/ +#define PSCI_MAJOR_VER (0 << 16) +#define PSCI_MINOR_VER 0x2 + +/******************************************************************************* + * PSCI error codes + ******************************************************************************/ +#define PSCI_E_SUCCESS 0 +#define PSCI_E_NOT_SUPPORTED -1 +#define PSCI_E_INVALID_PARAMS -2 +#define PSCI_E_DENIED -3 +#define PSCI_E_ALREADY_ON -4 +#define PSCI_E_ON_PENDING -5 +#define PSCI_E_INTERN_FAIL -6 +#define PSCI_E_NOT_PRESENT -7 +#define PSCI_E_DISABLED -8 + +/******************************************************************************* + * PSCI affinity state related constants. An affinity instance could be present + * or absent physically to cater for asymmetric topologies. If present then it + * could in one of the 4 further defined states. + ******************************************************************************/ +#define PSCI_STATE_SHIFT 1 +#define PSCI_STATE_MASK 0xff + +#define PSCI_AFF_ABSENT 0x0 +#define PSCI_AFF_PRESENT 0x1 +#define PSCI_STATE_ON 0x0 +#define PSCI_STATE_OFF 0x1 +#define PSCI_STATE_ON_PENDING 0x2 +#define PSCI_STATE_SUSPEND 0x3 + +#define PSCI_INVALID_DATA -1 + +#define get_phys_state(x) (x != PSCI_STATE_ON ? \ + PSCI_STATE_OFF : PSCI_STATE_ON) + +#define psci_validate_power_state(pstate) (pstate & PSTATE_VALID_MASK) + + +/* Number of affinity instances whose state this psci imp. can track */ +#define PSCI_NUM_AFFS 32ull + +#ifndef __ASSEMBLY__ +/******************************************************************************* + * Structure populated by platform specific code to export routines which + * perform common low level pm functions + ******************************************************************************/ +typedef struct { + int (*affinst_standby)(unsigned int); + int (*affinst_on)(unsigned long, + unsigned long, + unsigned long, + unsigned int, + unsigned int); + int (*affinst_off)(unsigned long, unsigned int, unsigned int); + int (*affinst_suspend)(unsigned long, + unsigned long, + unsigned long, + unsigned int, + unsigned int); + int (*affinst_on_finish)(unsigned long, unsigned int, unsigned int); + int (*affinst_suspend_finish)(unsigned long, + unsigned int, + unsigned int); +} plat_pm_ops; + +/******************************************************************************* + * Optional structure populated by the Secure Payload Dispatcher to be given a + * chance to perform any bookkeeping before PSCI executes a power mgmt. + * operation. It also allows PSCI to determine certain properties of the SP e.g. + * migrate capability etc. + ******************************************************************************/ +typedef struct { + void (*svc_on)(uint64_t target_cpu); + int32_t (*svc_off)(uint64_t __unused); + void (*svc_suspend)(uint64_t power_state); + void (*svc_on_finish)(uint64_t __unused); + void (*svc_suspend_finish)(uint64_t suspend_level); + void (*svc_migrate)(uint64_t __unused1, uint64_t __unused2); + int32_t (*svc_migrate_info)(uint64_t *__unused); +} spd_pm_ops; + +/******************************************************************************* + * Function & Data prototypes + ******************************************************************************/ +extern unsigned int psci_version(void); +extern int __psci_cpu_suspend(unsigned int, unsigned long, unsigned long); +extern int __psci_cpu_off(void); +extern int psci_affinity_info(unsigned long, unsigned int); +extern int psci_migrate(unsigned int); +extern unsigned int psci_migrate_info_type(void); +extern unsigned long psci_migrate_info_up_cpu(void); +extern void psci_system_off(void); +extern void psci_system_reset(void); +extern int psci_cpu_on(unsigned long, + unsigned long, + unsigned long); +extern void psci_aff_on_finish_entry(void); +extern void psci_aff_suspend_finish_entry(void); +extern void psci_register_spd_pm_hook(const spd_pm_ops *); +extern int psci_get_suspend_stateid(unsigned long mpidr); +extern int psci_get_suspend_afflvl(unsigned long mpidr); + +#endif /*__ASSEMBLY__*/ + + +#endif /* __PSCI_H__ */ diff --git a/include/bl31/services/std_svc.h b/include/bl31/services/std_svc.h new file mode 100644 index 0000000..cbd5b62 --- /dev/null +++ b/include/bl31/services/std_svc.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __STD_SVC_H__ +#define __STD_SVC_H__ + +/* SMC function IDs for Standard Service queries */ + +#define ARM_STD_SVC_CALL_COUNT 0x8400ff00 +#define ARM_STD_SVC_UID 0x8400ff01 +/* 0x8400ff02 is reserved */ +#define ARM_STD_SVC_VERSION 0x8400ff03 + +/* ARM Standard Service Calls version numbers */ +#define STD_SVC_VERSION_MAJOR 0x0 +#define STD_SVC_VERSION_MINOR 0x1 + +/* The macros below are used to identify PSCI calls from the SMC function ID */ +#define PSCI_FID_MASK 0xffe0u +#define PSCI_FID_VALUE 0u +#define is_psci_fid(_fid) \ + (((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE) + +#endif /* __STD_SVC_H__ */ diff --git a/include/bl32.h b/include/bl32.h deleted file mode 100644 index 88e18bd..0000000 --- a/include/bl32.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __BL32_H__ -#define __BL32_H__ - -#ifndef __ASSEMBLY__ -#include - -#include - -extern void bl32_platform_setup(void); -extern meminfo *bl32_plat_sec_mem_layout(void); -extern uint64_t bl32_main(void); - -#endif /* __ASSEMBLY__ */ - -#endif /* __BL32_H__ */ diff --git a/include/bl32/bl32.h b/include/bl32/bl32.h new file mode 100644 index 0000000..88e18bd --- /dev/null +++ b/include/bl32/bl32.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BL32_H__ +#define __BL32_H__ + +#ifndef __ASSEMBLY__ +#include + +#include + +extern void bl32_platform_setup(void); +extern meminfo *bl32_plat_sec_mem_layout(void); +extern uint64_t bl32_main(void); + +#endif /* __ASSEMBLY__ */ + +#endif /* __BL32_H__ */ diff --git a/include/bl32/payloads/tsp.h b/include/bl32/payloads/tsp.h new file mode 100644 index 0000000..9d747d7 --- /dev/null +++ b/include/bl32/payloads/tsp.h @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TSP_H__ +#define __TSP_H__ + +#include +#include + +/* + * SMC function IDs that TSP uses to signal various forms of completions + * to the secure payload dispatcher. + */ +#define TSP_ENTRY_DONE 0xf2000000 +#define TSP_ON_DONE 0xf2000001 +#define TSP_OFF_DONE 0xf2000002 +#define TSP_SUSPEND_DONE 0xf2000003 +#define TSP_RESUME_DONE 0xf2000004 +#define TSP_WORK_DONE 0xf2000005 + +/* SMC function ID that TSP uses to request service from secure montior */ +#define TSP_GET_ARGS 0xf2001000 + +/* Function IDs for various TSP services */ +#define TSP_FID_ADD 0xf2002000 +#define TSP_FID_SUB 0xf2002001 +#define TSP_FID_MUL 0xf2002002 +#define TSP_FID_DIV 0xf2002003 + +/* + * Total number of function IDs implemented for services offered to NS clients. + * The function IDs are defined above + */ +#define TSP_NUM_FID 0x4 + +/* TSP implementation version numbers */ +#define TSP_VERSION_MAJOR 0x0 /* Major version */ +#define TSP_VERSION_MINOR 0x1 /* Minor version */ + +/* + * Standard Trusted OS Function IDs that fall under Trusted OS call range + * according to SMC calling convention + */ +#define TOS_CALL_COUNT 0xbf00ff00 /* Number of calls implemented */ +#define TOS_UID 0xbf00ff01 /* Implementation UID */ +/* 0xbf00ff02 is reserved */ +#define TOS_CALL_VERSION 0xbf00ff03 /* Trusted OS Call Version */ + +/* Definitions to help the assembler access the SMC/ERET args structure */ +#define TSP_ARGS_SIZE 0x40 +#define TSP_ARG0 0x0 +#define TSP_ARG1 0x8 +#define TSP_ARG2 0x10 +#define TSP_ARG3 0x18 +#define TSP_ARG4 0x20 +#define TSP_ARG5 0x28 +#define TSP_ARG6 0x30 +#define TSP_ARG7 0x38 +#define TSP_ARGS_END 0x40 + +#ifndef __ASSEMBLY__ +#include + +typedef void (*tsp_generic_fptr)(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); + +typedef struct { + tsp_generic_fptr fast_smc_entry; + tsp_generic_fptr cpu_on_entry; + tsp_generic_fptr cpu_off_entry; + tsp_generic_fptr cpu_resume_entry; + tsp_generic_fptr cpu_suspend_entry; +} entry_info; + +typedef struct { + uint32_t smc_count; /* Number of returns on this cpu */ + uint32_t eret_count; /* Number of entries on this cpu */ + uint32_t cpu_on_count; /* Number of cpu on requests */ + uint32_t cpu_off_count; /* Number of cpu off requests */ + uint32_t cpu_suspend_count; /* Number of cpu suspend requests */ + uint32_t cpu_resume_count; /* Number of cpu resume requests */ +} __aligned(CACHE_WRITEBACK_GRANULE) work_statistics; + +typedef struct { + uint64_t _regs[TSP_ARGS_END >> 3]; +} __aligned(CACHE_WRITEBACK_GRANULE) tsp_args; + +/* Macros to access members of the above structure using their offsets */ +#define read_sp_arg(args, offset) ((args)->_regs[offset >> 3]) +#define write_sp_arg(args, offset, val)(((args)->_regs[offset >> 3]) \ + = val) + +/* + * Ensure that the assembler's view of the size of the tsp_args is the + * same as the compilers + */ +CASSERT(TSP_ARGS_SIZE == sizeof(tsp_args), assert_sp_args_size_mismatch); + +extern void tsp_get_magic(uint64_t args[4]); + +extern void tsp_fast_smc_entry(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); +extern void tsp_cpu_resume_entry(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); +extern tsp_args *tsp_cpu_resume_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); +extern void tsp_cpu_suspend_entry(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); +extern tsp_args *tsp_cpu_suspend_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); +extern void tsp_cpu_on_entry(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); +extern tsp_args *tsp_cpu_on_main(void); +extern void tsp_cpu_off_entry(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); +extern tsp_args *tsp_cpu_off_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); +#endif /* __ASSEMBLY__ */ + +#endif /* __BL2_H__ */ diff --git a/include/bl_common.h b/include/bl_common.h deleted file mode 100644 index ba6dc11..0000000 --- a/include/bl_common.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __BL_COMMON_H__ -#define __BL_COMMON_H__ - -#define SECURE 0 -#define NON_SECURE 1 - -#define UP 1 -#define DOWN 0 - -/******************************************************************************* - * Constants for loading images. When BLx wants to load BLy, it looks at a - * meminfo structure to find the extents of free memory. Then depending upon - * how it has been configured, it can either load BLy at the top or bottom of - * the free memory. These constants indicate the choice. - * TODO: Make this configurable while building the trusted firmware. - ******************************************************************************/ -#define TOP_LOAD 0x1 -#define BOT_LOAD !TOP_LOAD -#define LOAD_MASK (1 << 0) - -/******************************************************************************* - * Macro to flag a compile time assertion. It uses the preprocessor to generate - * an invalid C construct if 'cond' evaluates to false. - * The following compilation error is triggered if the assertion fails: - * "error: size of array 'msg' is negative" - ******************************************************************************/ -#define CASSERT(cond, msg) typedef char msg[(cond) ? 1 : -1] - -/****************************************************************************** - * Opcode passed in x0 to tell next EL that we want to run an image. - * Corresponds to the function ID of the only SMC that the BL1 exception - * handlers service. That's why the chosen value is the first function ID of - * the ARM SMC64 range. - *****************************************************************************/ -#define RUN_IMAGE 0xC0000000 - - -#ifndef __ASSEMBLY__ -#include - -/******************************************************************************* - * Structure used for telling the next BL how much of a particular type of - * memory is available for its use and how much is already used. - ******************************************************************************/ -typedef struct { - unsigned long total_base; - long total_size; - unsigned long free_base; - long free_size; - unsigned long attr; - unsigned long next; -} meminfo; - -typedef struct { - unsigned long arg0; - unsigned long arg1; - unsigned long arg2; - unsigned long arg3; - unsigned long arg4; - unsigned long arg5; - unsigned long arg6; - unsigned long arg7; -} aapcs64_params; - -/******************************************************************************* - * This structure represents the superset of information needed while switching - * exception levels. The only two mechanisms to do so are ERET & SMC. In case of - * SMC all members apart from 'aapcs64_params' will be ignored. - ******************************************************************************/ -typedef struct { - unsigned long entrypoint; - unsigned long spsr; - unsigned long security_state; - aapcs64_params args; -} el_change_info; - -/******************************************************************************* - * This structure represents the superset of information that can be passed to - * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be - * populated only if BL2 detects its presence. - ******************************************************************************/ -typedef struct { - meminfo bl31_meminfo; - el_change_info bl32_image_info; - meminfo bl32_meminfo; - el_change_info bl33_image_info; - meminfo bl33_meminfo; -} bl31_args; - -/******************************************************************************* - * Function & variable prototypes - ******************************************************************************/ -extern unsigned long page_align(unsigned long, unsigned); -extern void change_security_state(unsigned int); -extern void __dead2 drop_el(aapcs64_params *, unsigned long, unsigned long); -extern void __dead2 raise_el(aapcs64_params *); -extern void __dead2 change_el(el_change_info *); -extern unsigned long make_spsr(unsigned long, unsigned long, unsigned long); -extern void init_bl2_mem_layout(meminfo *, - meminfo *, - unsigned int, - unsigned long) __attribute__((weak)); -extern void init_bl31_mem_layout(const meminfo *, - meminfo *, - unsigned int) __attribute__((weak)); -extern unsigned long image_size(const char *); -extern unsigned long load_image(meminfo *, const char *, unsigned int, unsigned long); -extern void __dead2 run_image(unsigned long entrypoint, - unsigned long spsr, - unsigned long security_state, - void *first_arg, - void *second_arg); -extern unsigned long *get_el_change_mem_ptr(void); -extern const char build_message[]; - -#endif /*__ASSEMBLY__*/ - -#endif /* __BL_COMMON_H__ */ diff --git a/include/cm_macros.S b/include/cm_macros.S deleted file mode 100644 index 9eeec18..0000000 --- a/include/cm_macros.S +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - /* --------------------------------------------- - * Zero out the callee saved register to prevent - * leakage of secure state into the normal world - * during the first ERET after a cold/warm boot. - * --------------------------------------------- - */ - .macro zero_callee_saved_regs - mov x19, xzr - mov x20, xzr - mov x21, xzr - mov x22, xzr - mov x23, xzr - mov x24, xzr - mov x25, xzr - mov x26, xzr - mov x27, xzr - mov x28, xzr - mov x29, xzr - .endm - - .macro switch_to_exception_stack reg1 reg2 - mov \reg1 , sp - ldr \reg2, [\reg1, #CTX_EL3STATE_OFFSET + CTX_EXCEPTION_SP] - mov sp, \reg2 - .endm - - /* ----------------------------------------------------- - * Handle SMC exceptions seperately from other sync. - * exceptions. - * ----------------------------------------------------- - */ - .macro handle_sync_exception - stp x30, xzr, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] - mrs x30, esr_el3 - ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH - - cmp x30, #EC_AARCH32_SMC - b.eq smc_handler32 - - cmp x30, #EC_AARCH64_SMC - b.eq smc_handler64 - - /* ----------------------------------------------------- - * The following code handles any synchronous exception - * that is not an SMC. SP_EL3 is pointing to a context - * structure where all the scratch registers are saved. - * An exception stack is also retrieved from the context - * Currently, a register dump is printed since BL31 does - * not expect any such exceptions. - * ----------------------------------------------------- - */ - bl save_scratch_registers - switch_to_exception_stack x0 x1 - - /* Save the core_context pointer for handled faults */ - stp x0, xzr, [sp, #-0x10]! - bl fault_handler - ldp x0, xzr, [sp], #0x10 - - mov sp, x0 - bl restore_scratch_registers - ldp x30, xzr, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] - eret - .endm - - /* ----------------------------------------------------- - * Use a platform defined mechanism to report an async. - * exception. - * ----------------------------------------------------- - */ - .macro handle_async_exception type - stp x30, xzr, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] - bl save_scratch_registers - switch_to_exception_stack x0 x1 - - /* Save the core_context pointer */ - stp x0, xzr, [sp, #-0x10]! - mov x0, \type - bl plat_report_exception - ldp x0, xzr, [sp], #0x10 - - mov sp, x0 - bl restore_scratch_registers - ldp x30, xzr, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] - .endm - diff --git a/include/common/asm_macros.S b/include/common/asm_macros.S new file mode 100644 index 0000000..8bcb7d2 --- /dev/null +++ b/include/common/asm_macros.S @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + .macro func_prologue + stp x29, x30, [sp, #-0x10]! + mov x29,sp + .endm + + .macro func_epilogue + ldp x29, x30, [sp], #0x10 + .endm + + + .macro dcache_line_size reg, tmp + mrs \tmp, ctr_el0 + ubfx \tmp, \tmp, #16, #4 + mov \reg, #4 + lsl \reg, \reg, \tmp + .endm + + + .macro icache_line_size reg, tmp + mrs \tmp, ctr_el0 + and \tmp, \tmp, #0xf + mov \reg, #4 + lsl \reg, \reg, \tmp + .endm + + + .macro smc_check label + bl read_esr + ubfx x0, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH + cmp x0, #EC_AARCH64_SMC + b.ne $label + .endm + + + .macro setup_dcsw_op_args start_level, end_level, clidr, shift, fw, ls + mrs \clidr, clidr_el1 + mov \start_level, xzr + ubfx \end_level, \clidr, \shift, \fw + lsl \end_level, \end_level, \ls + .endm + + /* + * This macro verifies that the a given vector doesn't exceed the + * architectural limit of 32 instructions. This is meant to be placed + * immedately after the last instruction in the vector. It takes the + * vector entry as the parameter + */ + .macro check_vector_size since + .if (. - \since) > (32 * 4) + .error "Vector exceeds 32 instructions" + .endif + .endm + + /* + * This macro is used to create a function label and place the + * code into a separate text section based on the function name + * to enable elimination of unused code during linking + */ + .macro func _name + .section .text.\_name, "ax" + .type \_name, %function + \_name: + .endm + + /* + * This macro declares an array of 1 or more stacks, properly + * aligned and in the requested section + */ +#define STACK_ALIGN 6 + + .macro declare_stack _name, _section, _size, _count + .if ((\_size & ((1 << STACK_ALIGN) - 1)) <> 0) + .error "Stack size not correctly aligned" + .endif + .section \_section, "aw", %nobits + .align STACK_ALIGN + \_name: + .space ((\_count) * (\_size)), 0 + .endm + + /* + * This macro calculates the base address of an MP stack using the + * platform_get_core_pos() index, the name of the stack storage and + * the size of each stack + * In: X0 = MPIDR of CPU whose stack is wanted + * Out: X0 = physical address of stack base + * Clobber: X30, X1, X2 + */ + .macro get_mp_stack _name, _size + bl platform_get_core_pos + ldr x2, =(\_name + \_size) + mov x1, #\_size + madd x0, x0, x1, x2 + .endm + + /* + * This macro calculates the base address of a UP stack using the + * name of the stack storage and the size of the stack + * Out: X0 = physical address of stack base + */ + .macro get_up_stack _name, _size + ldr x0, =(\_name + \_size) + .endm diff --git a/include/common/bl_common.h b/include/common/bl_common.h new file mode 100644 index 0000000..a751d78 --- /dev/null +++ b/include/common/bl_common.h @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BL_COMMON_H__ +#define __BL_COMMON_H__ + +#define SECURE 0 +#define NON_SECURE 1 + +#define UP 1 +#define DOWN 0 + +/******************************************************************************* + * Constants for loading images. When BLx wants to load BLy, it looks at a + * meminfo structure to find the extents of free memory. Then depending upon + * how it has been configured, it can either load BLy at the top or bottom of + * the free memory. These constants indicate the choice. + * TODO: Make this configurable while building the trusted firmware. + ******************************************************************************/ +#define TOP_LOAD 0x1 +#define BOT_LOAD !TOP_LOAD +#define LOAD_MASK (1 << 0) + +/******************************************************************************* + * Macro to flag a compile time assertion. It uses the preprocessor to generate + * an invalid C construct if 'cond' evaluates to false. + * The following compilation error is triggered if the assertion fails: + * "error: size of array 'msg' is negative" + ******************************************************************************/ +#define CASSERT(cond, msg) typedef char msg[(cond) ? 1 : -1] + +/****************************************************************************** + * Opcode passed in x0 to tell next EL that we want to run an image. + * Corresponds to the function ID of the only SMC that the BL1 exception + * handlers service. That's why the chosen value is the first function ID of + * the ARM SMC64 range. + *****************************************************************************/ +#define RUN_IMAGE 0xC0000000 + + +#ifndef __ASSEMBLY__ +#include + +/******************************************************************************* + * Structure used for telling the next BL how much of a particular type of + * memory is available for its use and how much is already used. + ******************************************************************************/ +typedef struct { + unsigned long total_base; + long total_size; + unsigned long free_base; + long free_size; + unsigned long attr; + unsigned long next; +} meminfo; + +typedef struct { + unsigned long arg0; + unsigned long arg1; + unsigned long arg2; + unsigned long arg3; + unsigned long arg4; + unsigned long arg5; + unsigned long arg6; + unsigned long arg7; +} aapcs64_params; + +/******************************************************************************* + * This structure represents the superset of information needed while switching + * exception levels. The only two mechanisms to do so are ERET & SMC. In case of + * SMC all members apart from 'aapcs64_params' will be ignored. + ******************************************************************************/ +typedef struct { + unsigned long entrypoint; + unsigned long spsr; + unsigned long security_state; + aapcs64_params args; +} el_change_info; + +/******************************************************************************* + * This structure represents the superset of information that can be passed to + * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be + * populated only if BL2 detects its presence. + ******************************************************************************/ +typedef struct { + meminfo bl31_meminfo; + el_change_info bl32_image_info; + meminfo bl32_meminfo; + el_change_info bl33_image_info; + meminfo bl33_meminfo; +} bl31_args; + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +extern unsigned long page_align(unsigned long, unsigned); +extern void change_security_state(unsigned int); +extern void __dead2 drop_el(aapcs64_params *, unsigned long, unsigned long); +extern void __dead2 raise_el(aapcs64_params *); +extern void __dead2 change_el(el_change_info *); +extern unsigned long make_spsr(unsigned long, unsigned long, unsigned long); +extern void init_bl2_mem_layout(meminfo *, + meminfo *, + unsigned int, + unsigned long) __attribute__((weak)); +extern void init_bl31_mem_layout(const meminfo *, + meminfo *, + unsigned int) __attribute__((weak)); +extern unsigned long image_size(const char *); +extern unsigned long load_image(meminfo *, + const char *, + unsigned int, + unsigned long); +extern void __dead2 run_image(unsigned long entrypoint, + unsigned long spsr, + unsigned long security_state, + void *first_arg, + void *second_arg); +extern unsigned long *get_el_change_mem_ptr(void); +extern const char build_message[]; + +#endif /*__ASSEMBLY__*/ + +#endif /* __BL_COMMON_H__ */ diff --git a/include/common/debug.h b/include/common/debug.h new file mode 100644 index 0000000..f829477 --- /dev/null +++ b/include/common/debug.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +/* Do not try to call this from ASM code. */ +#ifndef __ASSEMBLY__ + +#include + +/* If building the project with DEBUG disabled the INFO and WARN macros + * won't produce any output. The ERROR macro is always enabled. + * The format expected is the same as for printf(). + * INFO("Info %s.\n", "message") -> INFO: Info message. + * WARN("Warning %s.\n", "message") -> WARN: Warning message. + * ERROR("Error %s.\n", "message") -> ERROR: Error message. + * + * TODO : add debug levels. + */ +#if DEBUG + #define INFO(...) printf("INFO: " __VA_ARGS__) + #define WARN(...) printf("WARN: " __VA_ARGS__) +#else + #define INFO(...) + #define WARN(...) +#endif + +#define ERROR(...) printf("ERROR: " __VA_ARGS__) + + +/* For the moment this Panic function is very basic, Report an error and + * spin. This can be expanded in the future to provide more information. + */ +static inline void __attribute__((noreturn)) panic(void) +{ + ERROR("PANIC\n"); + while (1) + ; +} + +#endif /* __ASSEMBLY__ */ +#endif /* __DEBUG_H__ */ diff --git a/include/common/firmware_image_package.h b/include/common/firmware_image_package.h new file mode 100644 index 0000000..ff5e971 --- /dev/null +++ b/include/common/firmware_image_package.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FIRMWARE_IMAGE_PACKAGE_H__ +#define __FIRMWARE_IMAGE_PACKAGE_H__ + +#include +#include + +/* This is used as a signature to validate the blob header */ +#define TOC_HEADER_NAME 0xAA640001 + + +/* ToC Entry UUIDs */ +#define UUID_TRUSTED_BOOT_FIRMWARE_BL2 \ + {0x0becf95f, 0x224d, 0x4d3e, 0xa5, 0x44, {0xc3, 0x9d, 0x81, 0xc7, 0x3f, 0x0a} } +#define UUID_SCP_FIRMWARE_BL30 \ + {0x3dfd6697, 0xbe89, 0x49e8, 0xae, 0x5d, {0x78, 0xa1, 0x40, 0x60, 0x82, 0x13} } +#define UUID_EL3_RUNTIME_FIRMWARE_BL31 \ + {0x6d08d447, 0xfe4c, 0x4698, 0x9b, 0x95, {0x29, 0x50, 0xcb, 0xbd, 0x5a, 0x00} } +#define UUID_SECURE_PAYLOAD_BL32 \ + {0x89e1d005, 0xdc53, 0x4713, 0x8d, 0x2b, {0x50, 0x0a, 0x4b, 0x7a, 0x3e, 0x38} } +#define UUID_NON_TRUSTED_FIRMWARE_BL33 \ + {0xa7eed0d6, 0xeafc, 0x4bd5, 0x97, 0x82, {0x99, 0x34, 0xf2, 0x34, 0xb6, 0xe4} } + +typedef struct { + uint32_t name; + uint32_t serial_number; + uint64_t flags; +} fip_toc_header; + +typedef struct { + uuid_t uuid; + uint64_t offset_address; + uint64_t size; + uint64_t flags; +} fip_toc_entry; + +#endif /* __FIRMWARE_IMAGE_PACKAGE_H__ */ diff --git a/include/context.h b/include/context.h deleted file mode 100644 index cb4cd8e..0000000 --- a/include/context.h +++ /dev/null @@ -1,315 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __CONTEXT_H__ -#define __CONTEXT_H__ - -#include -#include - -/******************************************************************************* - * Constants that allow assembler code to access members of and the 'gp_regs' - * structure at their correct offsets. - ******************************************************************************/ -#define CTX_GPREGS_OFFSET 0x0 -#define CTX_GPREG_X0 0x0 -#define CTX_GPREG_X1 0x8 -#define CTX_GPREG_X2 0x10 -#define CTX_GPREG_X3 0x18 -#define CTX_GPREG_X4 0x20 -#define CTX_GPREG_X5 0x28 -#define CTX_GPREG_X6 0x30 -#define CTX_GPREG_X7 0x38 -#define CTX_GPREG_X8 0x40 -#define CTX_GPREG_X9 0x48 -#define CTX_GPREG_X10 0x50 -#define CTX_GPREG_X11 0x58 -#define CTX_GPREG_X12 0x60 -#define CTX_GPREG_X13 0x68 -#define CTX_GPREG_X14 0x70 -#define CTX_GPREG_X15 0x78 -#define CTX_GPREG_X16 0x80 -#define CTX_GPREG_X17 0x88 -#define CTX_GPREG_X18 0x90 -#define CTX_GPREG_SP_EL0 0x98 -#define CTX_GPREG_LR 0xa0 -/* Unused space to allow registers to be stored as pairs */ -#define CTX_GPREGS_END 0xb0 - -/******************************************************************************* - * Constants that allow assembler code to access members of and the 'el3_state' - * structure at their correct offsets. Note that some of the registers are only - * 32-bits wide but are stored as 64-bit values for convenience - ******************************************************************************/ -#define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) -#define CTX_EXCEPTION_SP 0x0 -#define CTX_RUNTIME_SP 0x8 -#define CTX_SPSR_EL3 0x10 -#define CTX_ELR_EL3 0x18 -#define CTX_SCR_EL3 0x20 -#define CTX_SCTLR_EL3 0x28 -#define CTX_CPTR_EL3 0x30 -/* Unused space to allow registers to be stored as pairs */ -#define CTX_CNTFRQ_EL0 0x40 -#define CTX_MAIR_EL3 0x48 -#define CTX_TCR_EL3 0x50 -#define CTX_TTBR0_EL3 0x58 -#define CTX_DAIF_EL3 0x60 -#define CTX_VBAR_EL3 0x68 /* Currently unused */ -#define CTX_EL3STATE_END 0x70 - -/******************************************************************************* - * Constants that allow assembler code to access members of and the - * 'el1_sys_regs' structure at their correct offsets. Note that some of the - * registers are only 32-bits wide but are stored as 64-bit values for - * convenience - ******************************************************************************/ -#define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) -#define CTX_SPSR_EL1 0x0 -#define CTX_ELR_EL1 0x8 -#define CTX_SPSR_ABT 0x10 -#define CTX_SPSR_UND 0x18 -#define CTX_SPSR_IRQ 0x20 -#define CTX_SPSR_FIQ 0x28 -#define CTX_SCTLR_EL1 0x30 -#define CTX_ACTLR_EL1 0x38 -#define CTX_CPACR_EL1 0x40 -#define CTX_CSSELR_EL1 0x48 -#define CTX_SP_EL1 0x50 -#define CTX_ESR_EL1 0x58 -#define CTX_TTBR0_EL1 0x60 -#define CTX_TTBR1_EL1 0x68 -#define CTX_MAIR_EL1 0x70 -#define CTX_AMAIR_EL1 0x78 -#define CTX_TCR_EL1 0x80 -#define CTX_TPIDR_EL1 0x88 -#define CTX_TPIDR_EL0 0x90 -#define CTX_TPIDRRO_EL0 0x98 -#define CTX_DACR32_EL2 0xa0 -#define CTX_IFSR32_EL2 0xa8 -#define CTX_PAR_EL1 0xb0 -#define CTX_FAR_EL1 0xb8 -#define CTX_AFSR0_EL1 0xc0 -#define CTX_AFSR1_EL1 0xc8 -#define CTX_CONTEXTIDR_EL1 0xd0 -#define CTX_VBAR_EL1 0xd8 -#define CTX_CNTP_CTL_EL0 0xe0 -#define CTX_CNTP_CVAL_EL0 0xe8 -#define CTX_CNTV_CTL_EL0 0xf0 -#define CTX_CNTV_CVAL_EL0 0xf8 -#define CTX_CNTKCTL_EL1 0x100 -#define CTX_FP_FPEXC32_EL2 0x108 -#define CTX_SYSREGS_END 0x110 - -/******************************************************************************* - * Constants that allow assembler code to access members of and the 'fp_regs' - * structure at their correct offsets. - ******************************************************************************/ -#define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END) -#define CTX_FP_Q0 0x0 -#define CTX_FP_Q1 0x10 -#define CTX_FP_Q2 0x20 -#define CTX_FP_Q3 0x30 -#define CTX_FP_Q4 0x40 -#define CTX_FP_Q5 0x50 -#define CTX_FP_Q6 0x60 -#define CTX_FP_Q7 0x70 -#define CTX_FP_Q8 0x80 -#define CTX_FP_Q9 0x90 -#define CTX_FP_Q10 0xa0 -#define CTX_FP_Q11 0xb0 -#define CTX_FP_Q12 0xc0 -#define CTX_FP_Q13 0xd0 -#define CTX_FP_Q14 0xe0 -#define CTX_FP_Q15 0xf0 -#define CTX_FP_Q16 0x100 -#define CTX_FP_Q17 0x110 -#define CTX_FP_Q18 0x120 -#define CTX_FP_Q19 0x130 -#define CTX_FP_Q20 0x140 -#define CTX_FP_Q21 0x150 -#define CTX_FP_Q22 0x160 -#define CTX_FP_Q23 0x170 -#define CTX_FP_Q24 0x180 -#define CTX_FP_Q25 0x190 -#define CTX_FP_Q26 0x1a0 -#define CTX_FP_Q27 0x1b0 -#define CTX_FP_Q28 0x1c0 -#define CTX_FP_Q29 0x1d0 -#define CTX_FP_Q30 0x1e0 -#define CTX_FP_Q31 0x1f0 -#define CTX_FP_FPSR 0x200 -#define CTX_FP_FPCR 0x208 -#define CTX_FPREGS_END 0x210 - -#ifndef __ASSEMBLY__ - -/* - * Common constants to help define the 'cpu_context' structure and its - * members below. - */ -#define DWORD_SHIFT 3 -#define DEFINE_REG_STRUCT(name, num_regs) \ - typedef struct { \ - uint64_t _regs[num_regs]; \ - } __aligned(16) name - -/* Constants to determine the size of individual context structures */ -#define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) -#define CTX_SYSREG_ALL (CTX_SYSREGS_END >> DWORD_SHIFT) -#define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) -#define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) - -/* - * AArch64 general purpose register context structure. Only x0-x18, lr - * are saved as the compiler is expected to preserve the remaining - * callee saved registers if used by the C runtime and the assembler - * does not touch the remaining. - */ -DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); - -/* - * AArch64 EL1 system register context structure for preserving the - * architectural state during switches from one security state to - * another in EL1. - */ -DEFINE_REG_STRUCT(el1_sys_regs, CTX_SYSREG_ALL); - -/* - * AArch64 floating point register context structure for preserving - * the floating point state during switches from one security state to - * another. - */ -DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL); - -/* - * Miscellaneous registers used by EL3 firmware to maintain its state - * across exception entries and exits - */ -DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); - -/* - * Macros to access members of any of the above structures using their - * offsets - */ -#define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> DWORD_SHIFT]) -#define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[offset >> DWORD_SHIFT]) \ - = val) - -/* - * Top-level context structure which is used by EL3 firmware to - * preserve the state of a core at EL1 in one of the two security - * states and save enough EL3 meta data to be able to return to that - * EL and security state. The context management library will be used - * to ensure that SP_EL3 always points to an instance of this - * structure at exception entry and exit. Each instance will - * correspond to either the secure or the non-secure state. - */ -typedef struct { - gp_regs gpregs_ctx; - el3_state el3state_ctx; - el1_sys_regs sysregs_ctx; - fp_regs fpregs_ctx; -} cpu_context; - -/* Macros to access members of the 'cpu_context' structure */ -#define get_el3state_ctx(h) (&((cpu_context *) h)->el3state_ctx) -#define get_fpregs_ctx(h) (&((cpu_context *) h)->fpregs_ctx) -#define get_sysregs_ctx(h) (&((cpu_context *) h)->sysregs_ctx) -#define get_gpregs_ctx(h) (&((cpu_context *) h)->gpregs_ctx) - -/* - * Compile time assertions related to the 'cpu_context' structure to - * ensure that the assembler and the compiler view of the offsets of - * the structure members is the same. - */ -CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context, gpregs_ctx), \ - assert_core_context_gp_offset_mismatch); -CASSERT(CTX_SYSREGS_OFFSET == __builtin_offsetof(cpu_context, sysregs_ctx), \ - assert_core_context_sys_offset_mismatch); -CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context, fpregs_ctx), \ - assert_core_context_fp_offset_mismatch); -CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context, el3state_ctx), \ - assert_core_context_el3state_offset_mismatch); - -/* - * Helper macro to set the general purpose registers that correspond to - * parameters in an aapcs_64 call i.e. x0-x7 - */ -#define set_aapcs_args0(ctx, x0) do { \ - write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \ - } while (0); -#define set_aapcs_args1(ctx, x0, x1) do { \ - write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \ - set_aapcs_args0(ctx, x0); \ - } while (0); -#define set_aapcs_args2(ctx, x0, x1, x2) do { \ - write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \ - set_aapcs_args1(ctx, x0, x1); \ - } while (0); -#define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ - write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \ - set_aapcs_args2(ctx, x0, x1, x2); \ - } while (0); -#define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ - write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \ - set_aapcs_args3(ctx, x0, x1, x2, x3); \ - } while (0); -#define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ - write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \ - set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \ - } while (0); -#define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ - write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \ - set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \ - } while (0); -#define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ - write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \ - set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \ - } while (0); - -/******************************************************************************* - * Function prototypes - ******************************************************************************/ -void el3_sysregs_context_save(el3_state *regs); -void el3_sysregs_context_restore(el3_state *regs); -void el1_sysregs_context_save(el1_sys_regs *regs); -void el1_sysregs_context_restore(el1_sys_regs *regs); -void fpregs_context_save(fp_regs *regs); -void fpregs_context_restore(fp_regs *regs); - -#undef CTX_SYSREG_ALL -#undef CTX_FP_ALL -#undef CTX_GPREG_ALL -#undef CTX_EL3STATE_ALL - -#endif /* __ASSEMBLY__ */ - -#endif /* __CONTEXT_H__ */ diff --git a/include/context_mgmt.h b/include/context_mgmt.h deleted file mode 100644 index 35f7c8c..0000000 --- a/include/context_mgmt.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __CM_H__ -#define __CM_H__ - -#include - -#ifndef __ASSEMBLY__ -/******************************************************************************* - * Function & variable prototypes - ******************************************************************************/ -extern void cm_init(void); -extern void *cm_get_context(uint64_t mpidr, uint32_t security_state); -extern void cm_set_context(uint64_t mpidr, - void *context, - uint32_t security_state); -extern void cm_el3_sysregs_context_save(uint32_t security_state); -extern void cm_el3_sysregs_context_restore(uint32_t security_state); -extern void cm_el1_sysregs_context_save(uint32_t security_state); -extern void cm_el1_sysregs_context_restore(uint32_t security_state); -extern void cm_set_el3_eret_context(uint32_t security_state, uint64_t entrypoint, - uint32_t spsr, uint32_t scr); -extern void cm_set_el3_elr(uint32_t security_state, uint64_t entrypoint); -extern void cm_set_next_eret_context(uint32_t security_state); -extern void cm_init_exception_stack(uint64_t mpidr, uint32_t security_state); -#endif /*__ASSEMBLY__*/ -#endif /* __CM_H__ */ diff --git a/include/debug.h b/include/debug.h deleted file mode 100644 index f829477..0000000 --- a/include/debug.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __DEBUG_H__ -#define __DEBUG_H__ - -/* Do not try to call this from ASM code. */ -#ifndef __ASSEMBLY__ - -#include - -/* If building the project with DEBUG disabled the INFO and WARN macros - * won't produce any output. The ERROR macro is always enabled. - * The format expected is the same as for printf(). - * INFO("Info %s.\n", "message") -> INFO: Info message. - * WARN("Warning %s.\n", "message") -> WARN: Warning message. - * ERROR("Error %s.\n", "message") -> ERROR: Error message. - * - * TODO : add debug levels. - */ -#if DEBUG - #define INFO(...) printf("INFO: " __VA_ARGS__) - #define WARN(...) printf("WARN: " __VA_ARGS__) -#else - #define INFO(...) - #define WARN(...) -#endif - -#define ERROR(...) printf("ERROR: " __VA_ARGS__) - - -/* For the moment this Panic function is very basic, Report an error and - * spin. This can be expanded in the future to provide more information. - */ -static inline void __attribute__((noreturn)) panic(void) -{ - ERROR("PANIC\n"); - while (1) - ; -} - -#endif /* __ASSEMBLY__ */ -#endif /* __DEBUG_H__ */ diff --git a/include/drivers/arm/cci400.h b/include/drivers/arm/cci400.h new file mode 100644 index 0000000..3921675 --- /dev/null +++ b/include/drivers/arm/cci400.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CCI_400_H__ +#define __CCI_400_H__ + +/* Slave interface offsets from PERIPHBASE */ +#define SLAVE_IFACE4_OFFSET 0x5000 +#define SLAVE_IFACE3_OFFSET 0x4000 +#define SLAVE_IFACE2_OFFSET 0x3000 +#define SLAVE_IFACE1_OFFSET 0x2000 +#define SLAVE_IFACE0_OFFSET 0x1000 +#define SLAVE_IFACE_OFFSET(index) SLAVE_IFACE0_OFFSET + (0x1000 * index) + +/* Control and ID register offsets */ +#define CTRL_OVERRIDE_REG 0x0 +#define SPEC_CTRL_REG 0x4 +#define SECURE_ACCESS_REG 0x8 +#define STATUS_REG 0xc +#define IMPRECISE_ERR_REG 0x10 +#define PERFMON_CTRL_REG 0x100 + +/* Slave interface register offsets */ +#define SNOOP_CTRL_REG 0x0 +#define SH_OVERRIDE_REG 0x4 +#define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100 +#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104 +#define QOS_CTRL_REG 0x10c +#define MAX_OT_REG 0x110 +#define TARGET_LATENCY_REG 0x130 +#define LATENCY_REGULATION_REG 0x134 +#define QOS_RANGE_REG 0x138 + +/* Snoop Control register bit definitions */ +#define DVM_EN_BIT (1 << 1) +#define SNOOP_EN_BIT (1 << 0) + +/* Status register bit definitions */ +#define CHANGE_PENDING_BIT (1 << 0) + +/* Function declarations */ +extern void cci_enable_coherency(unsigned long mpidr); +extern void cci_disable_coherency(unsigned long mpidr); + +#endif /* __CCI_400_H__ */ diff --git a/include/drivers/arm/gic.h b/include/drivers/arm/gic.h new file mode 100644 index 0000000..3266043 --- /dev/null +++ b/include/drivers/arm/gic.h @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GIC_H__ +#define __GIC_H__ + +#define MAX_SPIS 480 +#define MAX_PPIS 14 +#define MAX_SGIS 16 + +#define GRP0 0 +#define GRP1 1 +#define GIC_PRI_MASK 0xff +#define GIC_HIGHEST_SEC_PRIORITY 0 +#define GIC_LOWEST_SEC_PRIORITY 127 +#define GIC_HIGHEST_NS_PRIORITY 128 +#define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */ + +#define ENABLE_GRP0 (1 << 0) +#define ENABLE_GRP1 (1 << 1) + +/* Distributor interface definitions */ +#define GICD_CTLR 0x0 +#define GICD_TYPER 0x4 +#define GICD_IGROUPR 0x80 +#define GICD_ISENABLER 0x100 +#define GICD_ICENABLER 0x180 +#define GICD_ISPENDR 0x200 +#define GICD_ICPENDR 0x280 +#define GICD_ISACTIVER 0x300 +#define GICD_ICACTIVER 0x380 +#define GICD_IPRIORITYR 0x400 +#define GICD_ITARGETSR 0x800 +#define GICD_ICFGR 0xC00 +#define GICD_SGIR 0xF00 +#define GICD_CPENDSGIR 0xF10 +#define GICD_SPENDSGIR 0xF20 + +#define IGROUPR_SHIFT 5 +#define ISENABLER_SHIFT 5 +#define ICENABLER_SHIFT ISENABLER_SHIFT +#define ISPENDR_SHIFT 5 +#define ICPENDR_SHIFT ISPENDR_SHIFT +#define ISACTIVER_SHIFT 5 +#define ICACTIVER_SHIFT ISACTIVER_SHIFT +#define IPRIORITYR_SHIFT 2 +#define ITARGETSR_SHIFT 2 +#define ICFGR_SHIFT 4 +#define CPENDSGIR_SHIFT 2 +#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT + +/* GICD_TYPER bit definitions */ +#define IT_LINES_NO_MASK 0x1f + +/* Physical CPU Interface registers */ +#define GICC_CTLR 0x0 +#define GICC_PMR 0x4 +#define GICC_BPR 0x8 +#define GICC_IAR 0xC +#define GICC_EOIR 0x10 +#define GICC_RPR 0x14 +#define GICC_HPPIR 0x18 +#define GICC_IIDR 0xFC +#define GICC_DIR 0x1000 +#define GICC_PRIODROP GICC_EOIR + +/* GICC_CTLR bit definitions */ +#define EOI_MODE_NS (1 << 10) +#define EOI_MODE_S (1 << 9) +#define IRQ_BYP_DIS_GRP1 (1 << 8) +#define FIQ_BYP_DIS_GRP1 (1 << 7) +#define IRQ_BYP_DIS_GRP0 (1 << 6) +#define FIQ_BYP_DIS_GRP0 (1 << 5) +#define CBPR (1 << 4) +#define FIQ_EN (1 << 3) +#define ACK_CTL (1 << 2) + +/* GICC_IIDR bit masks and shifts */ +#define GICC_IIDR_PID_SHIFT 20 +#define GICC_IIDR_ARCH_SHIFT 16 +#define GICC_IIDR_REV_SHIFT 12 +#define GICC_IIDR_IMP_SHIFT 0 + +#define GICC_IIDR_PID_MASK 0xfff +#define GICC_IIDR_ARCH_MASK 0xf +#define GICC_IIDR_REV_MASK 0xf +#define GICC_IIDR_IMP_MASK 0xfff + +/* HYP view virtual CPU Interface registers */ +#define GICH_CTL 0x0 +#define GICH_VTR 0x4 +#define GICH_ELRSR0 0x30 +#define GICH_ELRSR1 0x34 +#define GICH_APR0 0xF0 +#define GICH_LR_BASE 0x100 + +/* Virtual CPU Interface registers */ +#define GICV_CTL 0x0 +#define GICV_PRIMASK 0x4 +#define GICV_BP 0x8 +#define GICV_INTACK 0xC +#define GICV_EOI 0x10 +#define GICV_RUNNINGPRI 0x14 +#define GICV_HIGHESTPEND 0x18 +#define GICV_DEACTIVATE 0x1000 + +/* GICv3 Re-distributor interface registers & shifts */ +#define GICR_PCPUBASE_SHIFT 0x11 +#define GICR_TYPER 0x08 +#define GICR_WAKER 0x14 + +/* GICR_WAKER bit definitions */ +#define WAKER_CA (1UL << 2) +#define WAKER_PS (1UL << 1) + +/* GICR_TYPER bit definitions */ +#define GICR_TYPER_AFF_SHIFT 32 +#define GICR_TYPER_AFF_MASK 0xffffffff +#define GICR_TYPER_LAST (1UL << 4) + +/* GICv3 ICC_SRE register bit definitions*/ +#define ICC_SRE_EN (1UL << 3) +#define ICC_SRE_SRE (1UL << 0) + +#ifndef __ASSEMBLY__ + +#include +#include + +/******************************************************************************* + * Function prototypes + ******************************************************************************/ + +extern unsigned int gicd_read_igroupr(unsigned int, unsigned int); +extern unsigned int gicd_read_isenabler(unsigned int, unsigned int); +extern unsigned int gicd_read_icenabler(unsigned int, unsigned int); +extern unsigned int gicd_read_ispendr(unsigned int, unsigned int); +extern unsigned int gicd_read_icpendr(unsigned int, unsigned int); +extern unsigned int gicd_read_isactiver(unsigned int, unsigned int); +extern unsigned int gicd_read_icactiver(unsigned int, unsigned int); +extern unsigned int gicd_read_ipriorityr(unsigned int, unsigned int); +extern unsigned int gicd_read_itargetsr(unsigned int, unsigned int); +extern unsigned int gicd_read_icfgr(unsigned int, unsigned int); +extern unsigned int gicd_read_cpendsgir(unsigned int, unsigned int); +extern unsigned int gicd_read_spendsgir(unsigned int, unsigned int); +extern void gicd_write_igroupr(unsigned int, unsigned int, unsigned int); +extern void gicd_write_isenabler(unsigned int, unsigned int, unsigned int); +extern void gicd_write_icenabler(unsigned int, unsigned int, unsigned int); +extern void gicd_write_ispendr(unsigned int, unsigned int, unsigned int); +extern void gicd_write_icpendr(unsigned int, unsigned int, unsigned int); +extern void gicd_write_isactiver(unsigned int, unsigned int, unsigned int); +extern void gicd_write_icactiver(unsigned int, unsigned int, unsigned int); +extern void gicd_write_ipriorityr(unsigned int, unsigned int, unsigned int); +extern void gicd_write_itargetsr(unsigned int, unsigned int, unsigned int); +extern void gicd_write_icfgr(unsigned int, unsigned int, unsigned int); +extern void gicd_write_cpendsgir(unsigned int, unsigned int, unsigned int); +extern void gicd_write_spendsgir(unsigned int, unsigned int, unsigned int); +extern unsigned int gicd_get_igroupr(unsigned int, unsigned int); +extern void gicd_set_igroupr(unsigned int, unsigned int); +extern void gicd_clr_igroupr(unsigned int, unsigned int); +extern void gicd_set_isenabler(unsigned int, unsigned int); +extern void gicd_set_icenabler(unsigned int, unsigned int); +extern void gicd_set_ispendr(unsigned int, unsigned int); +extern void gicd_set_icpendr(unsigned int, unsigned int); +extern void gicd_set_isactiver(unsigned int, unsigned int); +extern void gicd_set_icactiver(unsigned int, unsigned int); +extern void gicd_set_ipriorityr(unsigned int, unsigned int, unsigned int); +extern void gicd_set_itargetsr(unsigned int, unsigned int, unsigned int); + +/* GICv3 functions */ + +extern unsigned int read_icc_sre_el1(void); +extern unsigned int read_icc_sre_el2(void); +extern unsigned int read_icc_sre_el3(void); +extern void write_icc_sre_el1(unsigned int); +extern void write_icc_sre_el2(unsigned int); +extern void write_icc_sre_el3(unsigned int); +extern void write_icc_pmr_el1(unsigned int); + +#endif /*__ASSEMBLY__*/ + +#endif /* __GIC_H__ */ + diff --git a/include/drivers/arm/gic_v2.h b/include/drivers/arm/gic_v2.h new file mode 100644 index 0000000..30bd4fc --- /dev/null +++ b/include/drivers/arm/gic_v2.h @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GIC_V2_H__ +#define __GIC_V2_H__ + +#include + +/******************************************************************************* + * GIC Distributor interface accessors for reading entire registers + ******************************************************************************/ + +static inline unsigned int gicd_read_ctlr(unsigned int base) +{ + return mmio_read_32(base + GICD_CTLR); +} + +static inline unsigned int gicd_read_typer(unsigned int base) +{ + return mmio_read_32(base + GICD_TYPER); +} + +static inline unsigned int gicd_read_sgir(unsigned int base) +{ + return mmio_read_32(base + GICD_SGIR); +} + + +/******************************************************************************* + * GIC Distributor interface accessors for writing entire registers + ******************************************************************************/ + +static inline void gicd_write_ctlr(unsigned int base, unsigned int val) +{ + mmio_write_32(base + GICD_CTLR, val); +} + +static inline void gicd_write_sgir(unsigned int base, unsigned int val) +{ + mmio_write_32(base + GICD_SGIR, val); +} + + +/******************************************************************************* + * GIC CPU interface accessors for reading entire registers + ******************************************************************************/ + +static inline unsigned int gicc_read_ctlr(unsigned int base) +{ + return mmio_read_32(base + GICC_CTLR); +} + +static inline unsigned int gicc_read_pmr(unsigned int base) +{ + return mmio_read_32(base + GICC_PMR); +} + +static inline unsigned int gicc_read_BPR(unsigned int base) +{ + return mmio_read_32(base + GICC_BPR); +} + +static inline unsigned int gicc_read_IAR(unsigned int base) +{ + return mmio_read_32(base + GICC_IAR); +} + +static inline unsigned int gicc_read_EOIR(unsigned int base) +{ + return mmio_read_32(base + GICC_EOIR); +} + +static inline unsigned int gicc_read_hppir(unsigned int base) +{ + return mmio_read_32(base + GICC_HPPIR); +} + +static inline unsigned int gicc_read_dir(unsigned int base) +{ + return mmio_read_32(base + GICC_DIR); +} + +static inline unsigned int gicc_read_iidr(unsigned int base) +{ + return mmio_read_32(base + GICC_IIDR); +} + + +/******************************************************************************* + * GIC CPU interface accessors for writing entire registers + ******************************************************************************/ + +static inline void gicc_write_ctlr(unsigned int base, unsigned int val) +{ + mmio_write_32(base + GICC_CTLR, val); +} + +static inline void gicc_write_pmr(unsigned int base, unsigned int val) +{ + mmio_write_32(base + GICC_PMR, val); +} + +static inline void gicc_write_BPR(unsigned int base, unsigned int val) +{ + mmio_write_32(base + GICC_BPR, val); +} + + +static inline void gicc_write_IAR(unsigned int base, unsigned int val) +{ + mmio_write_32(base + GICC_IAR, val); +} + +static inline void gicc_write_EOIR(unsigned int base, unsigned int val) +{ + mmio_write_32(base + GICC_EOIR, val); +} + +static inline void gicc_write_hppir(unsigned int base, unsigned int val) +{ + mmio_write_32(base + GICC_HPPIR, val); +} + +static inline void gicc_write_dir(unsigned int base, unsigned int val) +{ + mmio_write_32(base + GICC_DIR, val); +} + +#endif /* __GIC_V2_H__ */ diff --git a/include/drivers/arm/gic_v3.h b/include/drivers/arm/gic_v3.h new file mode 100644 index 0000000..df7e7fd --- /dev/null +++ b/include/drivers/arm/gic_v3.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GIC_V3_H__ +#define __GIC_V3_H__ + +#include +#include + +#define GICV3_AFFLVL_MASK 0xff +#define GICV3_AFF0_SHIFT 0 +#define GICV3_AFF1_SHIFT 8 +#define GICV3_AFF2_SHIFT 16 +#define GICV3_AFF3_SHIFT 24 +#define GICV3_AFFINITY_MASK 0xffffffff + +uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr); + +/******************************************************************************* + * GIC Redistributor interface accessors + ******************************************************************************/ +static inline uint32_t gicr_read_waker(uintptr_t base) +{ + return mmio_read_32(base + GICR_WAKER); +} + +static inline void gicr_write_waker(uintptr_t base, uint32_t val) +{ + mmio_write_32(base + GICR_WAKER, val); +} + +static inline uint64_t gicr_read_typer(uintptr_t base) +{ + return mmio_read_64(base + GICR_TYPER); +} + + +#endif /* __GIC_V3_H__ */ diff --git a/include/drivers/arm/pl011.h b/include/drivers/arm/pl011.h new file mode 100644 index 0000000..5ad2fc7 --- /dev/null +++ b/include/drivers/arm/pl011.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PL011_H__ +#define __PL011_H__ + +/* PL011 Registers */ +#define UARTDR 0x000 +#define UARTRSR 0x004 +#define UARTECR 0x004 +#define UARTFR 0x018 +#define UARTILPR 0x020 +#define UARTIBRD 0x024 +#define UARTFBRD 0x028 +#define UARTLCR_H 0x02C +#define UARTCR 0x030 +#define UARTIFLS 0x034 +#define UARTIMSC 0x038 +#define UARTRIS 0x03C +#define UARTMIS 0x040 +#define UARTICR 0x044 +#define UARTDMACR 0x048 + +/* Data status bits */ +#define UART_DATA_ERROR_MASK 0x0F00 + +/* Status reg bits */ +#define UART_STATUS_ERROR_MASK 0x0F + +/* Flag reg bits */ +#define PL011_UARTFR_RI (1 << 8) /* Ring indicator */ +#define PL011_UARTFR_TXFE (1 << 7) /* Transmit FIFO empty */ +#define PL011_UARTFR_RXFF (1 << 6) /* Receive FIFO full */ +#define PL011_UARTFR_TXFF (1 << 5) /* Transmit FIFO full */ +#define PL011_UARTFR_RXFE (1 << 4) /* Receive FIFO empty */ +#define PL011_UARTFR_BUSY (1 << 3) /* UART busy */ +#define PL011_UARTFR_DCD (1 << 2) /* Data carrier detect */ +#define PL011_UARTFR_DSR (1 << 1) /* Data set ready */ +#define PL011_UARTFR_CTS (1 << 0) /* Clear to send */ + +/* Control reg bits */ +#define PL011_UARTCR_CTSEN (1 << 15) /* CTS hardware flow control enable */ +#define PL011_UARTCR_RTSEN (1 << 14) /* RTS hardware flow control enable */ +#define PL011_UARTCR_RTS (1 << 11) /* Request to send */ +#define PL011_UARTCR_DTR (1 << 10) /* Data transmit ready. */ +#define PL011_UARTCR_RXE (1 << 9) /* Receive enable */ +#define PL011_UARTCR_TXE (1 << 8) /* Transmit enable */ +#define PL011_UARTCR_LBE (1 << 7) /* Loopback enable */ +#define PL011_UARTCR_UARTEN (1 << 0) /* UART Enable */ + +#if !defined(PL011_BASE) +#error "The PL011_BASE macro must be defined." +#endif + +#if !defined(PL011_BAUDRATE) +#define PL011_BAUDRATE 115200 +#endif + +#if !defined(PL011_CLK_IN_HZ) +#define PL011_CLK_IN_HZ 24000000 +#endif + +#if !defined(PL011_LINE_CONTROL) +/* FIFO Enabled / No Parity / 8 Data bit / One Stop Bit */ +#define PL011_LINE_CONTROL (PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8) +#endif + +/* Line Control Register Bits */ +#define PL011_UARTLCR_H_SPS (1 << 7) /* Stick parity select */ +#define PL011_UARTLCR_H_WLEN_8 (3 << 5) +#define PL011_UARTLCR_H_WLEN_7 (2 << 5) +#define PL011_UARTLCR_H_WLEN_6 (1 << 5) +#define PL011_UARTLCR_H_WLEN_5 (0 << 5) +#define PL011_UARTLCR_H_FEN (1 << 4) /* FIFOs Enable */ +#define PL011_UARTLCR_H_STP2 (1 << 3) /* Two stop bits select */ +#define PL011_UARTLCR_H_EPS (1 << 2) /* Even parity select */ +#define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */ +#define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */ + +/******************************************************************************* + * Pl011 CPU interface accessors for writing registers + ******************************************************************************/ + +static inline void pl011_write_ibrd(unsigned int base, unsigned int val) +{ + mmio_write_32(base + UARTIBRD, val); +} + +static inline void pl011_write_fbrd(unsigned int base, unsigned int val) +{ + mmio_write_32(base + UARTFBRD, val); +} + +static inline void pl011_write_lcr_h(unsigned int base, unsigned int val) +{ + mmio_write_32(base + UARTLCR_H, val); +} + +static inline void pl011_write_ecr(unsigned int base, unsigned int val) +{ + mmio_write_32(base + UARTECR, val); +} + +static inline void pl011_write_cr(unsigned int base, unsigned int val) +{ + mmio_write_32(base + UARTCR, val); +} + +static inline void pl011_write_dr(unsigned int base, unsigned int val) +{ + mmio_write_32(base + UARTDR, val); +} + +/******************************************************************************* + * Pl011 CPU interface accessors for reading registers + ******************************************************************************/ + +static inline unsigned int pl011_read_fr(unsigned int base) +{ + return mmio_read_32(base + UARTFR); +} + +static inline unsigned int pl011_read_dr(unsigned int base) +{ + return mmio_read_32(base + UARTDR); +} + +/******************************************************************************* + * Function prototypes + ******************************************************************************/ + +void pl011_setbaudrate(unsigned long base_addr, unsigned int baudrate); + +#endif /* __PL011_H__ */ diff --git a/include/drivers/arm/tzc400.h b/include/drivers/arm/tzc400.h new file mode 100644 index 0000000..7eaafd2 --- /dev/null +++ b/include/drivers/arm/tzc400.h @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TZC400_H__ +#define __TZC400_H__ + +#include + +#define BUILD_CONFIG_OFF 0x000 +#define ACTION_OFF 0x004 +#define GATE_KEEPER_OFF 0x008 +#define SPECULATION_CTRL_OFF 0x00c +#define INT_STATUS 0x010 +#define INT_CLEAR 0x014 + +#define FAIL_ADDRESS_LOW_OFF 0x020 +#define FAIL_ADDRESS_HIGH_OFF 0x024 +#define FAIL_CONTROL_OFF 0x028 +#define FAIL_ID 0x02c + +#define REGION_BASE_LOW_OFF 0x100 +#define REGION_BASE_HIGH_OFF 0x104 +#define REGION_TOP_LOW_OFF 0x108 +#define REGION_TOP_HIGH_OFF 0x10c +#define REGION_ATTRIBUTES_OFF 0x110 +#define REGION_ID_ACCESS_OFF 0x114 +#define REGION_NUM_OFF(region) (0x20 * region) + +/* ID Registers */ +#define PID0_OFF 0xfe0 +#define PID1_OFF 0xfe4 +#define PID2_OFF 0xfe8 +#define PID3_OFF 0xfec +#define PID4_OFF 0xfd0 +#define PID5_OFF 0xfd4 +#define PID6_OFF 0xfd8 +#define PID7_OFF 0xfdc +#define CID0_OFF 0xff0 +#define CID1_OFF 0xff4 +#define CID2_OFF 0xff8 +#define CID3_OFF 0xffc + +#define BUILD_CONFIG_NF_SHIFT 24 +#define BUILD_CONFIG_NF_MASK 0x3 +#define BUILD_CONFIG_AW_SHIFT 8 +#define BUILD_CONFIG_AW_MASK 0x3f +#define BUILD_CONFIG_NR_SHIFT 0 +#define BUILD_CONFIG_NR_MASK 0x1f + +/* Not describing the case where regions 1 to 8 overlap */ +#define ACTION_RV_SHIFT 0 +#define ACTION_RV_MASK 0x3 +#define ACTION_RV_LOWOK 0x0 +#define ACTION_RV_LOWERR 0x1 +#define ACTION_RV_HIGHOK 0x2 +#define ACTION_RV_HIGHERR 0x3 + +/* + * Number of gate keepers is implementation defined. But we know the max for + * this device is 4. Get implementation details from BUILD_CONFIG. + */ +#define GATE_KEEPER_OS_SHIFT 16 +#define GATE_KEEPER_OS_MASK 0xf +#define GATE_KEEPER_OR_SHIFT 0 +#define GATE_KEEPER_OR_MASK 0xf + +/* Speculation is enabled by default. */ +#define SPECULATION_CTRL_WRITE_DISABLE (1 << 1) +#define SPECULATION_CTRL_READ_DISABLE (1 << 0) + +/* Max number of filters allowed is 4. */ +#define INT_STATUS_OVERLAP_SHIFT 16 +#define INT_STATUS_OVERLAP_MASK 0xf +#define INT_STATUS_OVERRUN_SHIFT 8 +#define INT_STATUS_OVERRUN_MASK 0xf +#define INT_STATUS_STATUS_SHIFT 0 +#define INT_STATUS_STATUS_MASK 0xf + +#define INT_CLEAR_CLEAR_SHIFT 0 +#define INT_CLEAR_CLEAR_MASK 0xf + +#define FAIL_CONTROL_DIR_SHIFT (1 << 24) +#define FAIL_CONTROL_DIR_READ 0x0 +#define FAIL_CONTROL_DIR_WRITE 0x1 +#define FAIL_CONTROL_NS_SHIFT (1 << 21) +#define FAIL_CONTROL_NS_SECURE 0x0 +#define FAIL_CONTROL_NS_NONSECURE 0x1 +#define FAIL_CONTROL_PRIV_SHIFT (1 << 20) +#define FAIL_CONTROL_PRIV_PRIV 0x0 +#define FAIL_CONTROL_PRIV_UNPRIV 0x1 + +/* + * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific. + * Platform should provide the value on initialisation. + */ +#define FAIL_ID_VNET_SHIFT 24 +#define FAIL_ID_VNET_MASK 0xf +#define FAIL_ID_ID_SHIFT 0 + +/* Used along with 'tzc_region_attributes_t' below */ +#define REGION_ATTRIBUTES_SEC_SHIFT 30 +#define REGION_ATTRIBUTES_F_EN_SHIFT 0 +#define REGION_ATTRIBUTES_F_EN_MASK 0xf + +#define REGION_ID_ACCESS_NSAID_WR_EN_SHIFT 16 +#define REGION_ID_ACCESS_NSAID_RD_EN_SHIFT 0 +#define REGION_ID_ACCESS_NSAID_ID_MASK 0xf + + +/* Macros for setting Region ID access permissions based on NSAID */ +#define TZC_REGION_ACCESS_RD(id) \ + ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \ + REGION_ID_ACCESS_NSAID_RD_EN_SHIFT) +#define TZC_REGION_ACCESS_WR(id) \ + ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \ + REGION_ID_ACCESS_NSAID_WR_EN_SHIFT) +#define TZC_REGION_ACCESS_RDWR(id) \ + (TZC_REGION_ACCESS_RD(id) | TZC_REGION_ACCESS_WR(id)) + +/* Filters are bit mapped 0 to 3. */ +#define TZC400_COMPONENT_ID 0xb105f00d + +#ifndef __ASSEMBLY__ + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ + +/* + * What type of action is expected when an access violation occurs. + * The memory requested is zeroed. But we can also raise and event to + * let the system know it happened. + * We can raise an interrupt(INT) and/or cause an exception(ERR). + * TZC_ACTION_NONE - No interrupt, no Exception + * TZC_ACTION_ERR - No interrupt, raise exception -> sync external + * data abort + * TZC_ACTION_INT - Raise interrupt, no exception + * TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync + * external data abort + */ +enum tzc_action { + TZC_ACTION_NONE = 0, + TZC_ACTION_ERR = 1, + TZC_ACTION_INT = 2, + TZC_ACTION_ERR_INT = (TZC_ACTION_ERR | TZC_ACTION_INT) +}; + +/* + * Controls secure access to a region. If not enabled secure access is not + * allowed to region. + */ +enum tzc_region_attributes { + TZC_REGION_S_NONE = 0, + TZC_REGION_S_RD = 1, + TZC_REGION_S_WR = 2, + TZC_REGION_S_RDWR = (TZC_REGION_S_RD | TZC_REGION_S_WR) +}; + +/* + * Implementation defined values used to validate inputs later. + * Filters : max of 4 ; 0 to 3 + * Regions : max of 9 ; 0 to 8 + * Address width : Values between 32 to 64 + */ +struct tzc_instance { + uint64_t base; + uint32_t aid_width; + uint8_t addr_width; + uint8_t num_filters; + uint8_t num_regions; +}; + +void tzc_init(struct tzc_instance *controller); +void tzc_configure_region(const struct tzc_instance *controller, uint32_t filters, + uint8_t region, uint64_t region_base, uint64_t region_top, + enum tzc_region_attributes sec_attr, uint32_t ns_device_access); +void tzc_enable_filters(const struct tzc_instance *controller); +void tzc_disable_filters(const struct tzc_instance *controller); +void tzc_set_action(const struct tzc_instance *controller, + enum tzc_action action); + +#endif /*__ASSEMBLY__*/ + +#endif /* __TZC400__ */ diff --git a/include/drivers/console.h b/include/drivers/console.h new file mode 100644 index 0000000..e285909 --- /dev/null +++ b/include/drivers/console.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CONSOLE_H__ +#define __CONSOLE_H__ + +void console_init(unsigned long base_addr); +int console_putc(int c); +int console_getc(void); + +#endif /* __CONSOLE_H__ */ + diff --git a/include/drivers/fvp_pwrc.h b/include/drivers/fvp_pwrc.h new file mode 100644 index 0000000..f600a24 --- /dev/null +++ b/include/drivers/fvp_pwrc.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FVP_PWRC_H__ +#define __FVP_PWRC_H__ + +/* FVP Power controller register offset etc */ +#define PPOFFR_OFF 0x0 +#define PPONR_OFF 0x4 +#define PCOFFR_OFF 0x8 +#define PWKUPR_OFF 0xc +#define PSYSR_OFF 0x10 + +#define PWKUPR_WEN (1ull << 31) + +#define PSYSR_AFF_L2 (1 << 31) +#define PSYSR_AFF_L1 (1 << 30) +#define PSYSR_AFF_L0 (1 << 29) +#define PSYSR_WEN (1 << 28) +#define PSYSR_PC (1 << 27) +#define PSYSR_PP (1 << 26) + +#define PSYSR_WK_SHIFT 24 +#define PSYSR_WK_MASK 0x3 +#define PSYSR_WK(x) (x >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK + +#define WKUP_COLD 0x0 +#define WKUP_RESET 0x1 +#define WKUP_PPONR 0x2 +#define WKUP_GICREQ 0x3 + +#define PSYSR_INVALID 0xffffffff + +#ifndef __ASSEMBLY__ + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +extern int fvp_pwrc_setup(void); +extern void fvp_pwrc_write_pcoffr(unsigned long); +extern void fvp_pwrc_write_ppoffr(unsigned long); +extern void fvp_pwrc_write_pponr(unsigned long); +extern void fvp_pwrc_set_wen(unsigned long); +extern void fvp_pwrc_clr_wen(unsigned long); +extern unsigned int fvp_pwrc_read_psysr(unsigned long); +extern unsigned int fvp_pwrc_get_cpu_wkr(unsigned long); + +#endif /*__ASSEMBLY__*/ + +#endif /* __FVP_PWRC_H__ */ diff --git a/include/drivers/io_driver.h b/include/drivers/io_driver.h new file mode 100644 index 0000000..82dbbf1 --- /dev/null +++ b/include/drivers/io_driver.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IO_DRIVER_H__ +#define __IO_DRIVER_H__ + +#include "platform.h" /* For MAX_IO_DEVICES */ + + +/* Generic IO entity structure,representing an accessible IO construct on the + * device, such as a file */ +struct io_entity { + io_dev_handle dev_handle; + uintptr_t info; +}; + + +/* Device info structure, providing device-specific functions and a means of + * adding driver-specific state */ +struct io_dev_info { + struct io_dev_funcs *funcs; + uintptr_t info; +}; + + +/* Structure used to create a connection to a type of device */ +struct io_dev_connector { + /* dev_open opens a connection to a particular device driver */ + int (*dev_open)(void *spec, struct io_dev_info **dev_info); +}; + + +/* Structure to hold device driver function pointers */ +struct io_dev_funcs { + io_type (*type)(void); + int (*open)(struct io_dev_info *dev_info, const void *spec, + struct io_entity *entity); + int (*seek)(struct io_entity *entity, int mode, ssize_t offset); + int (*size)(struct io_entity *entity, size_t *length); + int (*read)(struct io_entity *entity, void *buffer, size_t length, + size_t *length_read); + int (*write)(struct io_entity *entity, const void *buffer, + size_t length, size_t *length_written); + int (*close)(struct io_entity *entity); + int (*dev_init)(struct io_dev_info *dev_info, const void *init_params); + int (*dev_close)(struct io_dev_info *dev_info); +}; + + +/* IO platform data - used to track devices registered for a specific + * platform */ +struct io_plat_data { + struct io_dev_info *devices[MAX_IO_DEVICES]; + unsigned int dev_count; +}; + + +/* Operations intended to be performed during platform initialisation */ + +/* Initialise the IO layer */ +void io_init(struct io_plat_data *data); + +/* Register a device driver */ +int io_register_device(struct io_dev_info *dev_info); + +#endif /* __IO_DRIVER_H__ */ diff --git a/include/drivers/io_fip.h b/include/drivers/io_fip.h new file mode 100644 index 0000000..56dd1e0 --- /dev/null +++ b/include/drivers/io_fip.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2014 ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IO_FIP_H__ +#define __IO_FIP_H__ + +int register_io_dev_fip(struct io_dev_connector **dev_con); + +#endif /* __IO_FIP_H__ */ diff --git a/include/drivers/io_memmap.h b/include/drivers/io_memmap.h new file mode 100644 index 0000000..5fa7bc9 --- /dev/null +++ b/include/drivers/io_memmap.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IO_MEMMAP_H__ +#define __IO_MEMMAP_H__ + +int register_io_dev_memmap(struct io_dev_connector **dev_con); + +#endif /* __IO_MEMMAP_H__ */ diff --git a/include/drivers/io_semihosting.h b/include/drivers/io_semihosting.h new file mode 100644 index 0000000..7dc632d --- /dev/null +++ b/include/drivers/io_semihosting.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IO_SH_H__ +#define __IO_SH_H__ + +int register_io_dev_sh(struct io_dev_connector **dev_con); + +#endif /* __IO_SH_H__ */ diff --git a/include/firmware_image_package.h b/include/firmware_image_package.h deleted file mode 100644 index ff5e971..0000000 --- a/include/firmware_image_package.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __FIRMWARE_IMAGE_PACKAGE_H__ -#define __FIRMWARE_IMAGE_PACKAGE_H__ - -#include -#include - -/* This is used as a signature to validate the blob header */ -#define TOC_HEADER_NAME 0xAA640001 - - -/* ToC Entry UUIDs */ -#define UUID_TRUSTED_BOOT_FIRMWARE_BL2 \ - {0x0becf95f, 0x224d, 0x4d3e, 0xa5, 0x44, {0xc3, 0x9d, 0x81, 0xc7, 0x3f, 0x0a} } -#define UUID_SCP_FIRMWARE_BL30 \ - {0x3dfd6697, 0xbe89, 0x49e8, 0xae, 0x5d, {0x78, 0xa1, 0x40, 0x60, 0x82, 0x13} } -#define UUID_EL3_RUNTIME_FIRMWARE_BL31 \ - {0x6d08d447, 0xfe4c, 0x4698, 0x9b, 0x95, {0x29, 0x50, 0xcb, 0xbd, 0x5a, 0x00} } -#define UUID_SECURE_PAYLOAD_BL32 \ - {0x89e1d005, 0xdc53, 0x4713, 0x8d, 0x2b, {0x50, 0x0a, 0x4b, 0x7a, 0x3e, 0x38} } -#define UUID_NON_TRUSTED_FIRMWARE_BL33 \ - {0xa7eed0d6, 0xeafc, 0x4bd5, 0x97, 0x82, {0x99, 0x34, 0xf2, 0x34, 0xb6, 0xe4} } - -typedef struct { - uint32_t name; - uint32_t serial_number; - uint64_t flags; -} fip_toc_header; - -typedef struct { - uuid_t uuid; - uint64_t offset_address; - uint64_t size; - uint64_t flags; -} fip_toc_entry; - -#endif /* __FIRMWARE_IMAGE_PACKAGE_H__ */ diff --git a/include/io_storage.h b/include/io_storage.h deleted file mode 100644 index 04e63c3..0000000 --- a/include/io_storage.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __IO_H__ -#define __IO_H__ - -#ifndef __ASSEMBLY__ - -#include -#include /* For ssize_t */ - - -/* Device type which can be used to enable policy decisions about which device - * to access */ -typedef enum { - IO_TYPE_INVALID, - IO_TYPE_SEMIHOSTING, - IO_TYPE_MEMMAP, - IO_TYPE_FIRMWARE_IMAGE_PACKAGE, - IO_TYPE_MAX -} io_type; - - -/* Modes used when seeking data on a supported device */ -typedef enum { - IO_SEEK_INVALID, - IO_SEEK_SET, - IO_SEEK_END, - IO_SEEK_CUR, - IO_SEEK_MAX -} io_seek_mode; - - -/* Connector type, providing a means of identifying a device to open */ -struct io_dev_connector; - -/* Device handle, providing a client with access to a specific device */ -typedef struct io_dev_info *io_dev_handle; - -/* IO handle, providing a client with access to a specific source of data from - * a device */ -typedef struct io_entity *io_handle; - - -/* File specification - used to refer to data on a device supporting file-like - * entities */ -typedef struct { - const char *path; - unsigned int mode; -} io_file_spec; - - -/* Block specification - used to refer to data on a device supporting - * block-like entities */ -typedef struct { - unsigned long offset; - size_t length; -} io_block_spec; - - -/* Access modes used when accessing data on a device */ -#define IO_MODE_INVALID (0) -#define IO_MODE_RO (1 << 0) -#define IO_MODE_RW (1 << 1) - - -/* Return codes reported by 'io_*' APIs */ -#define IO_SUCCESS (0) -#define IO_FAIL (-1) -#define IO_NOT_SUPPORTED (-2) -#define IO_RESOURCES_EXHAUSTED (-3) - - -/* Open a connection to a device */ -int io_dev_open(struct io_dev_connector *dev_con, void *dev_spec, - io_dev_handle *dev_handle); - - -/* Initialise a device explicitly - to permit lazy initialisation or - * re-initialisation */ -int io_dev_init(io_dev_handle dev_handle, const void *init_params); - -/* TODO: Consider whether an explicit "shutdown" API should be included */ - -/* Close a connection to a device */ -int io_dev_close(io_dev_handle dev_handle); - - -/* Synchronous operations */ -int io_open(io_dev_handle dev_handle, const void *spec, io_handle *handle); - -int io_seek(io_handle handle, io_seek_mode mode, ssize_t offset); - -int io_size(io_handle handle, size_t *length); - -int io_read(io_handle handle, void *buffer, size_t length, size_t *length_read); - -int io_write(io_handle handle, const void *buffer, size_t length, - size_t *length_written); - -int io_close(io_handle handle); - - -#endif /* __ASSEMBLY__ */ -#endif /* __IO_H__ */ diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h new file mode 100644 index 0000000..a41e82b --- /dev/null +++ b/include/lib/aarch64/arch.h @@ -0,0 +1,345 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_H__ +#define __ARCH_H__ + +#include + +/******************************************************************************* + * MIDR bit definitions + ******************************************************************************/ +#define MIDR_PN_MASK 0xfff +#define MIDR_PN_SHIFT 0x4 +#define MIDR_PN_AEM 0xd0f +#define MIDR_PN_A57 0xd07 +#define MIDR_PN_A53 0xd03 + +/******************************************************************************* + * MPIDR macros + ******************************************************************************/ +#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK +#define MPIDR_CLUSTER_MASK MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS +#define MPIDR_AFFINITY_BITS 8 +#define MPIDR_AFFLVL_MASK 0xff +#define MPIDR_AFF0_SHIFT 0 +#define MPIDR_AFF1_SHIFT 8 +#define MPIDR_AFF2_SHIFT 16 +#define MPIDR_AFF3_SHIFT 32 +#define MPIDR_AFFINITY_MASK 0xff00ffffff +#define MPIDR_AFFLVL_SHIFT 3 +#define MPIDR_AFFLVL0 0 +#define MPIDR_AFFLVL1 1 +#define MPIDR_AFFLVL2 2 +#define MPIDR_AFFLVL3 3 +/* TODO: Support only the first 3 affinity levels for now */ +#define MPIDR_MAX_AFFLVL 2 + +/* Constant to highlight the assumption that MPIDR allocation starts from 0 */ +#define FIRST_MPIDR 0 + +/******************************************************************************* + * Implementation defined sysreg encodings + ******************************************************************************/ +#define CPUECTLR_EL1 S3_1_C15_C2_1 + +/******************************************************************************* + * Generic timer memory mapped registers & offsets + ******************************************************************************/ +#define CNTCR_OFF 0x000 +#define CNTFID_OFF 0x020 + +#define CNTCR_EN (1 << 0) +#define CNTCR_HDBG (1 << 1) +#define CNTCR_FCREQ(x) ((x) << 8) + +/******************************************************************************* + * System register bit definitions + ******************************************************************************/ +/* CLIDR definitions */ +#define LOUIS_SHIFT 21 +#define LOC_SHIFT 24 +#define CLIDR_FIELD_WIDTH 3 + +/* CSSELR definitions */ +#define LEVEL_SHIFT 1 + +/* D$ set/way op type defines */ +#define DCISW 0x0 +#define DCCISW 0x1 +#define DCCSW 0x2 + +/* ID_AA64PFR0_EL1 definitions */ +#define ID_AA64PFR0_EL0_SHIFT 0 +#define ID_AA64PFR0_EL1_SHIFT 4 +#define ID_AA64PFR0_EL2_SHIFT 8 +#define ID_AA64PFR0_EL3_SHIFT 12 +#define ID_AA64PFR0_ELX_MASK 0xf + +/* ID_PFR1_EL1 definitions */ +#define ID_PFR1_VIRTEXT_SHIFT 12 +#define ID_PFR1_VIRTEXT_MASK 0xf +#define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \ + & ID_PFR1_VIRTEXT_MASK) + +/* SCTLR definitions */ +#define SCTLR_EL2_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \ + (1 << 18) | (1 << 16) | (1 << 11) | (1 << 5) | \ + (1 << 4)) + +#define SCTLR_EL1_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \ + (1 << 11)) +#define SCTLR_M_BIT (1 << 0) +#define SCTLR_A_BIT (1 << 1) +#define SCTLR_C_BIT (1 << 2) +#define SCTLR_SA_BIT (1 << 3) +#define SCTLR_B_BIT (1 << 7) +#define SCTLR_Z_BIT (1 << 11) +#define SCTLR_I_BIT (1 << 12) +#define SCTLR_WXN_BIT (1 << 19) +#define SCTLR_EXCEPTION_BITS (0x3 << 6) +#define SCTLR_EE_BIT (1 << 25) + +/* CPUECTLR definitions */ +#define CPUECTLR_SMP_BIT (1 << 6) + +/* CPACR_El1 definitions */ +#define CPACR_EL1_FPEN(x) (x << 20) +#define CPACR_EL1_FP_TRAP_EL0 0x1 +#define CPACR_EL1_FP_TRAP_ALL 0x2 +#define CPACR_EL1_FP_TRAP_NONE 0x3 + +/* SCR definitions */ +#define SCR_RES1_BITS ((1 << 4) | (1 << 5)) +#define SCR_TWE_BIT (1 << 13) +#define SCR_TWI_BIT (1 << 12) +#define SCR_ST_BIT (1 << 11) +#define SCR_RW_BIT (1 << 10) +#define SCR_SIF_BIT (1 << 9) +#define SCR_HCE_BIT (1 << 8) +#define SCR_SMD_BIT (1 << 7) +#define SCR_EA_BIT (1 << 3) +#define SCR_FIQ_BIT (1 << 2) +#define SCR_IRQ_BIT (1 << 1) +#define SCR_NS_BIT (1 << 0) + +/* HCR definitions */ +#define HCR_RW_BIT (1ull << 31) +#define HCR_AMO_BIT (1 << 5) +#define HCR_IMO_BIT (1 << 4) +#define HCR_FMO_BIT (1 << 3) + +/* CNTHCTL_EL2 definitions */ +#define EL1PCEN_BIT (1 << 1) +#define EL1PCTEN_BIT (1 << 0) + +/* CNTKCTL_EL1 definitions */ +#define EL0PTEN_BIT (1 << 9) +#define EL0VTEN_BIT (1 << 8) +#define EL0PCTEN_BIT (1 << 0) +#define EL0VCTEN_BIT (1 << 1) + +/* CPTR_EL3 definitions */ +#define TCPAC_BIT (1 << 31) +#define TTA_BIT (1 << 20) +#define TFP_BIT (1 << 10) + +/* CPSR/SPSR definitions */ +#define DAIF_FIQ_BIT (1 << 0) +#define DAIF_IRQ_BIT (1 << 1) +#define DAIF_ABT_BIT (1 << 2) +#define DAIF_DBG_BIT (1 << 3) +#define PSR_DAIF_SHIFT 0x6 + +/* + * TCR defintions + */ +#define TCR_EL3_RES1 ((1UL << 31) | (1UL << 23)) + +#define TCR_T0SZ_4GB 32 + +#define TCR_RGN_INNER_NC (0x0 << 8) +#define TCR_RGN_INNER_WBA (0x1 << 8) +#define TCR_RGN_INNER_WT (0x2 << 8) +#define TCR_RGN_INNER_WBNA (0x3 << 8) + +#define TCR_RGN_OUTER_NC (0x0 << 10) +#define TCR_RGN_OUTER_WBA (0x1 << 10) +#define TCR_RGN_OUTER_WT (0x2 << 10) +#define TCR_RGN_OUTER_WBNA (0x3 << 10) + +#define TCR_SH_NON_SHAREABLE (0x0 << 12) +#define TCR_SH_OUTER_SHAREABLE (0x2 << 12) +#define TCR_SH_INNER_SHAREABLE (0x3 << 12) + +#define MODE_RW_64 0x0 +#define MODE_RW_32 0x1 +#define MODE_SP_EL0 0x0 +#define MODE_SP_ELX 0x1 +#define MODE_EL3 0x3 +#define MODE_EL2 0x2 +#define MODE_EL1 0x1 +#define MODE_EL0 0x0 + +#define MODE_RW_SHIFT 0x4 +#define MODE_EL_SHIFT 0x2 +#define MODE_SP_SHIFT 0x0 + +#define GET_RW(mode) ((mode >> MODE_RW_SHIFT) & 0x1) +#define GET_EL(mode) ((mode >> MODE_EL_SHIFT) & 0x3) +#define PSR_MODE(rw, el, sp) (rw << MODE_RW_SHIFT | el << MODE_EL_SHIFT \ + | sp << MODE_SP_SHIFT) + +#define SPSR32_EE_BIT (1 << 9) +#define SPSR32_T_BIT (1 << 5) + +#define AARCH32_MODE_SVC 0x13 +#define AARCH32_MODE_HYP 0x1a + +/* Miscellaneous MMU related constants */ +#define NUM_2MB_IN_GB (1 << 9) +#define NUM_4K_IN_2MB (1 << 9) +#define NUM_GB_IN_4GB (1 << 2) + +#define TWO_MB_SHIFT 21 +#define ONE_GB_SHIFT 30 +#define FOUR_KB_SHIFT 12 + +#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT) +#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT) +#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT) + +#define INVALID_DESC 0x0 +#define BLOCK_DESC 0x1 +#define TABLE_DESC 0x3 + +#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT +#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT +#define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT + +#define LEVEL1 1 +#define LEVEL2 2 +#define LEVEL3 3 + +#define XN (1ull << 2) +#define PXN (1ull << 1) +#define CONT_HINT (1ull << 0) + +#define UPPER_ATTRS(x) (x & 0x7) << 52 +#define NON_GLOBAL (1 << 9) +#define ACCESS_FLAG (1 << 8) +#define NSH (0x0 << 6) +#define OSH (0x2 << 6) +#define ISH (0x3 << 6) + +#define PAGE_SIZE_SHIFT FOUR_KB_SHIFT +#define PAGE_SIZE (1 << PAGE_SIZE_SHIFT) +#define PAGE_SIZE_MASK (PAGE_SIZE - 1) +#define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0) + +#define XLAT_ENTRY_SIZE_SHIFT 3 /* Each MMU table entry is 8 bytes (1 << 3) */ +#define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SIZE_SHIFT) + +#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT +#define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT) + +/* Values for number of entries in each MMU translation table */ +#define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT) +#define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT) +#define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1) + +/* Values to convert a memory address to an index into a translation table */ +#define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT +#define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) +#define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) + +/* + * AP[1] bit is ignored by hardware and is + * treated as if it is One in EL2/EL3 + */ +#define AP_RO (0x1 << 5) +#define AP_RW (0x0 << 5) + +#define NS (0x1 << 3) +#define ATTR_SO_INDEX 0x2 +#define ATTR_DEVICE_INDEX 0x1 +#define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0 +#define LOWER_ATTRS(x) (((x) & 0xfff) << 2) +#define ATTR_SO (0x0) +#define ATTR_DEVICE (0x4) +#define ATTR_IWBWA_OWBWA_NTR (0xff) +#define MAIR_ATTR_SET(attr, index) (attr << (index << 3)) + +/* Exception Syndrome register bits and bobs */ +#define ESR_EC_SHIFT 26 +#define ESR_EC_MASK 0x3f +#define ESR_EC_LENGTH 6 +#define EC_UNKNOWN 0x0 +#define EC_WFE_WFI 0x1 +#define EC_AARCH32_CP15_MRC_MCR 0x3 +#define EC_AARCH32_CP15_MRRC_MCRR 0x4 +#define EC_AARCH32_CP14_MRC_MCR 0x5 +#define EC_AARCH32_CP14_LDC_STC 0x6 +#define EC_FP_SIMD 0x7 +#define EC_AARCH32_CP10_MRC 0x8 +#define EC_AARCH32_CP14_MRRC_MCRR 0xc +#define EC_ILLEGAL 0xe +#define EC_AARCH32_SVC 0x11 +#define EC_AARCH32_HVC 0x12 +#define EC_AARCH32_SMC 0x13 +#define EC_AARCH64_SVC 0x15 +#define EC_AARCH64_HVC 0x16 +#define EC_AARCH64_SMC 0x17 +#define EC_AARCH64_SYS 0x18 +#define EC_IABORT_LOWER_EL 0x20 +#define EC_IABORT_CUR_EL 0x21 +#define EC_PC_ALIGN 0x22 +#define EC_DABORT_LOWER_EL 0x24 +#define EC_DABORT_CUR_EL 0x25 +#define EC_SP_ALIGN 0x26 +#define EC_AARCH32_FP 0x28 +#define EC_AARCH64_FP 0x2c +#define EC_SERROR 0x2f + +#define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK + +#ifndef __ASSEMBLY__ +/******************************************************************************* + * Function prototypes + ******************************************************************************/ + +extern void early_exceptions(void); +extern void runtime_exceptions(void); +extern void bl1_arch_setup(void); +extern void bl2_arch_setup(void); +extern void bl31_arch_setup(void); +#endif /*__ASSEMBLY__*/ + +#endif /* __ARCH_H__ */ diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h new file mode 100644 index 0000000..f55c003 --- /dev/null +++ b/include/lib/aarch64/arch_helpers.h @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_HELPERS_H__ +#define __ARCH_HELPERS_H__ + +#include + +#ifndef __ASSEMBLY__ +#include + +/******************************************************************************* + * Aarch64 translation tables manipulation helper prototypes + ******************************************************************************/ +extern unsigned long create_table_desc(unsigned long *next_table_ptr); +extern unsigned long create_block_desc(unsigned long desc, + unsigned long addr, + unsigned int level); +extern unsigned long create_device_block(unsigned long output_addr, + unsigned int level, + unsigned int ns); +extern unsigned long create_romem_block(unsigned long output_addr, + unsigned int level, + unsigned int ns); +extern unsigned long create_rwmem_block(unsigned long output_addr, + unsigned int level, + unsigned int ns); + +/******************************************************************************* + * TLB maintenance accessor prototypes + ******************************************************************************/ +extern void tlbialle1(void); +extern void tlbialle1is(void); +extern void tlbialle2(void); +extern void tlbialle2is(void); +extern void tlbialle3(void); +extern void tlbialle3is(void); +extern void tlbivmalle1(void); + +/******************************************************************************* + * Cache maintenance accessor prototypes + ******************************************************************************/ +extern void dcisw(unsigned long); +extern void dccisw(unsigned long); +extern void dccsw(unsigned long); +extern void dccvac(unsigned long); +extern void dcivac(unsigned long); +extern void dccivac(unsigned long); +extern void dccvau(unsigned long); +extern void dczva(unsigned long); +extern void flush_dcache_range(unsigned long, unsigned long); +extern void inv_dcache_range(unsigned long, unsigned long); +extern void dcsw_op_louis(unsigned int); +extern void dcsw_op_all(unsigned int); + +/******************************************************************************* + * Misc. accessor prototypes + ******************************************************************************/ +extern void enable_irq(void); +extern void enable_fiq(void); +extern void enable_serror(void); +extern void enable_debug_exceptions(void); + +extern void disable_irq(void); +extern void disable_fiq(void); +extern void disable_serror(void); +extern void disable_debug_exceptions(void); + +extern unsigned long read_id_pfr1_el1(void); +extern unsigned long read_id_aa64pfr0_el1(void); +extern unsigned long read_current_el(void); +extern unsigned long read_daif(void); +extern unsigned long read_spsr_el1(void); +extern unsigned long read_spsr_el2(void); +extern unsigned long read_spsr_el3(void); +extern unsigned long read_elr_el1(void); +extern unsigned long read_elr_el2(void); +extern unsigned long read_elr_el3(void); + +extern void write_daif(unsigned long); +extern void write_spsr_el1(unsigned long); +extern void write_spsr_el2(unsigned long); +extern void write_spsr_el3(unsigned long); +extern void write_elr_el1(unsigned long); +extern void write_elr_el2(unsigned long); +extern void write_elr_el3(unsigned long); + +extern void wfi(void); +extern void wfe(void); +extern void rfe(void); +extern void sev(void); +extern void dsb(void); +extern void isb(void); + +extern unsigned int get_afflvl_shift(unsigned int); +extern unsigned int mpidr_mask_lower_afflvls(unsigned long, unsigned int); + +extern void __dead2 eret(unsigned long, unsigned long, + unsigned long, unsigned long, + unsigned long, unsigned long, + unsigned long, unsigned long); + +extern void __dead2 smc(unsigned long, unsigned long, + unsigned long, unsigned long, + unsigned long, unsigned long, + unsigned long, unsigned long); + +/******************************************************************************* + * System register accessor prototypes + ******************************************************************************/ +extern unsigned long read_midr(void); +extern unsigned long read_mpidr(void); + +extern unsigned long read_scr(void); +extern unsigned long read_hcr(void); + +extern unsigned long read_vbar_el1(void); +extern unsigned long read_vbar_el2(void); +extern unsigned long read_vbar_el3(void); + +extern unsigned long read_sctlr_el1(void); +extern unsigned long read_sctlr_el2(void); +extern unsigned long read_sctlr_el3(void); + +extern unsigned long read_actlr_el1(void); +extern unsigned long read_actlr_el2(void); +extern unsigned long read_actlr_el3(void); + +extern unsigned long read_esr_el1(void); +extern unsigned long read_esr_el2(void); +extern unsigned long read_esr_el3(void); + +extern unsigned long read_afsr0_el1(void); +extern unsigned long read_afsr0_el2(void); +extern unsigned long read_afsr0_el3(void); + +extern unsigned long read_afsr1_el1(void); +extern unsigned long read_afsr1_el2(void); +extern unsigned long read_afsr1_el3(void); + +extern unsigned long read_far_el1(void); +extern unsigned long read_far_el2(void); +extern unsigned long read_far_el3(void); + +extern unsigned long read_mair_el1(void); +extern unsigned long read_mair_el2(void); +extern unsigned long read_mair_el3(void); + +extern unsigned long read_amair_el1(void); +extern unsigned long read_amair_el2(void); +extern unsigned long read_amair_el3(void); + +extern unsigned long read_rvbar_el1(void); +extern unsigned long read_rvbar_el2(void); +extern unsigned long read_rvbar_el3(void); + +extern unsigned long read_rmr_el1(void); +extern unsigned long read_rmr_el2(void); +extern unsigned long read_rmr_el3(void); + +extern unsigned long read_tcr_el1(void); +extern unsigned long read_tcr_el2(void); +extern unsigned long read_tcr_el3(void); + +extern unsigned long read_ttbr0_el1(void); +extern unsigned long read_ttbr0_el2(void); +extern unsigned long read_ttbr0_el3(void); + +extern unsigned long read_ttbr1(void); +extern unsigned long read_ttbr1_el1(void); +extern unsigned long read_ttbr1_el2(void); + +extern unsigned long read_cptr_el2(void); +extern unsigned long read_cptr_el3(void); + +extern unsigned long read_cpacr(void); +extern unsigned long read_cpuectlr(void); +extern unsigned int read_cntfrq_el0(void); +extern unsigned long read_cnthctl_el2(void); + +extern void write_scr(unsigned long); +extern void write_hcr(unsigned long); +extern void write_cpacr(unsigned long); +extern void write_cntfrq_el0(unsigned int); +extern void write_cnthctl_el2(unsigned long); + +extern void write_vbar_el1(unsigned long); +extern void write_vbar_el2(unsigned long); +extern void write_vbar_el3(unsigned long); + +extern void write_sctlr_el1(unsigned long); +extern void write_sctlr_el2(unsigned long); +extern void write_sctlr_el3(unsigned long); + +extern void write_actlr_el1(unsigned long); +extern void write_actlr_el2(unsigned long); +extern void write_actlr_el3(unsigned long); + +extern void write_esr_el1(unsigned long); +extern void write_esr_el2(unsigned long); +extern void write_esr_el3(unsigned long); + +extern void write_afsr0(unsigned long); +extern void write_afsr0_el1(unsigned long); +extern void write_afsr0_el2(unsigned long); +extern void write_afsr0_el3(unsigned long); + +extern void write_afsr1(unsigned long); +extern void write_afsr1_el1(unsigned long); +extern void write_afsr1_el2(unsigned long); +extern void write_afsr1_el3(unsigned long); + +extern void write_far_el1(unsigned long); +extern void write_far_el2(unsigned long); +extern void write_far_el3(unsigned long); + +extern void write_mair_el1(unsigned long); +extern void write_mair_el2(unsigned long); +extern void write_mair_el3(unsigned long); + +extern void write_amair_el1(unsigned long); +extern void write_amair_el2(unsigned long); +extern void write_amair_el3(unsigned long); + +extern void write_rmr_el1(unsigned long); +extern void write_rmr_el2(unsigned long); +extern void write_rmr_el3(unsigned long); + +extern void write_tcr_el1(unsigned long); +extern void write_tcr_el2(unsigned long); +extern void write_tcr_el3(unsigned long); + +extern void write_ttbr0_el1(unsigned long); +extern void write_ttbr0_el2(unsigned long); +extern void write_ttbr0_el3(unsigned long); + +extern void write_ttbr1_el1(unsigned long); +extern void write_ttbr1_el2(unsigned long); + +extern void write_cpuectlr(unsigned long); +extern void write_cptr_el2(unsigned long); +extern void write_cptr_el3(unsigned long); + +#endif /*__ASSEMBLY__*/ + +#endif /* __ARCH_HELPERS_H__ */ diff --git a/include/lib/aarch64/xlat_tables.h b/include/lib/aarch64/xlat_tables.h new file mode 100644 index 0000000..01b1afe --- /dev/null +++ b/include/lib/aarch64/xlat_tables.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __XLAT_TABLES_H__ +#define __XLAT_TABLES_H__ + +#include + +/* + * Flags for building up memory mapping attributes. + * These are organised so that a clear bit gives a more restrictive mapping + * that a set bit, that way a bitwise-and two sets of attributes will never give + * an attribute which has greater access rights that any of the original + * attributes. + */ +typedef enum { + MT_DEVICE = 0 << 0, + MT_MEMORY = 1 << 0, + + MT_RO = 0 << 1, + MT_RW = 1 << 1, + + MT_SECURE = 0 << 2, + MT_NS = 1 << 2 +} mmap_attr; + +/* + * Structure for specifying a single region of memory. + */ +typedef struct { + unsigned long base; + unsigned long size; + mmap_attr attr; +} mmap_region; + +extern void mmap_add_region(unsigned long base, unsigned long size, + unsigned attr); +extern void mmap_add(const mmap_region *mm); + +extern void init_xlat_tables(void); + +extern uint64_t l1_xlation_table[]; + +#endif /* __XLAT_TABLES_H__ */ diff --git a/include/lib/bakery_lock.h b/include/lib/bakery_lock.h new file mode 100644 index 0000000..6e6e966 --- /dev/null +++ b/include/lib/bakery_lock.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BAKERY_LOCK_H__ +#define __BAKERY_LOCK_H__ + +#include + +#define BAKERY_LOCK_MAX_CPUS PLATFORM_CORE_COUNT + +#ifndef __ASSEMBLY__ +typedef struct { + int owner; + volatile char entering[BAKERY_LOCK_MAX_CPUS]; + volatile unsigned number[BAKERY_LOCK_MAX_CPUS]; +} bakery_lock; + +#define NO_OWNER (-1) + +void bakery_lock_init(bakery_lock *bakery); +void bakery_lock_get(unsigned long mpidr, bakery_lock *bakery); +void bakery_lock_release(unsigned long mpidr, bakery_lock *bakery); +int bakery_lock_try(unsigned long mpidr, bakery_lock *bakery); +#endif /*__ASSEMBLY__*/ + +#endif /* __BAKERY_LOCK_H__ */ diff --git a/include/lib/io_storage.h b/include/lib/io_storage.h new file mode 100644 index 0000000..04e63c3 --- /dev/null +++ b/include/lib/io_storage.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IO_H__ +#define __IO_H__ + +#ifndef __ASSEMBLY__ + +#include +#include /* For ssize_t */ + + +/* Device type which can be used to enable policy decisions about which device + * to access */ +typedef enum { + IO_TYPE_INVALID, + IO_TYPE_SEMIHOSTING, + IO_TYPE_MEMMAP, + IO_TYPE_FIRMWARE_IMAGE_PACKAGE, + IO_TYPE_MAX +} io_type; + + +/* Modes used when seeking data on a supported device */ +typedef enum { + IO_SEEK_INVALID, + IO_SEEK_SET, + IO_SEEK_END, + IO_SEEK_CUR, + IO_SEEK_MAX +} io_seek_mode; + + +/* Connector type, providing a means of identifying a device to open */ +struct io_dev_connector; + +/* Device handle, providing a client with access to a specific device */ +typedef struct io_dev_info *io_dev_handle; + +/* IO handle, providing a client with access to a specific source of data from + * a device */ +typedef struct io_entity *io_handle; + + +/* File specification - used to refer to data on a device supporting file-like + * entities */ +typedef struct { + const char *path; + unsigned int mode; +} io_file_spec; + + +/* Block specification - used to refer to data on a device supporting + * block-like entities */ +typedef struct { + unsigned long offset; + size_t length; +} io_block_spec; + + +/* Access modes used when accessing data on a device */ +#define IO_MODE_INVALID (0) +#define IO_MODE_RO (1 << 0) +#define IO_MODE_RW (1 << 1) + + +/* Return codes reported by 'io_*' APIs */ +#define IO_SUCCESS (0) +#define IO_FAIL (-1) +#define IO_NOT_SUPPORTED (-2) +#define IO_RESOURCES_EXHAUSTED (-3) + + +/* Open a connection to a device */ +int io_dev_open(struct io_dev_connector *dev_con, void *dev_spec, + io_dev_handle *dev_handle); + + +/* Initialise a device explicitly - to permit lazy initialisation or + * re-initialisation */ +int io_dev_init(io_dev_handle dev_handle, const void *init_params); + +/* TODO: Consider whether an explicit "shutdown" API should be included */ + +/* Close a connection to a device */ +int io_dev_close(io_dev_handle dev_handle); + + +/* Synchronous operations */ +int io_open(io_dev_handle dev_handle, const void *spec, io_handle *handle); + +int io_seek(io_handle handle, io_seek_mode mode, ssize_t offset); + +int io_size(io_handle handle, size_t *length); + +int io_read(io_handle handle, void *buffer, size_t length, size_t *length_read); + +int io_write(io_handle handle, const void *buffer, size_t length, + size_t *length_written); + +int io_close(io_handle handle); + + +#endif /* __ASSEMBLY__ */ +#endif /* __IO_H__ */ diff --git a/include/lib/mmio.h b/include/lib/mmio.h new file mode 100644 index 0000000..c79c3f5 --- /dev/null +++ b/include/lib/mmio.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MMIO_H__ +#define __MMIO_H__ + +#ifndef __ASSEMBLY__ + +#include + +extern void mmio_write_8(uintptr_t addr, uint8_t value); +extern uint8_t mmio_read_8(uintptr_t addr); + +extern void mmio_write_32(uintptr_t addr, uint32_t value); +extern uint32_t mmio_read_32(uintptr_t addr); + +extern void mmio_write_64(uintptr_t addr, uint64_t value); +extern uint64_t mmio_read_64(uintptr_t addr); + +#endif /*__ASSEMBLY__*/ + +#endif /* __MMIO_H__ */ diff --git a/include/lib/semihosting.h b/include/lib/semihosting.h new file mode 100644 index 0000000..e688618 --- /dev/null +++ b/include/lib/semihosting.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SEMIHOSTING_H__ +#define __SEMIHOSTING_H__ + +#define SEMIHOSTING_SYS_OPEN 0x01 +#define SEMIHOSTING_SYS_CLOSE 0x02 +#define SEMIHOSTING_SYS_WRITE0 0x04 +#define SEMIHOSTING_SYS_WRITEC 0x03 +#define SEMIHOSTING_SYS_WRITE 0x05 +#define SEMIHOSTING_SYS_READ 0x06 +#define SEMIHOSTING_SYS_READC 0x07 +#define SEMIHOSTING_SYS_SEEK 0x0A +#define SEMIHOSTING_SYS_FLEN 0x0C +#define SEMIHOSTING_SYS_REMOVE 0x0E +#define SEMIHOSTING_SYS_SYSTEM 0x12 +#define SEMIHOSTING_SYS_ERRNO 0x13 + +#define FOPEN_MODE_R 0x0 +#define FOPEN_MODE_RB 0x1 +#define FOPEN_MODE_RPLUS 0x2 +#define FOPEN_MODE_RPLUSB 0x3 +#define FOPEN_MODE_W 0x4 +#define FOPEN_MODE_WB 0x5 +#define FOPEN_MODE_WPLUS 0x6 +#define FOPEN_MODE_WPLUSB 0x7 +#define FOPEN_MODE_A 0x8 +#define FOPEN_MODE_AB 0x9 +#define FOPEN_MODE_APLUS 0xa +#define FOPEN_MODE_APLUSB 0xb + +long semihosting_connection_supported(void); +long semihosting_file_open(const char *file_name, size_t mode); +long semihosting_file_seek(long file_handle, ssize_t offset); +long semihosting_file_read(long file_handle, size_t *length, void *buffer); +long semihosting_file_write(long file_handle, + size_t *length, + const void *buffer); +long semihosting_file_close(long file_handle); +long semihosting_file_length(long file_handle); +long semihosting_system(char *command_line); +long semihosting_get_flen(const char *file_name); +long semihosting_download_file(const char *file_name, + size_t buf_size, + void *buf); +void semihosting_write_char(char character); +void semihosting_write_string(char *string); +char semihosting_read_char(void); + +#endif /* __SEMIHOSTING_H__ */ diff --git a/include/lib/spinlock.h b/include/lib/spinlock.h new file mode 100644 index 0000000..94aaa1a --- /dev/null +++ b/include/lib/spinlock.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SPINLOCK_H__ +#define __SPINLOCK_H__ + +typedef struct { + volatile unsigned int lock; +} spinlock_t; + +void spin_lock(spinlock_t *lock); +void spin_unlock(spinlock_t *lock); + +#endif /* __SPINLOCK_H__ */ diff --git a/include/mmio.h b/include/mmio.h deleted file mode 100644 index c79c3f5..0000000 --- a/include/mmio.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __MMIO_H__ -#define __MMIO_H__ - -#ifndef __ASSEMBLY__ - -#include - -extern void mmio_write_8(uintptr_t addr, uint8_t value); -extern uint8_t mmio_read_8(uintptr_t addr); - -extern void mmio_write_32(uintptr_t addr, uint32_t value); -extern uint32_t mmio_read_32(uintptr_t addr); - -extern void mmio_write_64(uintptr_t addr, uint64_t value); -extern uint64_t mmio_read_64(uintptr_t addr); - -#endif /*__ASSEMBLY__*/ - -#endif /* __MMIO_H__ */ diff --git a/include/pm.h b/include/pm.h deleted file mode 100644 index bfdbf67..0000000 --- a/include/pm.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __PM_H__ -#define __PM_H__ - -#ifndef __ASSEMBLY__ - -/******************************************************************************* - * Structure populated by platform specific code to export routines which - * perform common low level pm functions - ******************************************************************************/ -typedef struct { - int (*cpu_on)(unsigned long); - int (*cpu_off)(unsigned long); - int (*cpu_suspend)(unsigned long); - int (*affinity_info)(unsigned long, unsigned int); -} pm_frontend_ops; - -/******************************************************************************* - * Structure populated by a generic power management api implementation e.g. - * psci to perform api specific bits after a cpu has been turned on. - ******************************************************************************/ -typedef struct { - unsigned long (*cpu_off_finisher)(unsigned long); - unsigned long (*cpu_suspend_finisher)(unsigned long); -} pm_backend_ops; - -/******************************************************************************* - * Function & variable prototypes - ******************************************************************************/ -extern pm_frontend_ops *get_pm_frontend_ops(void); -extern pm_backend_ops *get_pm_backend_ops(void); -extern void set_pm_frontend_ops(pm_frontend_ops *); -extern void set_pm_backend_ops(pm_backend_ops *); - -#endif /*__ASSEMBLY__*/ - -#endif /* __PM_H__ */ diff --git a/include/psci.h b/include/psci.h deleted file mode 100644 index e290793..0000000 --- a/include/psci.h +++ /dev/null @@ -1,197 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __PSCI_H__ -#define __PSCI_H__ - -/******************************************************************************* - * Defines for runtime services func ids - ******************************************************************************/ -#define PSCI_VERSION 0x84000000 -#define PSCI_CPU_SUSPEND_AARCH32 0x84000001 -#define PSCI_CPU_SUSPEND_AARCH64 0xc4000001 -#define PSCI_CPU_OFF 0x84000002 -#define PSCI_CPU_ON_AARCH32 0x84000003 -#define PSCI_CPU_ON_AARCH64 0xc4000003 -#define PSCI_AFFINITY_INFO_AARCH32 0x84000004 -#define PSCI_AFFINITY_INFO_AARCH64 0xc4000004 -#define PSCI_MIG_AARCH32 0x84000005 -#define PSCI_MIG_AARCH64 0xc4000005 -#define PSCI_MIG_INFO_TYPE 0x84000006 -#define PSCI_MIG_INFO_UP_CPU_AARCH32 0x84000007 -#define PSCI_MIG_INFO_UP_CPU_AARCH64 0xc4000007 -#define PSCI_SYSTEM_OFF 0x84000008 -#define PSCI_SYSTEM_RESET 0x84000009 - -/* - * Number of PSCI calls (above) implemented. System off and reset aren't - * implemented as yet - */ -#define PSCI_NUM_CALLS 13 - -/******************************************************************************* - * PSCI Migrate and friends - ******************************************************************************/ -#define PSCI_TOS_UP_MIG_CAP 0 -#define PSCI_TOS_NOT_UP_MIG_CAP 1 -#define PSCI_TOS_NOT_PRESENT_MP 2 - -/******************************************************************************* - * PSCI CPU_SUSPEND 'power_state' parameter specific defines - ******************************************************************************/ -#define PSTATE_ID_SHIFT 0 -#define PSTATE_TYPE_SHIFT 16 -#define PSTATE_AFF_LVL_SHIFT 24 - -#define PSTATE_ID_MASK 0xffff -#define PSTATE_TYPE_MASK 0x1 -#define PSTATE_AFF_LVL_MASK 0x3 -#define PSTATE_VALID_MASK 0xFCFE0000 - -#define PSTATE_TYPE_STANDBY 0x0 -#define PSTATE_TYPE_POWERDOWN 0x1 - -#define psci_get_pstate_id(pstate) (pstate >> PSTATE_ID_SHIFT) & \ - PSTATE_ID_MASK -#define psci_get_pstate_type(pstate) (pstate >> PSTATE_TYPE_SHIFT) & \ - PSTATE_TYPE_MASK -#define psci_get_pstate_afflvl(pstate) (pstate >> PSTATE_AFF_LVL_SHIFT) & \ - PSTATE_AFF_LVL_MASK - -/******************************************************************************* - * PSCI version - ******************************************************************************/ -#define PSCI_MAJOR_VER (0 << 16) -#define PSCI_MINOR_VER 0x2 - -/******************************************************************************* - * PSCI error codes - ******************************************************************************/ -#define PSCI_E_SUCCESS 0 -#define PSCI_E_NOT_SUPPORTED -1 -#define PSCI_E_INVALID_PARAMS -2 -#define PSCI_E_DENIED -3 -#define PSCI_E_ALREADY_ON -4 -#define PSCI_E_ON_PENDING -5 -#define PSCI_E_INTERN_FAIL -6 -#define PSCI_E_NOT_PRESENT -7 -#define PSCI_E_DISABLED -8 - -/******************************************************************************* - * PSCI affinity state related constants. An affinity instance could be present - * or absent physically to cater for asymmetric topologies. If present then it - * could in one of the 4 further defined states. - ******************************************************************************/ -#define PSCI_STATE_SHIFT 1 -#define PSCI_STATE_MASK 0xff - -#define PSCI_AFF_ABSENT 0x0 -#define PSCI_AFF_PRESENT 0x1 -#define PSCI_STATE_ON 0x0 -#define PSCI_STATE_OFF 0x1 -#define PSCI_STATE_ON_PENDING 0x2 -#define PSCI_STATE_SUSPEND 0x3 - -#define PSCI_INVALID_DATA -1 - -#define get_phys_state(x) (x != PSCI_STATE_ON ? \ - PSCI_STATE_OFF : PSCI_STATE_ON) - -#define psci_validate_power_state(pstate) (pstate & PSTATE_VALID_MASK) - - -/* Number of affinity instances whose state this psci imp. can track */ -#define PSCI_NUM_AFFS 32ull - -#ifndef __ASSEMBLY__ -/******************************************************************************* - * Structure populated by platform specific code to export routines which - * perform common low level pm functions - ******************************************************************************/ -typedef struct { - int (*affinst_standby)(unsigned int); - int (*affinst_on)(unsigned long, - unsigned long, - unsigned long, - unsigned int, - unsigned int); - int (*affinst_off)(unsigned long, unsigned int, unsigned int); - int (*affinst_suspend)(unsigned long, - unsigned long, - unsigned long, - unsigned int, - unsigned int); - int (*affinst_on_finish)(unsigned long, unsigned int, unsigned int); - int (*affinst_suspend_finish)(unsigned long, - unsigned int, - unsigned int); -} plat_pm_ops; - -/******************************************************************************* - * Optional structure populated by the Secure Payload Dispatcher to be given a - * chance to perform any bookkeeping before PSCI executes a power mgmt. - * operation. It also allows PSCI to determine certain properties of the SP e.g. - * migrate capability etc. - ******************************************************************************/ -typedef struct { - void (*svc_on)(uint64_t target_cpu); - int32_t (*svc_off)(uint64_t __unused); - void (*svc_suspend)(uint64_t power_state); - void (*svc_on_finish)(uint64_t __unused); - void (*svc_suspend_finish)(uint64_t suspend_level); - void (*svc_migrate)(uint64_t __unused1, uint64_t __unused2); - int32_t (*svc_migrate_info)(uint64_t *__unused); -} spd_pm_ops; - -/******************************************************************************* - * Function & Data prototypes - ******************************************************************************/ -extern unsigned int psci_version(void); -extern int __psci_cpu_suspend(unsigned int, unsigned long, unsigned long); -extern int __psci_cpu_off(void); -extern int psci_affinity_info(unsigned long, unsigned int); -extern int psci_migrate(unsigned int); -extern unsigned int psci_migrate_info_type(void); -extern unsigned long psci_migrate_info_up_cpu(void); -extern void psci_system_off(void); -extern void psci_system_reset(void); -extern int psci_cpu_on(unsigned long, - unsigned long, - unsigned long); -extern void psci_aff_on_finish_entry(void); -extern void psci_aff_suspend_finish_entry(void); -extern void psci_register_spd_pm_hook(const spd_pm_ops *); -extern int psci_get_suspend_stateid(unsigned long mpidr); -extern int psci_get_suspend_afflvl(unsigned long mpidr); - -#endif /*__ASSEMBLY__*/ - - -#endif /* __PSCI_H__ */ diff --git a/include/runtime_svc.h b/include/runtime_svc.h deleted file mode 100644 index 148c0bc..0000000 --- a/include/runtime_svc.h +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __RUNTIME_SVC_H__ -#define __RUNTIME_SVC_H__ -#include -#include - -/******************************************************************************* - * Bit definitions inside the function id as per the SMC calling convention - ******************************************************************************/ -#define FUNCID_TYPE_SHIFT 31 -#define FUNCID_CC_SHIFT 30 -#define FUNCID_OEN_SHIFT 24 -#define FUNCID_NUM_SHIFT 0 - -#define FUNCID_TYPE_MASK 0x1 -#define FUNCID_CC_MASK 0x1 -#define FUNCID_OEN_MASK 0x3f -#define FUNCID_NUM_MASK 0xffff - -#define FUNCID_TYPE_WIDTH 1 -#define FUNCID_CC_WIDTH 1 -#define FUNCID_OEN_WIDTH 6 -#define FUNCID_NUM_WIDTH 16 - -#define GET_SMC_CC(id) ((id >> FUNCID_CC_SHIFT) & \ - FUNCID_CC_MASK) - -#define SMC_64 1 -#define SMC_32 0 -#define SMC_UNK 0xffffffff -#define SMC_TYPE_FAST 1 -#define SMC_TYPE_STD 0 - -/******************************************************************************* - * Owning entity number definitions inside the function id as per the SMC - * calling convention - ******************************************************************************/ -#define OEN_ARM_START 0 -#define OEN_ARM_END 0 -#define OEN_CPU_START 1 -#define OEN_CPU_END 1 -#define OEN_SIP_START 2 -#define OEN_SIP_END 2 -#define OEN_OEM_START 3 -#define OEN_OEM_END 3 -#define OEN_STD_START 4 /* Standard Calls */ -#define OEN_STD_END 4 -#define OEN_TAP_START 48 /* Trusted Applications */ -#define OEN_TAP_END 49 -#define OEN_TOS_START 50 /* Trusted OS */ -#define OEN_TOS_END 63 -#define OEN_LIMIT 64 - -/******************************************************************************* - * Constants to indicate type of exception to the common exception handler. - ******************************************************************************/ -#define SYNC_EXCEPTION_SP_EL0 0x0 -#define IRQ_SP_EL0 0x1 -#define FIQ_SP_EL0 0x2 -#define SERROR_SP_EL0 0x3 -#define SYNC_EXCEPTION_SP_ELX 0x4 -#define IRQ_SP_ELX 0x5 -#define FIQ_SP_ELX 0x6 -#define SERROR_SP_ELX 0x7 -#define SYNC_EXCEPTION_AARCH64 0x8 -#define IRQ_AARCH64 0x9 -#define FIQ_AARCH64 0xa -#define SERROR_AARCH64 0xb -#define SYNC_EXCEPTION_AARCH32 0xc -#define IRQ_AARCH32 0xd -#define FIQ_AARCH32 0xe -#define SERROR_AARCH32 0xf - -/******************************************************************************* - * Structure definition, typedefs & constants for the runtime service framework - ******************************************************************************/ - -/* - * Constants to allow the assembler access a runtime service - * descriptor - */ -#define RT_SVC_SIZE_LOG2 5 -#define SIZEOF_RT_SVC_DESC (1 << RT_SVC_SIZE_LOG2) -#define RT_SVC_DESC_INIT 16 -#define RT_SVC_DESC_HANDLE 24 - -/* - * The function identifier has 6 bits for the owning entity number and - * single bit for the type of smc call. When taken together these - * values limit the maximum number of runtime services to 128. - */ -#define MAX_RT_SVCS 128 - -#ifndef __ASSEMBLY__ - -/* Various flags passed to SMC handlers */ -#define SMC_FROM_SECURE (0 << 0) -#define SMC_FROM_NON_SECURE (1 << 0) - -#define is_caller_non_secure(_f) (!!(_f & SMC_FROM_NON_SECURE)) -#define is_caller_secure(_f) (!(is_caller_non_secure(_f))) - -/* Prototype for runtime service initializing function */ -typedef int32_t (*rt_svc_init)(void); - -/* Convenience macros to return from SMC handler */ -#define SMC_RET1(_h, _x0) { \ - write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X0, (_x0)); \ - return _x0; \ -} -#define SMC_RET2(_h, _x0, _x1) { \ - write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X1, (_x1)); \ - SMC_RET1(_h, (_x0)); \ -} -#define SMC_RET3(_h, _x0, _x1, _x2) { \ - write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X2, (_x2)); \ - SMC_RET2(_h, (_x0), (_x1)); \ -} -#define SMC_RET4(_h, _x0, _x1, _x2, _x3) { \ - write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X3, (_x3)); \ - SMC_RET3(_h, (_x0), (_x1), (_x2)); \ -} - - -/* - * Convenience macros to access general purpose registers using handle provided - * to SMC handler. These takes the offset values defined in context.h - */ -#define SMC_GET_GP(_h, _g) \ - read_ctx_reg(get_gpregs_ctx(_h), (_g)); -#define SMC_SET_GP(_h, _g, _v) \ - write_ctx_reg(get_gpregs_ctx(_h), (_g), (_v)); - -/* - * Convenience macros to access EL3 context registers using handle provided to - * SMC handler. These takes the offset values defined in context.h - */ -#define SMC_GET_EL3(_h, _e) \ - read_ctx_reg(get_el3state_ctx(_h), (_e)); -#define SMC_SET_EL3(_h, _e, _v) \ - write_ctx_reg(get_el3state_ctx(_h), (_e), (_v)); - -/* - * Prototype for runtime service SMC handler function. x0 (SMC Function ID) to - * x4 are as passed by the caller. Rest of the arguments to SMC and the context - * can be accessed using the handle pointer. The cookie parameter is reserved - * for future use - */ -typedef uint64_t (*rt_svc_handle)(uint32_t smc_fid, - uint64_t x1, - uint64_t x2, - uint64_t x3, - uint64_t x4, - void *cookie, - void *handle, - uint64_t flags); -typedef struct { - uint8_t start_oen; - uint8_t end_oen; - uint8_t call_type; - const char *name; - rt_svc_init init; - rt_svc_handle handle; -} rt_svc_desc; - -/* - * Convenience macro to declare a service descriptor - */ -#define DECLARE_RT_SVC(_name, _start, _end, _type, _setup, _smch) \ - static const rt_svc_desc __svc_desc_ ## _name \ - __attribute__ ((section("rt_svc_descs"), used)) = { \ - _start, \ - _end, \ - _type, \ - #_name, \ - _setup, \ - _smch } - -/* - * Compile time assertions related to the 'rt_svc_desc' structure to: - * 1. ensure that the assembler and the compiler view of the size - * of the structure are the same. - * 2. ensure that the assembler and the compiler see the initialisation - * routine at the same offset. - * 3. ensure that the assembler and the compiler see the handler - * routine at the same offset. - */ -CASSERT((sizeof(rt_svc_desc) == SIZEOF_RT_SVC_DESC), \ - assert_sizeof_rt_svc_desc_mismatch); -CASSERT(RT_SVC_DESC_INIT == __builtin_offsetof(rt_svc_desc, init), \ - assert_rt_svc_desc_init_offset_mismatch); -CASSERT(RT_SVC_DESC_HANDLE == __builtin_offsetof(rt_svc_desc, handle), \ - assert_rt_svc_desc_handle_offset_mismatch); - - -/* - * This macro combines the call type and the owning entity number corresponding - * to a runtime service to generate a unique owning entity number. This unique - * oen is used to access an entry in the 'rt_svc_descs_indices' array. The entry - * contains the index of the service descriptor in the 'rt_svc_descs' array. - */ -#define get_unique_oen(oen, call_type) ((oen & FUNCID_OEN_MASK) | \ - ((call_type & FUNCID_TYPE_MASK) \ - << FUNCID_OEN_WIDTH)) - - -/* - * Macro to define UUID for services. Apart from defining and initializing a - * uuid_t structure, this macro verifies that the first word of the defined UUID - * does not equal SMC_UNK. This is to ensure that the caller won't mistake the - * returned UUID in x0 for an invalid SMC error return - */ -#define DEFINE_SVC_UUID(_name, _tl, _tm, _th, _cl, _ch, \ - _n0, _n1, _n2, _n3, _n4, _n5) \ - CASSERT(_tl != SMC_UNK, invalid_svc_uuid);\ - static const uuid_t _name = { \ - _tl, _tm, _th, _cl, _ch, \ - { _n0, _n1, _n2, _n3, _n4, _n5 } \ - } - -/* Return a UUID in the SMC return registers */ -#define SMC_UUID_RET(_h, _uuid) \ - SMC_RET4(handle, ((const uint32_t *) &(_uuid))[0], \ - ((const uint32_t *) &(_uuid))[1], \ - ((const uint32_t *) &(_uuid))[2], \ - ((const uint32_t *) &(_uuid))[3]) - -/******************************************************************************* - * Function & variable prototypes - ******************************************************************************/ -extern void runtime_svc_init(); -extern uint64_t __RT_SVC_DESCS_START__; -extern uint64_t __RT_SVC_DESCS_END__; -extern uint64_t get_exception_stack(uint64_t mpidr); -extern void fault_handler(void *handle); -#endif /*__ASSEMBLY__*/ -#endif /* __RUNTIME_SVC_H__ */ diff --git a/include/semihosting.h b/include/semihosting.h deleted file mode 100644 index e688618..0000000 --- a/include/semihosting.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __SEMIHOSTING_H__ -#define __SEMIHOSTING_H__ - -#define SEMIHOSTING_SYS_OPEN 0x01 -#define SEMIHOSTING_SYS_CLOSE 0x02 -#define SEMIHOSTING_SYS_WRITE0 0x04 -#define SEMIHOSTING_SYS_WRITEC 0x03 -#define SEMIHOSTING_SYS_WRITE 0x05 -#define SEMIHOSTING_SYS_READ 0x06 -#define SEMIHOSTING_SYS_READC 0x07 -#define SEMIHOSTING_SYS_SEEK 0x0A -#define SEMIHOSTING_SYS_FLEN 0x0C -#define SEMIHOSTING_SYS_REMOVE 0x0E -#define SEMIHOSTING_SYS_SYSTEM 0x12 -#define SEMIHOSTING_SYS_ERRNO 0x13 - -#define FOPEN_MODE_R 0x0 -#define FOPEN_MODE_RB 0x1 -#define FOPEN_MODE_RPLUS 0x2 -#define FOPEN_MODE_RPLUSB 0x3 -#define FOPEN_MODE_W 0x4 -#define FOPEN_MODE_WB 0x5 -#define FOPEN_MODE_WPLUS 0x6 -#define FOPEN_MODE_WPLUSB 0x7 -#define FOPEN_MODE_A 0x8 -#define FOPEN_MODE_AB 0x9 -#define FOPEN_MODE_APLUS 0xa -#define FOPEN_MODE_APLUSB 0xb - -long semihosting_connection_supported(void); -long semihosting_file_open(const char *file_name, size_t mode); -long semihosting_file_seek(long file_handle, ssize_t offset); -long semihosting_file_read(long file_handle, size_t *length, void *buffer); -long semihosting_file_write(long file_handle, - size_t *length, - const void *buffer); -long semihosting_file_close(long file_handle); -long semihosting_file_length(long file_handle); -long semihosting_system(char *command_line); -long semihosting_get_flen(const char *file_name); -long semihosting_download_file(const char *file_name, - size_t buf_size, - void *buf); -void semihosting_write_char(char character); -void semihosting_write_string(char *string); -char semihosting_read_char(void); - -#endif /* __SEMIHOSTING_H__ */ diff --git a/include/spinlock.h b/include/spinlock.h deleted file mode 100644 index 94aaa1a..0000000 --- a/include/spinlock.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __SPINLOCK_H__ -#define __SPINLOCK_H__ - -typedef struct { - volatile unsigned int lock; -} spinlock_t; - -void spin_lock(spinlock_t *lock); -void spin_unlock(spinlock_t *lock); - -#endif /* __SPINLOCK_H__ */ diff --git a/include/std_svc.h b/include/std_svc.h deleted file mode 100644 index cbd5b62..0000000 --- a/include/std_svc.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __STD_SVC_H__ -#define __STD_SVC_H__ - -/* SMC function IDs for Standard Service queries */ - -#define ARM_STD_SVC_CALL_COUNT 0x8400ff00 -#define ARM_STD_SVC_UID 0x8400ff01 -/* 0x8400ff02 is reserved */ -#define ARM_STD_SVC_VERSION 0x8400ff03 - -/* ARM Standard Service Calls version numbers */ -#define STD_SVC_VERSION_MAJOR 0x0 -#define STD_SVC_VERSION_MINOR 0x1 - -/* The macros below are used to identify PSCI calls from the SMC function ID */ -#define PSCI_FID_MASK 0xffe0u -#define PSCI_FID_VALUE 0u -#define is_psci_fid(_fid) \ - (((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE) - -#endif /* __STD_SVC_H__ */ diff --git a/include/tsp.h b/include/tsp.h deleted file mode 100644 index 9d747d7..0000000 --- a/include/tsp.h +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __TSP_H__ -#define __TSP_H__ - -#include -#include - -/* - * SMC function IDs that TSP uses to signal various forms of completions - * to the secure payload dispatcher. - */ -#define TSP_ENTRY_DONE 0xf2000000 -#define TSP_ON_DONE 0xf2000001 -#define TSP_OFF_DONE 0xf2000002 -#define TSP_SUSPEND_DONE 0xf2000003 -#define TSP_RESUME_DONE 0xf2000004 -#define TSP_WORK_DONE 0xf2000005 - -/* SMC function ID that TSP uses to request service from secure montior */ -#define TSP_GET_ARGS 0xf2001000 - -/* Function IDs for various TSP services */ -#define TSP_FID_ADD 0xf2002000 -#define TSP_FID_SUB 0xf2002001 -#define TSP_FID_MUL 0xf2002002 -#define TSP_FID_DIV 0xf2002003 - -/* - * Total number of function IDs implemented for services offered to NS clients. - * The function IDs are defined above - */ -#define TSP_NUM_FID 0x4 - -/* TSP implementation version numbers */ -#define TSP_VERSION_MAJOR 0x0 /* Major version */ -#define TSP_VERSION_MINOR 0x1 /* Minor version */ - -/* - * Standard Trusted OS Function IDs that fall under Trusted OS call range - * according to SMC calling convention - */ -#define TOS_CALL_COUNT 0xbf00ff00 /* Number of calls implemented */ -#define TOS_UID 0xbf00ff01 /* Implementation UID */ -/* 0xbf00ff02 is reserved */ -#define TOS_CALL_VERSION 0xbf00ff03 /* Trusted OS Call Version */ - -/* Definitions to help the assembler access the SMC/ERET args structure */ -#define TSP_ARGS_SIZE 0x40 -#define TSP_ARG0 0x0 -#define TSP_ARG1 0x8 -#define TSP_ARG2 0x10 -#define TSP_ARG3 0x18 -#define TSP_ARG4 0x20 -#define TSP_ARG5 0x28 -#define TSP_ARG6 0x30 -#define TSP_ARG7 0x38 -#define TSP_ARGS_END 0x40 - -#ifndef __ASSEMBLY__ -#include - -typedef void (*tsp_generic_fptr)(uint64_t arg0, - uint64_t arg1, - uint64_t arg2, - uint64_t arg3, - uint64_t arg4, - uint64_t arg5, - uint64_t arg6, - uint64_t arg7); - -typedef struct { - tsp_generic_fptr fast_smc_entry; - tsp_generic_fptr cpu_on_entry; - tsp_generic_fptr cpu_off_entry; - tsp_generic_fptr cpu_resume_entry; - tsp_generic_fptr cpu_suspend_entry; -} entry_info; - -typedef struct { - uint32_t smc_count; /* Number of returns on this cpu */ - uint32_t eret_count; /* Number of entries on this cpu */ - uint32_t cpu_on_count; /* Number of cpu on requests */ - uint32_t cpu_off_count; /* Number of cpu off requests */ - uint32_t cpu_suspend_count; /* Number of cpu suspend requests */ - uint32_t cpu_resume_count; /* Number of cpu resume requests */ -} __aligned(CACHE_WRITEBACK_GRANULE) work_statistics; - -typedef struct { - uint64_t _regs[TSP_ARGS_END >> 3]; -} __aligned(CACHE_WRITEBACK_GRANULE) tsp_args; - -/* Macros to access members of the above structure using their offsets */ -#define read_sp_arg(args, offset) ((args)->_regs[offset >> 3]) -#define write_sp_arg(args, offset, val)(((args)->_regs[offset >> 3]) \ - = val) - -/* - * Ensure that the assembler's view of the size of the tsp_args is the - * same as the compilers - */ -CASSERT(TSP_ARGS_SIZE == sizeof(tsp_args), assert_sp_args_size_mismatch); - -extern void tsp_get_magic(uint64_t args[4]); - -extern void tsp_fast_smc_entry(uint64_t arg0, - uint64_t arg1, - uint64_t arg2, - uint64_t arg3, - uint64_t arg4, - uint64_t arg5, - uint64_t arg6, - uint64_t arg7); -extern void tsp_cpu_resume_entry(uint64_t arg0, - uint64_t arg1, - uint64_t arg2, - uint64_t arg3, - uint64_t arg4, - uint64_t arg5, - uint64_t arg6, - uint64_t arg7); -extern tsp_args *tsp_cpu_resume_main(uint64_t arg0, - uint64_t arg1, - uint64_t arg2, - uint64_t arg3, - uint64_t arg4, - uint64_t arg5, - uint64_t arg6, - uint64_t arg7); -extern void tsp_cpu_suspend_entry(uint64_t arg0, - uint64_t arg1, - uint64_t arg2, - uint64_t arg3, - uint64_t arg4, - uint64_t arg5, - uint64_t arg6, - uint64_t arg7); -extern tsp_args *tsp_cpu_suspend_main(uint64_t arg0, - uint64_t arg1, - uint64_t arg2, - uint64_t arg3, - uint64_t arg4, - uint64_t arg5, - uint64_t arg6, - uint64_t arg7); -extern void tsp_cpu_on_entry(uint64_t arg0, - uint64_t arg1, - uint64_t arg2, - uint64_t arg3, - uint64_t arg4, - uint64_t arg5, - uint64_t arg6, - uint64_t arg7); -extern tsp_args *tsp_cpu_on_main(void); -extern void tsp_cpu_off_entry(uint64_t arg0, - uint64_t arg1, - uint64_t arg2, - uint64_t arg3, - uint64_t arg4, - uint64_t arg5, - uint64_t arg6, - uint64_t arg7); -extern tsp_args *tsp_cpu_off_main(uint64_t arg0, - uint64_t arg1, - uint64_t arg2, - uint64_t arg3, - uint64_t arg4, - uint64_t arg5, - uint64_t arg6, - uint64_t arg7); -#endif /* __ASSEMBLY__ */ - -#endif /* __BL2_H__ */ diff --git a/lib/aarch64/cache_helpers.S b/lib/aarch64/cache_helpers.S new file mode 100644 index 0000000..2696d90 --- /dev/null +++ b/lib/aarch64/cache_helpers.S @@ -0,0 +1,231 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + + .globl dcisw + .globl dccisw + .globl dccsw + .globl dccvac + .globl dcivac + .globl dccivac + .globl dccvau + .globl dczva + .globl flush_dcache_range + .globl inv_dcache_range + .globl dcsw_op_louis + .globl dcsw_op_all + +func dcisw + dc isw, x0 + dsb sy + isb + ret + + +func dccisw + dc cisw, x0 + dsb sy + isb + ret + + +func dccsw + dc csw, x0 + dsb sy + isb + ret + + +func dccvac + dc cvac, x0 + dsb sy + isb + ret + + +func dcivac + dc ivac, x0 + dsb sy + isb + ret + + +func dccivac + dc civac, x0 + dsb sy + isb + ret + + +func dccvau + dc cvau, x0 + dsb sy + isb + ret + + +func dczva + dc zva, x0 + dsb sy + isb + ret + + + /* ------------------------------------------ + * Clean+Invalidate from base address till + * size. 'x0' = addr, 'x1' = size + * ------------------------------------------ + */ +func flush_dcache_range + dcache_line_size x2, x3 + add x1, x0, x1 + sub x3, x2, #1 + bic x0, x0, x3 +flush_loop: + dc civac, x0 + add x0, x0, x2 + cmp x0, x1 + b.lo flush_loop + dsb sy + ret + + + /* ------------------------------------------ + * Invalidate from base address till + * size. 'x0' = addr, 'x1' = size + * ------------------------------------------ + */ +func inv_dcache_range + dcache_line_size x2, x3 + add x1, x0, x1 + sub x3, x2, #1 + bic x0, x0, x3 +inv_loop: + dc ivac, x0 + add x0, x0, x2 + cmp x0, x1 + b.lo inv_loop + dsb sy + ret + + + /* ------------------------------------------ + * Data cache operations by set/way to the + * level specified + * ------------------------------------------ + * ---------------------------------- + * Call this func with the clidr in + * x0, starting cache level in x10, + * last cache level in x3 & cm op in + * x14 + * ---------------------------------- + */ +func dcsw_op +all_start_at_level: + add x2, x10, x10, lsr #1 // work out 3x current cache level + lsr x1, x0, x2 // extract cache type bits from clidr + and x1, x1, #7 // mask of the bits for current cache only + cmp x1, #2 // see what cache we have at this level + b.lt skip // skip if no cache, or just i-cache + msr csselr_el1, x10 // select current cache level in csselr + isb // isb to sych the new cssr&csidr + mrs x1, ccsidr_el1 // read the new ccsidr + and x2, x1, #7 // extract the length of the cache lines + add x2, x2, #4 // add 4 (line length offset) + mov x4, #0x3ff + and x4, x4, x1, lsr #3 // find maximum number on the way size + clz w5, w4 // find bit position of way size increment + mov x7, #0x7fff + and x7, x7, x1, lsr #13 // extract max number of the index size +loop2: + mov x9, x4 // create working copy of max way size +loop3: + lsl x6, x9, x5 + orr x11, x10, x6 // factor way and cache number into x11 + lsl x6, x7, x2 + orr x11, x11, x6 // factor index number into x11 + mov x12, x0 + mov x13, x30 // lr + mov x0, x11 + blr x14 + mov x0, x12 + mov x30, x13 // lr + subs x9, x9, #1 // decrement the way + b.ge loop3 + subs x7, x7, #1 // decrement the index + b.ge loop2 +skip: + add x10, x10, #2 // increment cache number + cmp x3, x10 + b.gt all_start_at_level +finished: + mov x10, #0 // swith back to cache level 0 + msr csselr_el1, x10 // select current cache level in csselr + dsb sy + isb + ret + + +func do_dcsw_op + cbz x3, exit + cmp x0, #DCISW + b.eq dc_isw + cmp x0, #DCCISW + b.eq dc_cisw + cmp x0, #DCCSW + b.eq dc_csw +dc_isw: + mov x0, x9 + adr x14, dcisw + b dcsw_op +dc_cisw: + mov x0, x9 + adr x14, dccisw + b dcsw_op +dc_csw: + mov x0, x9 + adr x14, dccsw + b dcsw_op +exit: + ret + + +func dcsw_op_louis + dsb sy + setup_dcsw_op_args x10, x3, x9, #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT + b do_dcsw_op + + +func dcsw_op_all + dsb sy + setup_dcsw_op_args x10, x3, x9, #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT + b do_dcsw_op diff --git a/lib/aarch64/cpu_helpers.S b/lib/aarch64/cpu_helpers.S new file mode 100644 index 0000000..573d0b8 --- /dev/null +++ b/lib/aarch64/cpu_helpers.S @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + + .weak cpu_reset_handler + + +func cpu_reset_handler + mov x19, x30 // lr + + /* --------------------------------------------- + * As a bare minimal enable the SMP bit. + * --------------------------------------------- + */ + bl read_midr + lsr x0, x0, #MIDR_PN_SHIFT + and x0, x0, #MIDR_PN_MASK + cmp x0, #MIDR_PN_A57 + b.eq smp_setup_begin + cmp x0, #MIDR_PN_A53 + b.ne smp_setup_end +smp_setup_begin: + bl read_cpuectlr + orr x0, x0, #CPUECTLR_SMP_BIT + bl write_cpuectlr +smp_setup_end: + ret x19 diff --git a/lib/aarch64/misc_helpers.S b/lib/aarch64/misc_helpers.S new file mode 100644 index 0000000..e3b4ab5 --- /dev/null +++ b/lib/aarch64/misc_helpers.S @@ -0,0 +1,341 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + .globl enable_irq + .globl disable_irq + + .globl enable_fiq + .globl disable_fiq + + .globl enable_serror + .globl disable_serror + + .globl enable_debug_exceptions + .globl disable_debug_exceptions + + .globl read_daif + .globl write_daif + + .globl read_spsr + .globl read_spsr_el1 + .globl read_spsr_el2 + .globl read_spsr_el3 + + .globl write_spsr + .globl write_spsr_el1 + .globl write_spsr_el2 + .globl write_spsr_el3 + + .globl read_elr + .globl read_elr_el1 + .globl read_elr_el2 + .globl read_elr_el3 + + .globl write_elr + .globl write_elr_el1 + .globl write_elr_el2 + .globl write_elr_el3 + + .globl get_afflvl_shift + .globl mpidr_mask_lower_afflvls + .globl dsb + .globl isb + .globl sev + .globl wfe + .globl wfi + .globl eret + .globl smc + + .globl zeromem16 + .globl memcpy16 + + +func get_afflvl_shift + cmp x0, #3 + cinc x0, x0, eq + mov x1, #MPIDR_AFFLVL_SHIFT + lsl x0, x0, x1 + ret + +func mpidr_mask_lower_afflvls + cmp x1, #3 + cinc x1, x1, eq + mov x2, #MPIDR_AFFLVL_SHIFT + lsl x2, x1, x2 + lsr x0, x0, x2 + lsl x0, x0, x2 + ret + + /* ----------------------------------------------------- + * Asynchronous exception manipulation accessors + * ----------------------------------------------------- + */ +func enable_irq + msr daifclr, #DAIF_IRQ_BIT + ret + + +func enable_fiq + msr daifclr, #DAIF_FIQ_BIT + ret + + +func enable_serror + msr daifclr, #DAIF_ABT_BIT + ret + + +func enable_debug_exceptions + msr daifclr, #DAIF_DBG_BIT + ret + + +func disable_irq + msr daifset, #DAIF_IRQ_BIT + ret + + +func disable_fiq + msr daifset, #DAIF_FIQ_BIT + ret + + +func disable_serror + msr daifset, #DAIF_ABT_BIT + ret + + +func disable_debug_exceptions + msr daifset, #DAIF_DBG_BIT + ret + + +func read_daif + mrs x0, daif + ret + + +func write_daif + msr daif, x0 + ret + + +func read_spsr + mrs x0, CurrentEl + cmp x0, #(MODE_EL1 << MODE_EL_SHIFT) + b.eq read_spsr_el1 + cmp x0, #(MODE_EL2 << MODE_EL_SHIFT) + b.eq read_spsr_el2 + cmp x0, #(MODE_EL3 << MODE_EL_SHIFT) + b.eq read_spsr_el3 + + +func read_spsr_el1 + mrs x0, spsr_el1 + ret + + +func read_spsr_el2 + mrs x0, spsr_el2 + ret + + +func read_spsr_el3 + mrs x0, spsr_el3 + ret + + +func write_spsr + mrs x1, CurrentEl + cmp x1, #(MODE_EL1 << MODE_EL_SHIFT) + b.eq write_spsr_el1 + cmp x1, #(MODE_EL2 << MODE_EL_SHIFT) + b.eq write_spsr_el2 + cmp x1, #(MODE_EL3 << MODE_EL_SHIFT) + b.eq write_spsr_el3 + + +func write_spsr_el1 + msr spsr_el1, x0 + isb + ret + + +func write_spsr_el2 + msr spsr_el2, x0 + isb + ret + + +func write_spsr_el3 + msr spsr_el3, x0 + isb + ret + + +func read_elr + mrs x0, CurrentEl + cmp x0, #(MODE_EL1 << MODE_EL_SHIFT) + b.eq read_elr_el1 + cmp x0, #(MODE_EL2 << MODE_EL_SHIFT) + b.eq read_elr_el2 + cmp x0, #(MODE_EL3 << MODE_EL_SHIFT) + b.eq read_elr_el3 + + +func read_elr_el1 + mrs x0, elr_el1 + ret + + +func read_elr_el2 + mrs x0, elr_el2 + ret + + +func read_elr_el3 + mrs x0, elr_el3 + ret + + +func write_elr + mrs x1, CurrentEl + cmp x1, #(MODE_EL1 << MODE_EL_SHIFT) + b.eq write_elr_el1 + cmp x1, #(MODE_EL2 << MODE_EL_SHIFT) + b.eq write_elr_el2 + cmp x1, #(MODE_EL3 << MODE_EL_SHIFT) + b.eq write_elr_el3 + + +func write_elr_el1 + msr elr_el1, x0 + isb + ret + + +func write_elr_el2 + msr elr_el2, x0 + isb + ret + + +func write_elr_el3 + msr elr_el3, x0 + isb + ret + + +func dsb + dsb sy + ret + + +func isb + isb + ret + + +func sev + sev + ret + + +func wfe + wfe + ret + + +func wfi + wfi + ret + + +func eret + eret + + +func smc + smc #0 + +/* ----------------------------------------------------------------------- + * void zeromem16(void *mem, unsigned int length); + * + * Initialise a memory region to 0. + * The memory address must be 16-byte aligned. + * ----------------------------------------------------------------------- + */ +func zeromem16 + add x2, x0, x1 +/* zero 16 bytes at a time */ +z_loop16: + sub x3, x2, x0 + cmp x3, #16 + b.lt z_loop1 + stp xzr, xzr, [x0], #16 + b z_loop16 +/* zero byte per byte */ +z_loop1: + cmp x0, x2 + b.eq z_end + strb wzr, [x0], #1 + b z_loop1 +z_end: ret + + +/* -------------------------------------------------------------------------- + * void memcpy16(void *dest, const void *src, unsigned int length) + * + * Copy length bytes from memory area src to memory area dest. + * The memory areas should not overlap. + * Destination and source addresses must be 16-byte aligned. + * -------------------------------------------------------------------------- + */ +func memcpy16 +/* copy 16 bytes at a time */ +m_loop16: + cmp x2, #16 + b.lt m_loop1 + ldp x3, x4, [x1], #16 + stp x3, x4, [x0], #16 + sub x2, x2, #16 + b m_loop16 +/* copy byte per byte */ +m_loop1: + cbz x2, m_end + ldrb w3, [x1], #1 + strb w3, [x0], #1 + subs x2, x2, #1 + b.ne m_loop1 +m_end: ret diff --git a/lib/aarch64/sysreg_helpers.S b/lib/aarch64/sysreg_helpers.S new file mode 100644 index 0000000..8e816f0 --- /dev/null +++ b/lib/aarch64/sysreg_helpers.S @@ -0,0 +1,833 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + + .globl read_vbar_el1 + .globl read_vbar_el2 + .globl read_vbar_el3 + .globl write_vbar_el1 + .globl write_vbar_el2 + .globl write_vbar_el3 + + .globl read_sctlr_el1 + .globl read_sctlr_el2 + .globl read_sctlr_el3 + .globl write_sctlr_el1 + .globl write_sctlr_el2 + .globl write_sctlr_el3 + + .globl read_actlr_el1 + .globl read_actlr_el2 + .globl read_actlr_el3 + .globl write_actlr_el1 + .globl write_actlr_el2 + .globl write_actlr_el3 + + .globl read_esr_el1 + .globl read_esr_el2 + .globl read_esr_el3 + .globl write_esr_el1 + .globl write_esr_el2 + .globl write_esr_el3 + + .globl read_afsr0_el1 + .globl read_afsr0_el2 + .globl read_afsr0_el3 + .globl write_afsr0_el1 + .globl write_afsr0_el2 + .globl write_afsr0_el3 + + .globl read_afsr1_el1 + .globl read_afsr1_el2 + .globl read_afsr1_el3 + .globl write_afsr1_el1 + .globl write_afsr1_el2 + .globl write_afsr1_el3 + + .globl read_far_el1 + .globl read_far_el2 + .globl read_far_el3 + .globl write_far_el1 + .globl write_far_el2 + .globl write_far_el3 + + .globl read_mair_el1 + .globl read_mair_el2 + .globl read_mair_el3 + .globl write_mair_el1 + .globl write_mair_el2 + .globl write_mair_el3 + + .globl read_amair_el1 + .globl read_amair_el2 + .globl read_amair_el3 + .globl write_amair_el1 + .globl write_amair_el2 + .globl write_amair_el3 + + .globl read_rvbar_el1 + .globl read_rvbar_el2 + .globl read_rvbar_el3 + + .globl read_rmr_el1 + .globl read_rmr_el2 + .globl read_rmr_el3 + .globl write_rmr_el1 + .globl write_rmr_el2 + .globl write_rmr_el3 + + .globl read_tcr_el1 + .globl read_tcr_el2 + .globl read_tcr_el3 + .globl write_tcr_el1 + .globl write_tcr_el2 + .globl write_tcr_el3 + + .globl read_cptr_el2 + .globl read_cptr_el3 + .globl write_cptr_el2 + .globl write_cptr_el3 + + .globl read_ttbr0_el1 + .globl read_ttbr0_el2 + .globl read_ttbr0_el3 + .globl write_ttbr0_el1 + .globl write_ttbr0_el2 + .globl write_ttbr0_el3 + + .globl read_ttbr1_el1 + .globl read_ttbr1_el2 + .globl write_ttbr1 + .globl write_ttbr1_el1 + .globl write_ttbr1_el2 + + .globl read_cpacr + .globl write_cpacr + + .globl read_cntfrq + .globl write_cntfrq + + .globl read_cpuectlr + .globl write_cpuectlr + + .globl read_cnthctl_el2 + .globl write_cnthctl_el2 + + .globl read_cntfrq_el0 + .globl write_cntfrq_el0 + + .globl read_scr + .globl write_scr + + .globl read_hcr + .globl write_hcr + + .globl read_midr + .globl read_mpidr + + .globl read_current_el + .globl read_id_pfr1_el1 + .globl read_id_aa64pfr0_el1 + +#if SUPPORT_VFP + .globl enable_vfp + .globl read_fpexc + .globl write_fpexc +#endif + + +func read_current_el + mrs x0, CurrentEl + ret + + +func read_id_pfr1_el1 + mrs x0, id_pfr1_el1 + ret + + +func read_id_aa64pfr0_el1 + mrs x0, id_aa64pfr0_el1 + ret + + + /* ----------------------------------------------------- + * VBAR accessors + * ----------------------------------------------------- + */ +func read_vbar_el1 + mrs x0, vbar_el1 + ret + + +func read_vbar_el2 + mrs x0, vbar_el2 + ret + + +func read_vbar_el3 + mrs x0, vbar_el3 + ret + + +func write_vbar_el1 + msr vbar_el1, x0 + isb + ret + + +func write_vbar_el2 + msr vbar_el2, x0 + isb + ret + + +func write_vbar_el3 + msr vbar_el3, x0 + isb + ret + + + /* ----------------------------------------------------- + * AFSR0 accessors + * ----------------------------------------------------- + */ +func read_afsr0_el1 + mrs x0, afsr0_el1 + ret + + +func read_afsr0_el2 + mrs x0, afsr0_el2 + ret + + +func read_afsr0_el3 + mrs x0, afsr0_el3 + ret + + +func write_afsr0_el1 + msr afsr0_el1, x0 + isb + ret + + +func write_afsr0_el2 + msr afsr0_el2, x0 + isb + ret + + +func write_afsr0_el3 + msr afsr0_el3, x0 + isb + ret + + + /* ----------------------------------------------------- + * FAR accessors + * ----------------------------------------------------- + */ +func read_far_el1 + mrs x0, far_el1 + ret + + +func read_far_el2 + mrs x0, far_el2 + ret + + +func read_far_el3 + mrs x0, far_el3 + ret + + +func write_far_el1 + msr far_el1, x0 + isb + ret + + +func write_far_el2 + msr far_el2, x0 + isb + ret + + +func write_far_el3 + msr far_el3, x0 + isb + ret + + + /* ----------------------------------------------------- + * MAIR accessors + * ----------------------------------------------------- + */ +func read_mair_el1 + mrs x0, mair_el1 + ret + + +func read_mair_el2 + mrs x0, mair_el2 + ret + + +func read_mair_el3 + mrs x0, mair_el3 + ret + + +func write_mair_el1 + msr mair_el1, x0 + isb + ret + + +func write_mair_el2 + msr mair_el2, x0 + isb + ret + + +func write_mair_el3 + msr mair_el3, x0 + isb + ret + + + /* ----------------------------------------------------- + * AMAIR accessors + * ----------------------------------------------------- + */ +func read_amair_el1 + mrs x0, amair_el1 + ret + + +func read_amair_el2 + mrs x0, amair_el2 + ret + + +func read_amair_el3 + mrs x0, amair_el3 + ret + + +func write_amair_el1 + msr amair_el1, x0 + isb + ret + + +func write_amair_el2 + msr amair_el2, x0 + isb + ret + + +func write_amair_el3 + msr amair_el3, x0 + isb + ret + + + /* ----------------------------------------------------- + * RVBAR accessors + * ----------------------------------------------------- + */ +func read_rvbar_el1 + mrs x0, rvbar_el1 + ret + + +func read_rvbar_el2 + mrs x0, rvbar_el2 + ret + + +func read_rvbar_el3 + mrs x0, rvbar_el3 + ret + + + /* ----------------------------------------------------- + * RMR accessors + * ----------------------------------------------------- + */ +func read_rmr_el1 + mrs x0, rmr_el1 + ret + + +func read_rmr_el2 + mrs x0, rmr_el2 + ret + + +func read_rmr_el3 + mrs x0, rmr_el3 + ret + + +func write_rmr_el1 + msr rmr_el1, x0 + isb + ret + + +func write_rmr_el2 + msr rmr_el2, x0 + isb + ret + + +func write_rmr_el3 + msr rmr_el3, x0 + isb + ret + + + /* ----------------------------------------------------- + * AFSR1 accessors + * ----------------------------------------------------- + */ +func read_afsr1_el1 + mrs x0, afsr1_el1 + ret + + +func read_afsr1_el2 + mrs x0, afsr1_el2 + ret + + +func read_afsr1_el3 + mrs x0, afsr1_el3 + ret + + +func write_afsr1_el1 + msr afsr1_el1, x0 + isb + ret + + +func write_afsr1_el2 + msr afsr1_el2, x0 + isb + ret + + +func write_afsr1_el3 + msr afsr1_el3, x0 + isb + ret + + + /* ----------------------------------------------------- + * SCTLR accessors + * ----------------------------------------------------- + */ +func read_sctlr_el1 + mrs x0, sctlr_el1 + ret + + +func read_sctlr_el2 + mrs x0, sctlr_el2 + ret + + +func read_sctlr_el3 + mrs x0, sctlr_el3 + ret + + +func write_sctlr_el1 + msr sctlr_el1, x0 + dsb sy + isb + ret + + +func write_sctlr_el2 + msr sctlr_el2, x0 + dsb sy + isb + ret + + +func write_sctlr_el3 + msr sctlr_el3, x0 + dsb sy + isb + ret + + + /* ----------------------------------------------------- + * ACTLR accessors + * ----------------------------------------------------- + */ +func read_actlr_el1 + mrs x0, actlr_el1 + ret + + +func read_actlr_el2 + mrs x0, actlr_el2 + ret + + +func read_actlr_el3 + mrs x0, actlr_el3 + ret + + +func write_actlr_el1 + msr actlr_el1, x0 + dsb sy + isb + ret + + +func write_actlr_el2 + msr actlr_el2, x0 + dsb sy + isb + ret + + +func write_actlr_el3 + msr actlr_el3, x0 + dsb sy + isb + ret + + + /* ----------------------------------------------------- + * ESR accessors + * ----------------------------------------------------- + */ +func read_esr_el1 + mrs x0, esr_el1 + ret + + +func read_esr_el2 + mrs x0, esr_el2 + ret + + +func read_esr_el3 + mrs x0, esr_el3 + ret + + +func write_esr_el1 + msr esr_el1, x0 + dsb sy + isb + ret + + +func write_esr_el2 + msr esr_el2, x0 + dsb sy + isb + ret + + +func write_esr_el3 + msr esr_el3, x0 + dsb sy + isb + ret + + + /* ----------------------------------------------------- + * TCR accessors + * ----------------------------------------------------- + */ +func read_tcr_el1 + mrs x0, tcr_el1 + ret + + +func read_tcr_el2 + mrs x0, tcr_el2 + ret + + +func read_tcr_el3 + mrs x0, tcr_el3 + ret + + +func write_tcr_el1 + msr tcr_el1, x0 + dsb sy + isb + ret + + +func write_tcr_el2 + msr tcr_el2, x0 + dsb sy + isb + ret + + +func write_tcr_el3 + msr tcr_el3, x0 + dsb sy + isb + ret + + + /* ----------------------------------------------------- + * CPTR accessors + * ----------------------------------------------------- + */ +func read_cptr_el1 + b read_cptr_el1 + ret + + +func read_cptr_el2 + mrs x0, cptr_el2 + ret + + +func read_cptr_el3 + mrs x0, cptr_el3 + ret + + +func write_cptr_el1 + b write_cptr_el1 + + +func write_cptr_el2 + msr cptr_el2, x0 + dsb sy + isb + ret + + +func write_cptr_el3 + msr cptr_el3, x0 + dsb sy + isb + ret + + + /* ----------------------------------------------------- + * TTBR0 accessors + * ----------------------------------------------------- + */ +func read_ttbr0_el1 + mrs x0, ttbr0_el1 + ret + + +func read_ttbr0_el2 + mrs x0, ttbr0_el2 + ret + + +func read_ttbr0_el3 + mrs x0, ttbr0_el3 + ret + + +func write_ttbr0_el1 + msr ttbr0_el1, x0 + isb + ret + + +func write_ttbr0_el2 + msr ttbr0_el2, x0 + isb + ret + + +func write_ttbr0_el3 + msr ttbr0_el3, x0 + isb + ret + + + /* ----------------------------------------------------- + * TTBR1 accessors + * ----------------------------------------------------- + */ +func read_ttbr1_el1 + mrs x0, ttbr1_el1 + ret + + +func read_ttbr1_el2 + b read_ttbr1_el2 + + +func read_ttbr1_el3 + b read_ttbr1_el3 + + +func write_ttbr1_el1 + msr ttbr1_el1, x0 + isb + ret + + +func write_ttbr1_el2 + b write_ttbr1_el2 + + +func write_ttbr1_el3 + b write_ttbr1_el3 + + +func read_hcr + mrs x0, hcr_el2 + ret + + +func write_hcr + msr hcr_el2, x0 + dsb sy + isb + ret + + +func read_cpacr + mrs x0, cpacr_el1 + ret + + +func write_cpacr + msr cpacr_el1, x0 + ret + + +func read_cntfrq_el0 + mrs x0, cntfrq_el0 + ret + + +func write_cntfrq_el0 + msr cntfrq_el0, x0 + ret + + +func read_cpuectlr + mrs x0, CPUECTLR_EL1 + ret + + +func write_cpuectlr + msr CPUECTLR_EL1, x0 + dsb sy + isb + ret + + +func read_cnthctl_el2 + mrs x0, cnthctl_el2 + ret + + +func write_cnthctl_el2 + msr cnthctl_el2, x0 + ret + + +func read_cntfrq + mrs x0, cntfrq_el0 + ret + + +func write_cntfrq + msr cntfrq_el0, x0 + ret + + +func write_scr + msr scr_el3, x0 + dsb sy + isb + ret + + +func read_scr + mrs x0, scr_el3 + ret + + +func read_midr + mrs x0, midr_el1 + ret + + +func read_mpidr + mrs x0, mpidr_el1 + ret + + +#if SUPPORT_VFP +func enable_vfp + mrs x0, cpacr_el1 + orr x0, x0, #CPACR_VFP_BITS + msr cpacr_el1, x0 + mrs x0, cptr_el3 + mov x1, #AARCH64_CPTR_TFP + bic x0, x0, x1 + msr cptr_el3, x0 + ret + + +func read_fpexc + b read_fpexc + ret + + +func write_fpexc + b write_fpexc + ret + +#endif diff --git a/lib/aarch64/tlb_helpers.S b/lib/aarch64/tlb_helpers.S new file mode 100644 index 0000000..4244974 --- /dev/null +++ b/lib/aarch64/tlb_helpers.S @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + + .globl tlbialle1 + .globl tlbialle1is + .globl tlbialle2 + .globl tlbialle2is + .globl tlbialle3 + .globl tlbialle3is + .globl tlbivmalle1 + + +func tlbialle1 + tlbi alle1 + dsb sy + isb + ret + + +func tlbialle1is + tlbi alle1is + dsb sy + isb + ret + + +func tlbialle2 + tlbi alle2 + dsb sy + isb + ret + + +func tlbialle2is + tlbi alle2is + dsb sy + isb + ret + + +func tlbialle3 + tlbi alle3 + dsb sy + isb + ret + + +func tlbialle3is + tlbi alle3is + dsb sy + isb + ret + +func tlbivmalle1 + tlbi vmalle1 + dsb sy + isb + ret diff --git a/lib/aarch64/xlat_helpers.c b/lib/aarch64/xlat_helpers.c new file mode 100644 index 0000000..87d24ec --- /dev/null +++ b/lib/aarch64/xlat_helpers.c @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/******************************************************************************* + * Helper to create a level 1/2 table descriptor which points to a level 2/3 + * table. + ******************************************************************************/ +unsigned long create_table_desc(unsigned long *next_table_ptr) +{ + unsigned long desc = (unsigned long) next_table_ptr; + + /* Clear the last 12 bits */ + desc >>= FOUR_KB_SHIFT; + desc <<= FOUR_KB_SHIFT; + + desc |= TABLE_DESC; + + return desc; +} + +/******************************************************************************* + * Helper to create a level 1/2/3 block descriptor which maps the va to addr + ******************************************************************************/ +unsigned long create_block_desc(unsigned long desc, + unsigned long addr, + unsigned int level) +{ + switch (level) { + case LEVEL1: + desc |= (addr << FIRST_LEVEL_DESC_N) | BLOCK_DESC; + break; + case LEVEL2: + desc |= (addr << SECOND_LEVEL_DESC_N) | BLOCK_DESC; + break; + case LEVEL3: + desc |= (addr << THIRD_LEVEL_DESC_N) | TABLE_DESC; + break; + default: + assert(0); + } + + return desc; +} + +/******************************************************************************* + * Helper to create a level 1/2/3 block descriptor which maps the va to output_ + * addr with Device nGnRE attributes. + ******************************************************************************/ +unsigned long create_device_block(unsigned long output_addr, + unsigned int level, + unsigned int ns) +{ + unsigned long upper_attrs, lower_attrs, desc; + + lower_attrs = LOWER_ATTRS(ACCESS_FLAG | OSH | AP_RW); + lower_attrs |= LOWER_ATTRS(ns | ATTR_DEVICE_INDEX); + upper_attrs = UPPER_ATTRS(XN); + desc = upper_attrs | lower_attrs; + + return create_block_desc(desc, output_addr, level); +} + +/******************************************************************************* + * Helper to create a level 1/2/3 block descriptor which maps the va to output_ + * addr with inner-shareable normal wbwa read-only memory attributes. + ******************************************************************************/ +unsigned long create_romem_block(unsigned long output_addr, + unsigned int level, + unsigned int ns) +{ + unsigned long upper_attrs, lower_attrs, desc; + + lower_attrs = LOWER_ATTRS(ACCESS_FLAG | ISH | AP_RO); + lower_attrs |= LOWER_ATTRS(ns | ATTR_IWBWA_OWBWA_NTR_INDEX); + upper_attrs = UPPER_ATTRS(0ull); + desc = upper_attrs | lower_attrs; + + return create_block_desc(desc, output_addr, level); +} + +/******************************************************************************* + * Helper to create a level 1/2/3 block descriptor which maps the va to output_ + * addr with inner-shareable normal wbwa read-write memory attributes. + ******************************************************************************/ +unsigned long create_rwmem_block(unsigned long output_addr, + unsigned int level, + unsigned int ns) +{ + unsigned long upper_attrs, lower_attrs, desc; + + lower_attrs = LOWER_ATTRS(ACCESS_FLAG | ISH | AP_RW); + lower_attrs |= LOWER_ATTRS(ns | ATTR_IWBWA_OWBWA_NTR_INDEX); + upper_attrs = UPPER_ATTRS(XN); + desc = upper_attrs | lower_attrs; + + return create_block_desc(desc, output_addr, level); +} diff --git a/lib/aarch64/xlat_tables.c b/lib/aarch64/xlat_tables.c new file mode 100644 index 0000000..33a8b6d --- /dev/null +++ b/lib/aarch64/xlat_tables.c @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + +#ifndef DEBUG_XLAT_TABLE +#define DEBUG_XLAT_TABLE 0 +#endif + +#if DEBUG_XLAT_TABLE +#define debug_print(...) printf(__VA_ARGS__) +#else +#define debug_print(...) ((void)0) +#endif + + +#define UNSET_DESC ~0ul + +#define NUM_L1_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT) + +uint64_t l1_xlation_table[NUM_L1_ENTRIES] +__aligned(NUM_L1_ENTRIES * sizeof(uint64_t)); + +static uint64_t xlat_tables[MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES] +__aligned(XLAT_TABLE_SIZE) __attribute__((section("xlat_table"))); + +static unsigned next_xlat; + +/* + * Array of all memory regions stored in order of ascending base address. + * The list is terminated by the first entry with size == 0. + */ +static mmap_region mmap[MAX_MMAP_REGIONS + 1]; + + +static void print_mmap(void) +{ +#if DEBUG_XLAT_TABLE + debug_print("mmap:\n"); + mmap_region *mm = mmap; + while (mm->size) { + debug_print(" %010lx %10lx %x\n", mm->base, mm->size, mm->attr); + ++mm; + }; + debug_print("\n"); +#endif +} + +void mmap_add_region(unsigned long base, unsigned long size, unsigned attr) +{ + mmap_region *mm = mmap; + mmap_region *mm_last = mm + sizeof(mmap) / sizeof(mmap[0]) - 1; + + assert(IS_PAGE_ALIGNED(base)); + assert(IS_PAGE_ALIGNED(size)); + + if (!size) + return; + + /* Find correct place in mmap to insert new region */ + while (mm->base < base && mm->size) + ++mm; + + /* Make room for new region by moving other regions up by one place */ + memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm); + + /* Check we haven't lost the empty sentinal from the end of the array */ + assert(mm_last->size == 0); + + mm->base = base; + mm->size = size; + mm->attr = attr; +} + +void mmap_add(const mmap_region *mm) +{ + while (mm->size) { + mmap_add_region(mm->base, mm->size, mm->attr); + ++mm; + } +} + +static unsigned long mmap_desc(unsigned attr, unsigned long addr, + unsigned level) +{ + unsigned long desc = addr; + + desc |= level == 3 ? TABLE_DESC : BLOCK_DESC; + + desc |= attr & MT_NS ? LOWER_ATTRS(NS) : 0; + + desc |= attr & MT_RW ? LOWER_ATTRS(AP_RW) : LOWER_ATTRS(AP_RO); + + desc |= LOWER_ATTRS(ACCESS_FLAG); + + if (attr & MT_MEMORY) { + desc |= LOWER_ATTRS(ATTR_IWBWA_OWBWA_NTR_INDEX | ISH); + if (attr & MT_RW) + desc |= UPPER_ATTRS(XN); + } else { + desc |= LOWER_ATTRS(ATTR_DEVICE_INDEX | OSH); + desc |= UPPER_ATTRS(XN); + } + + debug_print(attr & MT_MEMORY ? "MEM" : "DEV"); + debug_print(attr & MT_RW ? "-RW" : "-RO"); + debug_print(attr & MT_NS ? "-NS" : "-S"); + + return desc; +} + +static int mmap_region_attr(mmap_region *mm, unsigned long base, + unsigned long size) +{ + int attr = mm->attr; + + for (;;) { + ++mm; + + if (!mm->size) + return attr; /* Reached end of list */ + + if (mm->base >= base + size) + return attr; /* Next region is after area so end */ + + if (mm->base + mm->size <= base) + continue; /* Next region has already been overtaken */ + + if ((mm->attr & attr) == attr) + continue; /* Region doesn't override attribs so skip */ + + attr &= mm->attr; + + if (mm->base > base || mm->base + mm->size < base + size) + return -1; /* Region doesn't fully cover our area */ + } +} + +static mmap_region *init_xlation_table(mmap_region *mm, unsigned long base, + unsigned long *table, unsigned level) +{ + unsigned level_size_shift = L1_XLAT_ADDRESS_SHIFT - (level - 1) * + XLAT_TABLE_ENTRIES_SHIFT; + unsigned level_size = 1 << level_size_shift; + unsigned level_index_mask = XLAT_TABLE_ENTRIES_MASK << level_size_shift; + + assert(level <= 3); + + debug_print("New xlat table:\n"); + + do { + unsigned long desc = UNSET_DESC; + + if (mm->base + mm->size <= base) { + /* Area now after the region so skip it */ + ++mm; + continue; + } + + debug_print(" %010lx %8lx " + 6 - 2 * level, base, level_size); + + if (mm->base >= base + level_size) { + /* Next region is after area so nothing to map yet */ + desc = INVALID_DESC; + } else if (mm->base <= base && + mm->base + mm->size >= base + level_size) { + /* Next region covers all of area */ + int attr = mmap_region_attr(mm, base, level_size); + if (attr >= 0) + desc = mmap_desc(attr, base, level); + } + /* else Next region only partially covers area, so need */ + + if (desc == UNSET_DESC) { + /* Area not covered by a region so need finer table */ + unsigned long *new_table = xlat_tables[next_xlat++]; + assert(next_xlat <= MAX_XLAT_TABLES); + desc = TABLE_DESC | (unsigned long)new_table; + + /* Recurse to fill in new table */ + mm = init_xlation_table(mm, base, new_table, level+1); + } + + debug_print("\n"); + + *table++ = desc; + base += level_size; + } while (mm->size && (base & level_index_mask)); + + return mm; +} + +void init_xlat_tables(void) +{ + print_mmap(); + init_xlation_table(mmap, 0, l1_xlation_table, 1); +} diff --git a/lib/arch/aarch64/cache_helpers.S b/lib/arch/aarch64/cache_helpers.S deleted file mode 100644 index 2696d90..0000000 --- a/lib/arch/aarch64/cache_helpers.S +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - - .globl dcisw - .globl dccisw - .globl dccsw - .globl dccvac - .globl dcivac - .globl dccivac - .globl dccvau - .globl dczva - .globl flush_dcache_range - .globl inv_dcache_range - .globl dcsw_op_louis - .globl dcsw_op_all - -func dcisw - dc isw, x0 - dsb sy - isb - ret - - -func dccisw - dc cisw, x0 - dsb sy - isb - ret - - -func dccsw - dc csw, x0 - dsb sy - isb - ret - - -func dccvac - dc cvac, x0 - dsb sy - isb - ret - - -func dcivac - dc ivac, x0 - dsb sy - isb - ret - - -func dccivac - dc civac, x0 - dsb sy - isb - ret - - -func dccvau - dc cvau, x0 - dsb sy - isb - ret - - -func dczva - dc zva, x0 - dsb sy - isb - ret - - - /* ------------------------------------------ - * Clean+Invalidate from base address till - * size. 'x0' = addr, 'x1' = size - * ------------------------------------------ - */ -func flush_dcache_range - dcache_line_size x2, x3 - add x1, x0, x1 - sub x3, x2, #1 - bic x0, x0, x3 -flush_loop: - dc civac, x0 - add x0, x0, x2 - cmp x0, x1 - b.lo flush_loop - dsb sy - ret - - - /* ------------------------------------------ - * Invalidate from base address till - * size. 'x0' = addr, 'x1' = size - * ------------------------------------------ - */ -func inv_dcache_range - dcache_line_size x2, x3 - add x1, x0, x1 - sub x3, x2, #1 - bic x0, x0, x3 -inv_loop: - dc ivac, x0 - add x0, x0, x2 - cmp x0, x1 - b.lo inv_loop - dsb sy - ret - - - /* ------------------------------------------ - * Data cache operations by set/way to the - * level specified - * ------------------------------------------ - * ---------------------------------- - * Call this func with the clidr in - * x0, starting cache level in x10, - * last cache level in x3 & cm op in - * x14 - * ---------------------------------- - */ -func dcsw_op -all_start_at_level: - add x2, x10, x10, lsr #1 // work out 3x current cache level - lsr x1, x0, x2 // extract cache type bits from clidr - and x1, x1, #7 // mask of the bits for current cache only - cmp x1, #2 // see what cache we have at this level - b.lt skip // skip if no cache, or just i-cache - msr csselr_el1, x10 // select current cache level in csselr - isb // isb to sych the new cssr&csidr - mrs x1, ccsidr_el1 // read the new ccsidr - and x2, x1, #7 // extract the length of the cache lines - add x2, x2, #4 // add 4 (line length offset) - mov x4, #0x3ff - and x4, x4, x1, lsr #3 // find maximum number on the way size - clz w5, w4 // find bit position of way size increment - mov x7, #0x7fff - and x7, x7, x1, lsr #13 // extract max number of the index size -loop2: - mov x9, x4 // create working copy of max way size -loop3: - lsl x6, x9, x5 - orr x11, x10, x6 // factor way and cache number into x11 - lsl x6, x7, x2 - orr x11, x11, x6 // factor index number into x11 - mov x12, x0 - mov x13, x30 // lr - mov x0, x11 - blr x14 - mov x0, x12 - mov x30, x13 // lr - subs x9, x9, #1 // decrement the way - b.ge loop3 - subs x7, x7, #1 // decrement the index - b.ge loop2 -skip: - add x10, x10, #2 // increment cache number - cmp x3, x10 - b.gt all_start_at_level -finished: - mov x10, #0 // swith back to cache level 0 - msr csselr_el1, x10 // select current cache level in csselr - dsb sy - isb - ret - - -func do_dcsw_op - cbz x3, exit - cmp x0, #DCISW - b.eq dc_isw - cmp x0, #DCCISW - b.eq dc_cisw - cmp x0, #DCCSW - b.eq dc_csw -dc_isw: - mov x0, x9 - adr x14, dcisw - b dcsw_op -dc_cisw: - mov x0, x9 - adr x14, dccisw - b dcsw_op -dc_csw: - mov x0, x9 - adr x14, dccsw - b dcsw_op -exit: - ret - - -func dcsw_op_louis - dsb sy - setup_dcsw_op_args x10, x3, x9, #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT - b do_dcsw_op - - -func dcsw_op_all - dsb sy - setup_dcsw_op_args x10, x3, x9, #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT - b do_dcsw_op diff --git a/lib/arch/aarch64/misc_helpers.S b/lib/arch/aarch64/misc_helpers.S deleted file mode 100644 index e3b4ab5..0000000 --- a/lib/arch/aarch64/misc_helpers.S +++ /dev/null @@ -1,341 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - - .globl enable_irq - .globl disable_irq - - .globl enable_fiq - .globl disable_fiq - - .globl enable_serror - .globl disable_serror - - .globl enable_debug_exceptions - .globl disable_debug_exceptions - - .globl read_daif - .globl write_daif - - .globl read_spsr - .globl read_spsr_el1 - .globl read_spsr_el2 - .globl read_spsr_el3 - - .globl write_spsr - .globl write_spsr_el1 - .globl write_spsr_el2 - .globl write_spsr_el3 - - .globl read_elr - .globl read_elr_el1 - .globl read_elr_el2 - .globl read_elr_el3 - - .globl write_elr - .globl write_elr_el1 - .globl write_elr_el2 - .globl write_elr_el3 - - .globl get_afflvl_shift - .globl mpidr_mask_lower_afflvls - .globl dsb - .globl isb - .globl sev - .globl wfe - .globl wfi - .globl eret - .globl smc - - .globl zeromem16 - .globl memcpy16 - - -func get_afflvl_shift - cmp x0, #3 - cinc x0, x0, eq - mov x1, #MPIDR_AFFLVL_SHIFT - lsl x0, x0, x1 - ret - -func mpidr_mask_lower_afflvls - cmp x1, #3 - cinc x1, x1, eq - mov x2, #MPIDR_AFFLVL_SHIFT - lsl x2, x1, x2 - lsr x0, x0, x2 - lsl x0, x0, x2 - ret - - /* ----------------------------------------------------- - * Asynchronous exception manipulation accessors - * ----------------------------------------------------- - */ -func enable_irq - msr daifclr, #DAIF_IRQ_BIT - ret - - -func enable_fiq - msr daifclr, #DAIF_FIQ_BIT - ret - - -func enable_serror - msr daifclr, #DAIF_ABT_BIT - ret - - -func enable_debug_exceptions - msr daifclr, #DAIF_DBG_BIT - ret - - -func disable_irq - msr daifset, #DAIF_IRQ_BIT - ret - - -func disable_fiq - msr daifset, #DAIF_FIQ_BIT - ret - - -func disable_serror - msr daifset, #DAIF_ABT_BIT - ret - - -func disable_debug_exceptions - msr daifset, #DAIF_DBG_BIT - ret - - -func read_daif - mrs x0, daif - ret - - -func write_daif - msr daif, x0 - ret - - -func read_spsr - mrs x0, CurrentEl - cmp x0, #(MODE_EL1 << MODE_EL_SHIFT) - b.eq read_spsr_el1 - cmp x0, #(MODE_EL2 << MODE_EL_SHIFT) - b.eq read_spsr_el2 - cmp x0, #(MODE_EL3 << MODE_EL_SHIFT) - b.eq read_spsr_el3 - - -func read_spsr_el1 - mrs x0, spsr_el1 - ret - - -func read_spsr_el2 - mrs x0, spsr_el2 - ret - - -func read_spsr_el3 - mrs x0, spsr_el3 - ret - - -func write_spsr - mrs x1, CurrentEl - cmp x1, #(MODE_EL1 << MODE_EL_SHIFT) - b.eq write_spsr_el1 - cmp x1, #(MODE_EL2 << MODE_EL_SHIFT) - b.eq write_spsr_el2 - cmp x1, #(MODE_EL3 << MODE_EL_SHIFT) - b.eq write_spsr_el3 - - -func write_spsr_el1 - msr spsr_el1, x0 - isb - ret - - -func write_spsr_el2 - msr spsr_el2, x0 - isb - ret - - -func write_spsr_el3 - msr spsr_el3, x0 - isb - ret - - -func read_elr - mrs x0, CurrentEl - cmp x0, #(MODE_EL1 << MODE_EL_SHIFT) - b.eq read_elr_el1 - cmp x0, #(MODE_EL2 << MODE_EL_SHIFT) - b.eq read_elr_el2 - cmp x0, #(MODE_EL3 << MODE_EL_SHIFT) - b.eq read_elr_el3 - - -func read_elr_el1 - mrs x0, elr_el1 - ret - - -func read_elr_el2 - mrs x0, elr_el2 - ret - - -func read_elr_el3 - mrs x0, elr_el3 - ret - - -func write_elr - mrs x1, CurrentEl - cmp x1, #(MODE_EL1 << MODE_EL_SHIFT) - b.eq write_elr_el1 - cmp x1, #(MODE_EL2 << MODE_EL_SHIFT) - b.eq write_elr_el2 - cmp x1, #(MODE_EL3 << MODE_EL_SHIFT) - b.eq write_elr_el3 - - -func write_elr_el1 - msr elr_el1, x0 - isb - ret - - -func write_elr_el2 - msr elr_el2, x0 - isb - ret - - -func write_elr_el3 - msr elr_el3, x0 - isb - ret - - -func dsb - dsb sy - ret - - -func isb - isb - ret - - -func sev - sev - ret - - -func wfe - wfe - ret - - -func wfi - wfi - ret - - -func eret - eret - - -func smc - smc #0 - -/* ----------------------------------------------------------------------- - * void zeromem16(void *mem, unsigned int length); - * - * Initialise a memory region to 0. - * The memory address must be 16-byte aligned. - * ----------------------------------------------------------------------- - */ -func zeromem16 - add x2, x0, x1 -/* zero 16 bytes at a time */ -z_loop16: - sub x3, x2, x0 - cmp x3, #16 - b.lt z_loop1 - stp xzr, xzr, [x0], #16 - b z_loop16 -/* zero byte per byte */ -z_loop1: - cmp x0, x2 - b.eq z_end - strb wzr, [x0], #1 - b z_loop1 -z_end: ret - - -/* -------------------------------------------------------------------------- - * void memcpy16(void *dest, const void *src, unsigned int length) - * - * Copy length bytes from memory area src to memory area dest. - * The memory areas should not overlap. - * Destination and source addresses must be 16-byte aligned. - * -------------------------------------------------------------------------- - */ -func memcpy16 -/* copy 16 bytes at a time */ -m_loop16: - cmp x2, #16 - b.lt m_loop1 - ldp x3, x4, [x1], #16 - stp x3, x4, [x0], #16 - sub x2, x2, #16 - b m_loop16 -/* copy byte per byte */ -m_loop1: - cbz x2, m_end - ldrb w3, [x1], #1 - strb w3, [x0], #1 - subs x2, x2, #1 - b.ne m_loop1 -m_end: ret diff --git a/lib/arch/aarch64/sysreg_helpers.S b/lib/arch/aarch64/sysreg_helpers.S deleted file mode 100644 index 8e816f0..0000000 --- a/lib/arch/aarch64/sysreg_helpers.S +++ /dev/null @@ -1,833 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - - .globl read_vbar_el1 - .globl read_vbar_el2 - .globl read_vbar_el3 - .globl write_vbar_el1 - .globl write_vbar_el2 - .globl write_vbar_el3 - - .globl read_sctlr_el1 - .globl read_sctlr_el2 - .globl read_sctlr_el3 - .globl write_sctlr_el1 - .globl write_sctlr_el2 - .globl write_sctlr_el3 - - .globl read_actlr_el1 - .globl read_actlr_el2 - .globl read_actlr_el3 - .globl write_actlr_el1 - .globl write_actlr_el2 - .globl write_actlr_el3 - - .globl read_esr_el1 - .globl read_esr_el2 - .globl read_esr_el3 - .globl write_esr_el1 - .globl write_esr_el2 - .globl write_esr_el3 - - .globl read_afsr0_el1 - .globl read_afsr0_el2 - .globl read_afsr0_el3 - .globl write_afsr0_el1 - .globl write_afsr0_el2 - .globl write_afsr0_el3 - - .globl read_afsr1_el1 - .globl read_afsr1_el2 - .globl read_afsr1_el3 - .globl write_afsr1_el1 - .globl write_afsr1_el2 - .globl write_afsr1_el3 - - .globl read_far_el1 - .globl read_far_el2 - .globl read_far_el3 - .globl write_far_el1 - .globl write_far_el2 - .globl write_far_el3 - - .globl read_mair_el1 - .globl read_mair_el2 - .globl read_mair_el3 - .globl write_mair_el1 - .globl write_mair_el2 - .globl write_mair_el3 - - .globl read_amair_el1 - .globl read_amair_el2 - .globl read_amair_el3 - .globl write_amair_el1 - .globl write_amair_el2 - .globl write_amair_el3 - - .globl read_rvbar_el1 - .globl read_rvbar_el2 - .globl read_rvbar_el3 - - .globl read_rmr_el1 - .globl read_rmr_el2 - .globl read_rmr_el3 - .globl write_rmr_el1 - .globl write_rmr_el2 - .globl write_rmr_el3 - - .globl read_tcr_el1 - .globl read_tcr_el2 - .globl read_tcr_el3 - .globl write_tcr_el1 - .globl write_tcr_el2 - .globl write_tcr_el3 - - .globl read_cptr_el2 - .globl read_cptr_el3 - .globl write_cptr_el2 - .globl write_cptr_el3 - - .globl read_ttbr0_el1 - .globl read_ttbr0_el2 - .globl read_ttbr0_el3 - .globl write_ttbr0_el1 - .globl write_ttbr0_el2 - .globl write_ttbr0_el3 - - .globl read_ttbr1_el1 - .globl read_ttbr1_el2 - .globl write_ttbr1 - .globl write_ttbr1_el1 - .globl write_ttbr1_el2 - - .globl read_cpacr - .globl write_cpacr - - .globl read_cntfrq - .globl write_cntfrq - - .globl read_cpuectlr - .globl write_cpuectlr - - .globl read_cnthctl_el2 - .globl write_cnthctl_el2 - - .globl read_cntfrq_el0 - .globl write_cntfrq_el0 - - .globl read_scr - .globl write_scr - - .globl read_hcr - .globl write_hcr - - .globl read_midr - .globl read_mpidr - - .globl read_current_el - .globl read_id_pfr1_el1 - .globl read_id_aa64pfr0_el1 - -#if SUPPORT_VFP - .globl enable_vfp - .globl read_fpexc - .globl write_fpexc -#endif - - -func read_current_el - mrs x0, CurrentEl - ret - - -func read_id_pfr1_el1 - mrs x0, id_pfr1_el1 - ret - - -func read_id_aa64pfr0_el1 - mrs x0, id_aa64pfr0_el1 - ret - - - /* ----------------------------------------------------- - * VBAR accessors - * ----------------------------------------------------- - */ -func read_vbar_el1 - mrs x0, vbar_el1 - ret - - -func read_vbar_el2 - mrs x0, vbar_el2 - ret - - -func read_vbar_el3 - mrs x0, vbar_el3 - ret - - -func write_vbar_el1 - msr vbar_el1, x0 - isb - ret - - -func write_vbar_el2 - msr vbar_el2, x0 - isb - ret - - -func write_vbar_el3 - msr vbar_el3, x0 - isb - ret - - - /* ----------------------------------------------------- - * AFSR0 accessors - * ----------------------------------------------------- - */ -func read_afsr0_el1 - mrs x0, afsr0_el1 - ret - - -func read_afsr0_el2 - mrs x0, afsr0_el2 - ret - - -func read_afsr0_el3 - mrs x0, afsr0_el3 - ret - - -func write_afsr0_el1 - msr afsr0_el1, x0 - isb - ret - - -func write_afsr0_el2 - msr afsr0_el2, x0 - isb - ret - - -func write_afsr0_el3 - msr afsr0_el3, x0 - isb - ret - - - /* ----------------------------------------------------- - * FAR accessors - * ----------------------------------------------------- - */ -func read_far_el1 - mrs x0, far_el1 - ret - - -func read_far_el2 - mrs x0, far_el2 - ret - - -func read_far_el3 - mrs x0, far_el3 - ret - - -func write_far_el1 - msr far_el1, x0 - isb - ret - - -func write_far_el2 - msr far_el2, x0 - isb - ret - - -func write_far_el3 - msr far_el3, x0 - isb - ret - - - /* ----------------------------------------------------- - * MAIR accessors - * ----------------------------------------------------- - */ -func read_mair_el1 - mrs x0, mair_el1 - ret - - -func read_mair_el2 - mrs x0, mair_el2 - ret - - -func read_mair_el3 - mrs x0, mair_el3 - ret - - -func write_mair_el1 - msr mair_el1, x0 - isb - ret - - -func write_mair_el2 - msr mair_el2, x0 - isb - ret - - -func write_mair_el3 - msr mair_el3, x0 - isb - ret - - - /* ----------------------------------------------------- - * AMAIR accessors - * ----------------------------------------------------- - */ -func read_amair_el1 - mrs x0, amair_el1 - ret - - -func read_amair_el2 - mrs x0, amair_el2 - ret - - -func read_amair_el3 - mrs x0, amair_el3 - ret - - -func write_amair_el1 - msr amair_el1, x0 - isb - ret - - -func write_amair_el2 - msr amair_el2, x0 - isb - ret - - -func write_amair_el3 - msr amair_el3, x0 - isb - ret - - - /* ----------------------------------------------------- - * RVBAR accessors - * ----------------------------------------------------- - */ -func read_rvbar_el1 - mrs x0, rvbar_el1 - ret - - -func read_rvbar_el2 - mrs x0, rvbar_el2 - ret - - -func read_rvbar_el3 - mrs x0, rvbar_el3 - ret - - - /* ----------------------------------------------------- - * RMR accessors - * ----------------------------------------------------- - */ -func read_rmr_el1 - mrs x0, rmr_el1 - ret - - -func read_rmr_el2 - mrs x0, rmr_el2 - ret - - -func read_rmr_el3 - mrs x0, rmr_el3 - ret - - -func write_rmr_el1 - msr rmr_el1, x0 - isb - ret - - -func write_rmr_el2 - msr rmr_el2, x0 - isb - ret - - -func write_rmr_el3 - msr rmr_el3, x0 - isb - ret - - - /* ----------------------------------------------------- - * AFSR1 accessors - * ----------------------------------------------------- - */ -func read_afsr1_el1 - mrs x0, afsr1_el1 - ret - - -func read_afsr1_el2 - mrs x0, afsr1_el2 - ret - - -func read_afsr1_el3 - mrs x0, afsr1_el3 - ret - - -func write_afsr1_el1 - msr afsr1_el1, x0 - isb - ret - - -func write_afsr1_el2 - msr afsr1_el2, x0 - isb - ret - - -func write_afsr1_el3 - msr afsr1_el3, x0 - isb - ret - - - /* ----------------------------------------------------- - * SCTLR accessors - * ----------------------------------------------------- - */ -func read_sctlr_el1 - mrs x0, sctlr_el1 - ret - - -func read_sctlr_el2 - mrs x0, sctlr_el2 - ret - - -func read_sctlr_el3 - mrs x0, sctlr_el3 - ret - - -func write_sctlr_el1 - msr sctlr_el1, x0 - dsb sy - isb - ret - - -func write_sctlr_el2 - msr sctlr_el2, x0 - dsb sy - isb - ret - - -func write_sctlr_el3 - msr sctlr_el3, x0 - dsb sy - isb - ret - - - /* ----------------------------------------------------- - * ACTLR accessors - * ----------------------------------------------------- - */ -func read_actlr_el1 - mrs x0, actlr_el1 - ret - - -func read_actlr_el2 - mrs x0, actlr_el2 - ret - - -func read_actlr_el3 - mrs x0, actlr_el3 - ret - - -func write_actlr_el1 - msr actlr_el1, x0 - dsb sy - isb - ret - - -func write_actlr_el2 - msr actlr_el2, x0 - dsb sy - isb - ret - - -func write_actlr_el3 - msr actlr_el3, x0 - dsb sy - isb - ret - - - /* ----------------------------------------------------- - * ESR accessors - * ----------------------------------------------------- - */ -func read_esr_el1 - mrs x0, esr_el1 - ret - - -func read_esr_el2 - mrs x0, esr_el2 - ret - - -func read_esr_el3 - mrs x0, esr_el3 - ret - - -func write_esr_el1 - msr esr_el1, x0 - dsb sy - isb - ret - - -func write_esr_el2 - msr esr_el2, x0 - dsb sy - isb - ret - - -func write_esr_el3 - msr esr_el3, x0 - dsb sy - isb - ret - - - /* ----------------------------------------------------- - * TCR accessors - * ----------------------------------------------------- - */ -func read_tcr_el1 - mrs x0, tcr_el1 - ret - - -func read_tcr_el2 - mrs x0, tcr_el2 - ret - - -func read_tcr_el3 - mrs x0, tcr_el3 - ret - - -func write_tcr_el1 - msr tcr_el1, x0 - dsb sy - isb - ret - - -func write_tcr_el2 - msr tcr_el2, x0 - dsb sy - isb - ret - - -func write_tcr_el3 - msr tcr_el3, x0 - dsb sy - isb - ret - - - /* ----------------------------------------------------- - * CPTR accessors - * ----------------------------------------------------- - */ -func read_cptr_el1 - b read_cptr_el1 - ret - - -func read_cptr_el2 - mrs x0, cptr_el2 - ret - - -func read_cptr_el3 - mrs x0, cptr_el3 - ret - - -func write_cptr_el1 - b write_cptr_el1 - - -func write_cptr_el2 - msr cptr_el2, x0 - dsb sy - isb - ret - - -func write_cptr_el3 - msr cptr_el3, x0 - dsb sy - isb - ret - - - /* ----------------------------------------------------- - * TTBR0 accessors - * ----------------------------------------------------- - */ -func read_ttbr0_el1 - mrs x0, ttbr0_el1 - ret - - -func read_ttbr0_el2 - mrs x0, ttbr0_el2 - ret - - -func read_ttbr0_el3 - mrs x0, ttbr0_el3 - ret - - -func write_ttbr0_el1 - msr ttbr0_el1, x0 - isb - ret - - -func write_ttbr0_el2 - msr ttbr0_el2, x0 - isb - ret - - -func write_ttbr0_el3 - msr ttbr0_el3, x0 - isb - ret - - - /* ----------------------------------------------------- - * TTBR1 accessors - * ----------------------------------------------------- - */ -func read_ttbr1_el1 - mrs x0, ttbr1_el1 - ret - - -func read_ttbr1_el2 - b read_ttbr1_el2 - - -func read_ttbr1_el3 - b read_ttbr1_el3 - - -func write_ttbr1_el1 - msr ttbr1_el1, x0 - isb - ret - - -func write_ttbr1_el2 - b write_ttbr1_el2 - - -func write_ttbr1_el3 - b write_ttbr1_el3 - - -func read_hcr - mrs x0, hcr_el2 - ret - - -func write_hcr - msr hcr_el2, x0 - dsb sy - isb - ret - - -func read_cpacr - mrs x0, cpacr_el1 - ret - - -func write_cpacr - msr cpacr_el1, x0 - ret - - -func read_cntfrq_el0 - mrs x0, cntfrq_el0 - ret - - -func write_cntfrq_el0 - msr cntfrq_el0, x0 - ret - - -func read_cpuectlr - mrs x0, CPUECTLR_EL1 - ret - - -func write_cpuectlr - msr CPUECTLR_EL1, x0 - dsb sy - isb - ret - - -func read_cnthctl_el2 - mrs x0, cnthctl_el2 - ret - - -func write_cnthctl_el2 - msr cnthctl_el2, x0 - ret - - -func read_cntfrq - mrs x0, cntfrq_el0 - ret - - -func write_cntfrq - msr cntfrq_el0, x0 - ret - - -func write_scr - msr scr_el3, x0 - dsb sy - isb - ret - - -func read_scr - mrs x0, scr_el3 - ret - - -func read_midr - mrs x0, midr_el1 - ret - - -func read_mpidr - mrs x0, mpidr_el1 - ret - - -#if SUPPORT_VFP -func enable_vfp - mrs x0, cpacr_el1 - orr x0, x0, #CPACR_VFP_BITS - msr cpacr_el1, x0 - mrs x0, cptr_el3 - mov x1, #AARCH64_CPTR_TFP - bic x0, x0, x1 - msr cptr_el3, x0 - ret - - -func read_fpexc - b read_fpexc - ret - - -func write_fpexc - b write_fpexc - ret - -#endif diff --git a/lib/arch/aarch64/tlb_helpers.S b/lib/arch/aarch64/tlb_helpers.S deleted file mode 100644 index 4244974..0000000 --- a/lib/arch/aarch64/tlb_helpers.S +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - - .globl tlbialle1 - .globl tlbialle1is - .globl tlbialle2 - .globl tlbialle2is - .globl tlbialle3 - .globl tlbialle3is - .globl tlbivmalle1 - - -func tlbialle1 - tlbi alle1 - dsb sy - isb - ret - - -func tlbialle1is - tlbi alle1is - dsb sy - isb - ret - - -func tlbialle2 - tlbi alle2 - dsb sy - isb - ret - - -func tlbialle2is - tlbi alle2is - dsb sy - isb - ret - - -func tlbialle3 - tlbi alle3 - dsb sy - isb - ret - - -func tlbialle3is - tlbi alle3is - dsb sy - isb - ret - -func tlbivmalle1 - tlbi vmalle1 - dsb sy - isb - ret diff --git a/lib/arch/aarch64/xlat_helpers.c b/lib/arch/aarch64/xlat_helpers.c deleted file mode 100644 index 87d24ec..0000000 --- a/lib/arch/aarch64/xlat_helpers.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - -/******************************************************************************* - * Helper to create a level 1/2 table descriptor which points to a level 2/3 - * table. - ******************************************************************************/ -unsigned long create_table_desc(unsigned long *next_table_ptr) -{ - unsigned long desc = (unsigned long) next_table_ptr; - - /* Clear the last 12 bits */ - desc >>= FOUR_KB_SHIFT; - desc <<= FOUR_KB_SHIFT; - - desc |= TABLE_DESC; - - return desc; -} - -/******************************************************************************* - * Helper to create a level 1/2/3 block descriptor which maps the va to addr - ******************************************************************************/ -unsigned long create_block_desc(unsigned long desc, - unsigned long addr, - unsigned int level) -{ - switch (level) { - case LEVEL1: - desc |= (addr << FIRST_LEVEL_DESC_N) | BLOCK_DESC; - break; - case LEVEL2: - desc |= (addr << SECOND_LEVEL_DESC_N) | BLOCK_DESC; - break; - case LEVEL3: - desc |= (addr << THIRD_LEVEL_DESC_N) | TABLE_DESC; - break; - default: - assert(0); - } - - return desc; -} - -/******************************************************************************* - * Helper to create a level 1/2/3 block descriptor which maps the va to output_ - * addr with Device nGnRE attributes. - ******************************************************************************/ -unsigned long create_device_block(unsigned long output_addr, - unsigned int level, - unsigned int ns) -{ - unsigned long upper_attrs, lower_attrs, desc; - - lower_attrs = LOWER_ATTRS(ACCESS_FLAG | OSH | AP_RW); - lower_attrs |= LOWER_ATTRS(ns | ATTR_DEVICE_INDEX); - upper_attrs = UPPER_ATTRS(XN); - desc = upper_attrs | lower_attrs; - - return create_block_desc(desc, output_addr, level); -} - -/******************************************************************************* - * Helper to create a level 1/2/3 block descriptor which maps the va to output_ - * addr with inner-shareable normal wbwa read-only memory attributes. - ******************************************************************************/ -unsigned long create_romem_block(unsigned long output_addr, - unsigned int level, - unsigned int ns) -{ - unsigned long upper_attrs, lower_attrs, desc; - - lower_attrs = LOWER_ATTRS(ACCESS_FLAG | ISH | AP_RO); - lower_attrs |= LOWER_ATTRS(ns | ATTR_IWBWA_OWBWA_NTR_INDEX); - upper_attrs = UPPER_ATTRS(0ull); - desc = upper_attrs | lower_attrs; - - return create_block_desc(desc, output_addr, level); -} - -/******************************************************************************* - * Helper to create a level 1/2/3 block descriptor which maps the va to output_ - * addr with inner-shareable normal wbwa read-write memory attributes. - ******************************************************************************/ -unsigned long create_rwmem_block(unsigned long output_addr, - unsigned int level, - unsigned int ns) -{ - unsigned long upper_attrs, lower_attrs, desc; - - lower_attrs = LOWER_ATTRS(ACCESS_FLAG | ISH | AP_RW); - lower_attrs |= LOWER_ATTRS(ns | ATTR_IWBWA_OWBWA_NTR_INDEX); - upper_attrs = UPPER_ATTRS(XN); - desc = upper_attrs | lower_attrs; - - return create_block_desc(desc, output_addr, level); -} diff --git a/lib/arch/aarch64/xlat_tables.c b/lib/arch/aarch64/xlat_tables.c deleted file mode 100644 index 33a8b6d..0000000 --- a/lib/arch/aarch64/xlat_tables.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include - - -#ifndef DEBUG_XLAT_TABLE -#define DEBUG_XLAT_TABLE 0 -#endif - -#if DEBUG_XLAT_TABLE -#define debug_print(...) printf(__VA_ARGS__) -#else -#define debug_print(...) ((void)0) -#endif - - -#define UNSET_DESC ~0ul - -#define NUM_L1_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT) - -uint64_t l1_xlation_table[NUM_L1_ENTRIES] -__aligned(NUM_L1_ENTRIES * sizeof(uint64_t)); - -static uint64_t xlat_tables[MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES] -__aligned(XLAT_TABLE_SIZE) __attribute__((section("xlat_table"))); - -static unsigned next_xlat; - -/* - * Array of all memory regions stored in order of ascending base address. - * The list is terminated by the first entry with size == 0. - */ -static mmap_region mmap[MAX_MMAP_REGIONS + 1]; - - -static void print_mmap(void) -{ -#if DEBUG_XLAT_TABLE - debug_print("mmap:\n"); - mmap_region *mm = mmap; - while (mm->size) { - debug_print(" %010lx %10lx %x\n", mm->base, mm->size, mm->attr); - ++mm; - }; - debug_print("\n"); -#endif -} - -void mmap_add_region(unsigned long base, unsigned long size, unsigned attr) -{ - mmap_region *mm = mmap; - mmap_region *mm_last = mm + sizeof(mmap) / sizeof(mmap[0]) - 1; - - assert(IS_PAGE_ALIGNED(base)); - assert(IS_PAGE_ALIGNED(size)); - - if (!size) - return; - - /* Find correct place in mmap to insert new region */ - while (mm->base < base && mm->size) - ++mm; - - /* Make room for new region by moving other regions up by one place */ - memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm); - - /* Check we haven't lost the empty sentinal from the end of the array */ - assert(mm_last->size == 0); - - mm->base = base; - mm->size = size; - mm->attr = attr; -} - -void mmap_add(const mmap_region *mm) -{ - while (mm->size) { - mmap_add_region(mm->base, mm->size, mm->attr); - ++mm; - } -} - -static unsigned long mmap_desc(unsigned attr, unsigned long addr, - unsigned level) -{ - unsigned long desc = addr; - - desc |= level == 3 ? TABLE_DESC : BLOCK_DESC; - - desc |= attr & MT_NS ? LOWER_ATTRS(NS) : 0; - - desc |= attr & MT_RW ? LOWER_ATTRS(AP_RW) : LOWER_ATTRS(AP_RO); - - desc |= LOWER_ATTRS(ACCESS_FLAG); - - if (attr & MT_MEMORY) { - desc |= LOWER_ATTRS(ATTR_IWBWA_OWBWA_NTR_INDEX | ISH); - if (attr & MT_RW) - desc |= UPPER_ATTRS(XN); - } else { - desc |= LOWER_ATTRS(ATTR_DEVICE_INDEX | OSH); - desc |= UPPER_ATTRS(XN); - } - - debug_print(attr & MT_MEMORY ? "MEM" : "DEV"); - debug_print(attr & MT_RW ? "-RW" : "-RO"); - debug_print(attr & MT_NS ? "-NS" : "-S"); - - return desc; -} - -static int mmap_region_attr(mmap_region *mm, unsigned long base, - unsigned long size) -{ - int attr = mm->attr; - - for (;;) { - ++mm; - - if (!mm->size) - return attr; /* Reached end of list */ - - if (mm->base >= base + size) - return attr; /* Next region is after area so end */ - - if (mm->base + mm->size <= base) - continue; /* Next region has already been overtaken */ - - if ((mm->attr & attr) == attr) - continue; /* Region doesn't override attribs so skip */ - - attr &= mm->attr; - - if (mm->base > base || mm->base + mm->size < base + size) - return -1; /* Region doesn't fully cover our area */ - } -} - -static mmap_region *init_xlation_table(mmap_region *mm, unsigned long base, - unsigned long *table, unsigned level) -{ - unsigned level_size_shift = L1_XLAT_ADDRESS_SHIFT - (level - 1) * - XLAT_TABLE_ENTRIES_SHIFT; - unsigned level_size = 1 << level_size_shift; - unsigned level_index_mask = XLAT_TABLE_ENTRIES_MASK << level_size_shift; - - assert(level <= 3); - - debug_print("New xlat table:\n"); - - do { - unsigned long desc = UNSET_DESC; - - if (mm->base + mm->size <= base) { - /* Area now after the region so skip it */ - ++mm; - continue; - } - - debug_print(" %010lx %8lx " + 6 - 2 * level, base, level_size); - - if (mm->base >= base + level_size) { - /* Next region is after area so nothing to map yet */ - desc = INVALID_DESC; - } else if (mm->base <= base && - mm->base + mm->size >= base + level_size) { - /* Next region covers all of area */ - int attr = mmap_region_attr(mm, base, level_size); - if (attr >= 0) - desc = mmap_desc(attr, base, level); - } - /* else Next region only partially covers area, so need */ - - if (desc == UNSET_DESC) { - /* Area not covered by a region so need finer table */ - unsigned long *new_table = xlat_tables[next_xlat++]; - assert(next_xlat <= MAX_XLAT_TABLES); - desc = TABLE_DESC | (unsigned long)new_table; - - /* Recurse to fill in new table */ - mm = init_xlation_table(mm, base, new_table, level+1); - } - - debug_print("\n"); - - *table++ = desc; - base += level_size; - } while (mm->size && (base & level_index_mask)); - - return mm; -} - -void init_xlat_tables(void) -{ - print_mmap(); - init_xlation_table(mmap, 0, l1_xlation_table, 1); -} diff --git a/lib/locks/bakery/bakery_lock.c b/lib/locks/bakery/bakery_lock.c new file mode 100644 index 0000000..03f1e74 --- /dev/null +++ b/lib/locks/bakery/bakery_lock.c @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include + +/* + * Functions in this file implement Bakery Algorithm for mutual exclusion. + * + * ARM architecture offers a family of exclusive access instructions to + * efficiently implement mutual exclusion with hardware support. However, as + * well as depending on external hardware, the these instructions have defined + * behavior only on certain memory types (cacheable and Normal memory in + * particular; see ARMv8 Architecture Reference Manual section B2.10). Use cases + * in trusted firmware are such that mutual exclusion implementation cannot + * expect that accesses to the lock have the specific type required by the + * architecture for these primitives to function (for example, not all + * contenders may have address translation enabled). + * + * This implementation does not use mutual exclusion primitives. It expects + * memory regions where the locks reside to be fully ordered and coherent + * (either by disabling address translation, or by assigning proper attributes + * when translation is enabled). + * + * Note that the ARM architecture guarantees single-copy atomicity for aligned + * accesses regardless of status of address translation. + */ + +#define assert_bakery_entry_valid(entry, bakery) do { \ + assert(bakery); \ + assert(entry < BAKERY_LOCK_MAX_CPUS); \ +} while (0) + +/* Convert a ticket to priority */ +#define PRIORITY(t, pos) (((t) << 8) | (pos)) + + +/* Initialize Bakery Lock to reset ownership and all ticket values */ +void bakery_lock_init(bakery_lock *bakery) +{ + assert(bakery); + + /* All ticket values need to be 0 */ + memset(bakery, 0, sizeof(*bakery)); + bakery->owner = NO_OWNER; +} + + +/* Obtain a ticket for a given CPU */ +static unsigned int bakery_get_ticket(bakery_lock *bakery, unsigned int me) +{ + unsigned int my_ticket, their_ticket; + unsigned int they; + + /* + * Flag that we're busy getting our ticket. All CPUs are iterated in the + * order of their ordinal position to decide the maximum ticket value + * observed so far. Our priority is set to be greater than the maximum + * observed priority + * + * Note that it's possible that more than one contender gets the same + * ticket value. That's OK as the lock is acquired based on the priority + * value, not the ticket value alone. + */ + my_ticket = 0; + bakery->entering[me] = 1; + for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) { + their_ticket = bakery->number[they]; + if (their_ticket > my_ticket) + my_ticket = their_ticket; + } + + /* + * Compute ticket; then signal to other contenders waiting for us to + * finish calculating our ticket value that we're done + */ + ++my_ticket; + bakery->number[me] = my_ticket; + bakery->entering[me] = 0; + sev(); + + return my_ticket; +} + + +/* + * Acquire bakery lock + * + * Contending CPUs need first obtain a non-zero ticket and then calculate + * priority value. A contending CPU iterate over all other CPUs in the platform, + * which may be contending for the same lock, in the order of their ordinal + * position (CPU0, CPU1 and so on). A non-contending CPU will have its ticket + * (and priority) value as 0. The contending CPU compares its priority with that + * of others'. The CPU with the highest priority (lowest numerical value) + * acquires the lock + */ +void bakery_lock_get(unsigned long mpidr, bakery_lock *bakery) +{ + unsigned int they, me; + unsigned int my_ticket, my_prio, their_ticket; + + me = platform_get_core_pos(mpidr); + + assert_bakery_entry_valid(me, bakery); + + /* Prevent recursive acquisition */ + assert(bakery->owner != me); + + /* Get a ticket */ + my_ticket = bakery_get_ticket(bakery, me); + + /* + * Now that we got our ticket, compute our priority value, then compare + * with that of others, and proceed to acquire the lock + */ + my_prio = PRIORITY(my_ticket, me); + for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) { + if (me == they) + continue; + + /* Wait for the contender to get their ticket */ + while (bakery->entering[they]) + wfe(); + + /* + * If the other party is a contender, they'll have non-zero + * (valid) ticket value. If they do, compare priorities + */ + their_ticket = bakery->number[they]; + if (their_ticket && (PRIORITY(their_ticket, they) < my_prio)) { + /* + * They have higher priority (lower value). Wait for + * their ticket value to change (either release the lock + * to have it dropped to 0; or drop and probably content + * again for the same lock to have an even higher value) + */ + do { + wfe(); + } while (their_ticket == bakery->number[they]); + } + } + + /* Lock acquired */ + bakery->owner = me; +} + + +/* Release the lock and signal contenders */ +void bakery_lock_release(unsigned long mpidr, bakery_lock *bakery) +{ + unsigned int me = platform_get_core_pos(mpidr); + + assert_bakery_entry_valid(me, bakery); + assert(bakery->owner == me); + + /* + * Release lock by resetting ownership and ticket. Then signal other + * waiting contenders + */ + bakery->owner = NO_OWNER; + bakery->number[me] = 0; + sev(); +} diff --git a/lib/locks/exclusive/spinlock.S b/lib/locks/exclusive/spinlock.S new file mode 100644 index 0000000..5eae2b0 --- /dev/null +++ b/lib/locks/exclusive/spinlock.S @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + + .globl spin_lock + .globl spin_unlock + + +func spin_lock + mov w2, #1 + sevl +l1: wfe +l2: ldaxr w1, [x0] + cbnz w1, l1 + stxr w1, w2, [x0] + cbnz w1, l2 + ret + + +func spin_unlock + stlr wzr, [x0] + ret diff --git a/lib/sync/locks/bakery/bakery_lock.c b/lib/sync/locks/bakery/bakery_lock.c deleted file mode 100644 index ec08135..0000000 --- a/lib/sync/locks/bakery/bakery_lock.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - -#include -#include - -/* - * Functions in this file implement Bakery Algorithm for mutual exclusion. - * - * ARM architecture offers a family of exclusive access instructions to - * efficiently implement mutual exclusion with hardware support. However, as - * well as depending on external hardware, the these instructions have defined - * behavior only on certain memory types (cacheable and Normal memory in - * particular; see ARMv8 Architecture Reference Manual section B2.10). Use cases - * in trusted firmware are such that mutual exclusion implementation cannot - * expect that accesses to the lock have the specific type required by the - * architecture for these primitives to function (for example, not all - * contenders may have address translation enabled). - * - * This implementation does not use mutual exclusion primitives. It expects - * memory regions where the locks reside to be fully ordered and coherent - * (either by disabling address translation, or by assigning proper attributes - * when translation is enabled). - * - * Note that the ARM architecture guarantees single-copy atomicity for aligned - * accesses regardless of status of address translation. - */ - -#define assert_bakery_entry_valid(entry, bakery) do { \ - assert(bakery); \ - assert(entry < BAKERY_LOCK_MAX_CPUS); \ -} while(0) - -/* Convert a ticket to priority */ -#define PRIORITY(t, pos) (((t) << 8) | (pos)) - - -/* Initialize Bakery Lock to reset ownership and all ticket values */ -void bakery_lock_init(bakery_lock * bakery) -{ - assert(bakery); - - /* All ticket values need to be 0 */ - memset(bakery, 0, sizeof(*bakery)); - bakery->owner = NO_OWNER; -} - - -/* Obtain a ticket for a given CPU */ -static unsigned int bakery_get_ticket(bakery_lock *bakery, unsigned int me) -{ - unsigned int my_ticket, their_ticket; - unsigned int they; - - /* - * Flag that we're busy getting our ticket. All CPUs are iterated in the - * order of their ordinal position to decide the maximum ticket value - * observed so far. Our priority is set to be greater than the maximum - * observed priority - * - * Note that it's possible that more than one contender gets the same - * ticket value. That's OK as the lock is acquired based on the priority - * value, not the ticket value alone. - */ - my_ticket = 0; - bakery->entering[me] = 1; - for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) { - their_ticket = bakery->number[they]; - if (their_ticket > my_ticket) - my_ticket = their_ticket; - } - - /* - * Compute ticket; then signal to other contenders waiting for us to - * finish calculating our ticket value that we're done - */ - ++my_ticket; - bakery->number[me] = my_ticket; - bakery->entering[me] = 0; - sev(); - - return my_ticket; -} - - -/* - * Acquire bakery lock - * - * Contending CPUs need first obtain a non-zero ticket and then calculate - * priority value. A contending CPU iterate over all other CPUs in the platform, - * which may be contending for the same lock, in the order of their ordinal - * position (CPU0, CPU1 and so on). A non-contending CPU will have its ticket - * (and priority) value as 0. The contending CPU compares its priority with that - * of others'. The CPU with the highest priority (lowest numerical value) - * acquires the lock - */ -void bakery_lock_get(unsigned long mpidr, bakery_lock *bakery) -{ - unsigned int they, me; - unsigned int my_ticket, my_prio, their_ticket; - - me = platform_get_core_pos(mpidr); - - assert_bakery_entry_valid(me, bakery); - - /* Prevent recursive acquisition */ - assert(bakery->owner != me); - - /* Get a ticket */ - my_ticket = bakery_get_ticket(bakery, me); - - /* - * Now that we got our ticket, compute our priority value, then compare - * with that of others, and proceed to acquire the lock - */ - my_prio = PRIORITY(my_ticket, me); - for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) { - if (me == they) - continue; - - /* Wait for the contender to get their ticket */ - while (bakery->entering[they]) - wfe(); - - /* - * If the other party is a contender, they'll have non-zero - * (valid) ticket value. If they do, compare priorities - */ - their_ticket = bakery->number[they]; - if (their_ticket && (PRIORITY(their_ticket, they) < my_prio)) { - /* - * They have higher priority (lower value). Wait for - * their ticket value to change (either release the lock - * to have it dropped to 0; or drop and probably content - * again for the same lock to have an even higher value) - */ - do { - wfe(); - } while (their_ticket == bakery->number[they]); - } - } - - /* Lock acquired */ - bakery->owner = me; -} - - -/* Release the lock and signal contenders */ -void bakery_lock_release(unsigned long mpidr, bakery_lock * bakery) -{ - unsigned int me = platform_get_core_pos(mpidr); - - assert_bakery_entry_valid(me, bakery); - assert(bakery->owner == me); - - /* - * Release lock by resetting ownership and ticket. Then signal other - * waiting contenders - */ - bakery->owner = NO_OWNER; - bakery->number[me] = 0; - sev(); -} diff --git a/lib/sync/locks/exclusive/spinlock.S b/lib/sync/locks/exclusive/spinlock.S deleted file mode 100644 index 5eae2b0..0000000 --- a/lib/sync/locks/exclusive/spinlock.S +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include - - .globl spin_lock - .globl spin_unlock - - -func spin_lock - mov w2, #1 - sevl -l1: wfe -l2: ldaxr w1, [x0] - cbnz w1, l1 - stxr w1, w2, [x0] - cbnz w1, l2 - ret - - -func spin_unlock - stlr wzr, [x0] - ret diff --git a/plat/fvp/platform.mk b/plat/fvp/platform.mk index 0fc45de..2b904ee 100644 --- a/plat/fvp/platform.mk +++ b/plat/fvp/platform.mk @@ -28,34 +28,33 @@ # POSSIBILITY OF SUCH DAMAGE. # -PLAT_INCLUDES := -Idrivers/arm/interconnect/cci-400 \ - -Idrivers/arm/interconnect/tzc-400 \ - -Idrivers/console \ - -Idrivers/arm/peripherals/pl011 \ - -Idrivers/power +# +# No additional platform system include directories required +# +# PLAT_INCLUDES := -PLAT_BL1_C_VPATH := drivers/arm/interconnect/cci-400 \ - drivers/arm/peripherals/pl011 \ - lib/arch/${ARCH} \ +PLAT_BL1_C_VPATH := drivers/arm/cci400 \ + drivers/arm/pl011 \ + lib/${ARCH} \ lib/semihosting \ lib/stdlib \ drivers/io PLAT_BL1_S_VPATH := lib/semihosting/${ARCH} -PLAT_BL2_C_VPATH := drivers/arm/interconnect/cci-400 \ - drivers/arm/interconnect/tzc-400 \ - drivers/arm/peripherals/pl011 \ - lib/arch/${ARCH} \ +PLAT_BL2_C_VPATH := drivers/arm/cci400 \ + drivers/arm/pl011 \ + drivers/arm/tzc400 \ + lib/${ARCH} \ lib/stdlib \ lib/semihosting \ drivers/io PLAT_BL2_S_VPATH := lib/semihosting/${ARCH} -PLAT_BL31_C_VPATH := drivers/arm/interconnect/cci-400 \ - drivers/arm/peripherals/pl011 \ - lib/arch/${ARCH} \ +PLAT_BL31_C_VPATH := drivers/arm/cci-400 \ + drivers/arm/pl011 \ + lib/${ARCH} \ lib/semihosting \ lib/stdlib \ drivers/power \ diff --git a/services/spd/tspd/tspd.mk b/services/spd/tspd/tspd.mk index bbf9f67..532e168 100644 --- a/services/spd/tspd/tspd.mk +++ b/services/spd/tspd/tspd.mk @@ -29,7 +29,7 @@ # TSPD_DIR := services/spd/tspd -SPD_INCLUDES := -Iinclude/spd/tspd \ +SPD_INCLUDES := -Iinclude/bl32/payloads \ -I${TSPD_DIR} SPD_SOURCES := tspd_common.c \ diff --git a/tools/fip_create/firmware_image_package.h b/tools/fip_create/firmware_image_package.h index 2c0d017..cc61903 120000 --- a/tools/fip_create/firmware_image_package.h +++ b/tools/fip_create/firmware_image_package.h @@ -1 +1 @@ -../../include/firmware_image_package.h \ No newline at end of file +../../include/common/firmware_image_package.h \ No newline at end of file