diff --git a/drivers/rpi3/mailbox/rpi3_mbox.c b/drivers/rpi3/mailbox/rpi3_mbox.c new file mode 100644 index 0000000..aef1f39 --- /dev/null +++ b/drivers/rpi3/mailbox/rpi3_mbox.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include + +#include + +#include + +#define RPI3_MAILBOX_MAX_RETRIES U(1000000) + +/******************************************************************************* + * Routine to send requests to the VideoCore using the mailboxes. + ******************************************************************************/ +void rpi3_vc_mailbox_request_send(rpi3_mbox_request_t *req, int req_size) +{ + uint32_t st, data; + uintptr_t resp_addr, addr; + unsigned int retries; + + /* This is the location of the request buffer */ + addr = (uintptr_t)req; + + /* Make sure that the changes are seen by the VideoCore */ + flush_dcache_range(addr, req_size); + + /* Wait until the outbound mailbox is empty */ + retries = 0U; + + do { + st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX1_STATUS_OFFSET); + + retries++; + if (retries == RPI3_MAILBOX_MAX_RETRIES) { + ERROR("rpi3: mbox: Send request timeout\n"); + return; + } + + } while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) == 0U); + + /* Send base address of this message to start request */ + mmio_write_32(RPI3_MBOX_BASE + RPI3_MBOX1_WRITE_OFFSET, + RPI3_CHANNEL_ARM_TO_VC | (uint32_t) addr); + + /* Wait until the inbound mailbox isn't empty */ + retries = 0U; + + do { + st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_STATUS_OFFSET); + + retries++; + if (retries == RPI3_MAILBOX_MAX_RETRIES) { + ERROR("rpi3: mbox: Receive response timeout\n"); + return; + } + + } while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) != 0U); + + /* Get location and channel */ + data = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_READ_OFFSET); + + if ((data & RPI3_CHANNEL_MASK) != RPI3_CHANNEL_ARM_TO_VC) { + ERROR("rpi3: mbox: Wrong channel: 0x%08x\n", data); + panic(); + } + + resp_addr = (uintptr_t)(data & ~RPI3_CHANNEL_MASK); + if (addr != resp_addr) { + ERROR("rpi3: mbox: Unexpected address: 0x%08x\n", data); + panic(); + } + + /* Make sure that the data seen by the CPU is up to date */ + inv_dcache_range(addr, req_size); +} diff --git a/drivers/rpi3/rng/rpi3_rng.c b/drivers/rpi3/rng/rpi3_rng.c new file mode 100644 index 0000000..b6bf005 --- /dev/null +++ b/drivers/rpi3/rng/rpi3_rng.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include + +/* Initial amount of values to discard */ +#define RNG_WARMUP_COUNT U(0x40000) + +static void rpi3_rng_initialize(void) +{ + uint32_t int_mask, ctrl; + + /* Return if it is already enabled */ + ctrl = mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_CTRL_OFFSET); + if ((ctrl & RPI3_RNG_CTRL_ENABLE) != 0U) { + return; + } + + /* Mask interrupts */ + int_mask = mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_INT_MASK_OFFSET); + int_mask |= RPI3_RNG_INT_MASK_DISABLE; + mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_INT_MASK_OFFSET, int_mask); + + /* Discard several values when initializing to give it time to warmup */ + mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_STATUS_OFFSET, RNG_WARMUP_COUNT); + + mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_CTRL_OFFSET, + RPI3_RNG_CTRL_ENABLE); +} + +static uint32_t rpi3_rng_get_word(void) +{ + size_t nwords; + + do { + /* Get number of available words to read */ + nwords = (mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_STATUS_OFFSET) + >> RPI3_RNG_STATUS_NUM_WORDS_SHIFT) + & RPI3_RNG_STATUS_NUM_WORDS_MASK; + } while (nwords == 0U); + + return mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_DATA_OFFSET); +} + +void rpi3_rng_read(void *buf, size_t len) +{ + uint32_t data; + size_t left = len; + uint32_t *dst = buf; + + assert(buf != NULL); + assert(len != 0U); + assert(check_uptr_overflow((uintptr_t) buf, (uintptr_t) len) == 0); + + rpi3_rng_initialize(); + + while (left >= sizeof(uint32_t)) { + data = rpi3_rng_get_word(); + *dst++ = data; + left -= sizeof(uint32_t); + } + + if (left > 0U) { + data = rpi3_rng_get_word(); + memcpy(dst, &data, left); + } +} diff --git a/include/drivers/rpi3/mailbox/rpi3_mbox.h b/include/drivers/rpi3/mailbox/rpi3_mbox.h new file mode 100644 index 0000000..c107440 --- /dev/null +++ b/include/drivers/rpi3/mailbox/rpi3_mbox.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RPI3_MBOX_H +#define RPI3_MBOX_H + +#include + +/* This struct must be aligned to 16 bytes */ +typedef struct __packed __aligned(16) rpi3_mbox_request { + uint32_t size; /* Buffer size in bytes */ + uint32_t code; /* Request/response code */ + uint32_t tags[0]; +} rpi3_mbox_request_t; + +#define RPI3_MBOX_BUFFER_SIZE U(256) + +/* Constants to perform a request/check the status of a request. */ +#define RPI3_MBOX_PROCESS_REQUEST U(0x00000000) +#define RPI3_MBOX_REQUEST_SUCCESSFUL U(0x80000000) +#define RPI3_MBOX_REQUEST_ERROR U(0x80000001) + +/* Command constants */ +#define RPI3_TAG_HARDWARE_GET_BOARD_REVISION U(0x00010002) +#define RPI3_TAG_END U(0x00000000) + +#define RPI3_TAG_REQUEST U(0x00000000) +#define RPI3_TAG_IS_RESPONSE U(0x80000000) /* Set if response */ +#define RPI3_TAG_RESPONSE_LENGTH_MASK U(0x7FFFFFFF) + +#define RPI3_CHANNEL_ARM_TO_VC U(0x8) +#define RPI3_CHANNEL_MASK U(0xF) + +void rpi3_vc_mailbox_request_send(rpi3_mbox_request_t *req, int req_size); + +#endif diff --git a/include/drivers/rpi3/rng/rpi3_rng.h b/include/drivers/rpi3/rng/rpi3_rng.h new file mode 100644 index 0000000..ea5a677 --- /dev/null +++ b/include/drivers/rpi3/rng/rpi3_rng.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RPI3_RNG_H +#define RPI3_RNG_H + +void rpi3_rng_read(void *buf, size_t len); + +#endif diff --git a/plat/rpi/rpi3/aarch64/plat_helpers.S b/plat/rpi/rpi3/aarch64/plat_helpers.S index 7974b60..556d872 100644 --- a/plat/rpi/rpi3/aarch64/plat_helpers.S +++ b/plat/rpi/rpi3/aarch64/plat_helpers.S @@ -9,7 +9,7 @@ #include #include -#include "../rpi3_hw.h" +#include "../include/rpi_hw.h" .globl plat_crash_console_flush .globl plat_crash_console_init diff --git a/plat/rpi/rpi3/include/platform_def.h b/plat/rpi/rpi3/include/platform_def.h index 4d90222..2a12fe7 100644 --- a/plat/rpi/rpi3/include/platform_def.h +++ b/plat/rpi/rpi3/include/platform_def.h @@ -12,7 +12,7 @@ #include #include -#include "../rpi3_hw.h" +#include "rpi_hw.h" /* Special value used to verify platform parameters from BL2 to BL31 */ #define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) diff --git a/plat/rpi/rpi3/include/rpi_hw.h b/plat/rpi/rpi3/include/rpi_hw.h new file mode 100644 index 0000000..7a3ea57 --- /dev/null +++ b/plat/rpi/rpi3/include/rpi_hw.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RPI_HW_H +#define RPI_HW_H + +#include + +/* + * Peripherals + */ + +#define RPI3_IO_BASE ULL(0x3F000000) +#define RPI3_IO_SIZE ULL(0x01000000) + +/* + * ARM <-> VideoCore mailboxes + */ +#define RPI3_MBOX_OFFSET ULL(0x0000B880) +#define RPI3_MBOX_BASE (RPI3_IO_BASE + RPI3_MBOX_OFFSET) +/* VideoCore -> ARM */ +#define RPI3_MBOX0_READ_OFFSET ULL(0x00000000) +#define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010) +#define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014) +#define RPI3_MBOX0_STATUS_OFFSET ULL(0x00000018) +#define RPI3_MBOX0_CONFIG_OFFSET ULL(0x0000001C) +/* ARM -> VideoCore */ +#define RPI3_MBOX1_WRITE_OFFSET ULL(0x00000020) +#define RPI3_MBOX1_PEEK_OFFSET ULL(0x00000030) +#define RPI3_MBOX1_SENDER_OFFSET ULL(0x00000034) +#define RPI3_MBOX1_STATUS_OFFSET ULL(0x00000038) +#define RPI3_MBOX1_CONFIG_OFFSET ULL(0x0000003C) +/* Mailbox status constants */ +#define RPI3_MBOX_STATUS_FULL_MASK U(0x80000000) /* Set if full */ +#define RPI3_MBOX_STATUS_EMPTY_MASK U(0x40000000) /* Set if empty */ + +/* + * Power management, reset controller, watchdog. + */ +#define RPI3_IO_PM_OFFSET ULL(0x00100000) +#define RPI3_PM_BASE (RPI3_IO_BASE + RPI3_IO_PM_OFFSET) +/* Registers on top of RPI3_PM_BASE. */ +#define RPI3_PM_RSTC_OFFSET ULL(0x0000001C) +#define RPI3_PM_RSTS_OFFSET ULL(0x00000020) +#define RPI3_PM_WDOG_OFFSET ULL(0x00000024) +/* Watchdog constants */ +#define RPI3_PM_PASSWORD U(0x5A000000) +#define RPI3_PM_RSTC_WRCFG_MASK U(0x00000030) +#define RPI3_PM_RSTC_WRCFG_FULL_RESET U(0x00000020) +/* + * The RSTS register is used by the VideoCore firmware when booting the + * Raspberry Pi to know which partition to boot from. The partition value is + * formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware + * to indicate halt. + */ +#define RPI3_PM_RSTS_WRCFG_HALT U(0x00000555) + +/* + * Hardware random number generator. + */ +#define RPI3_IO_RNG_OFFSET ULL(0x00104000) +#define RPI3_RNG_BASE (RPI3_IO_BASE + RPI3_IO_RNG_OFFSET) +#define RPI3_RNG_CTRL_OFFSET ULL(0x00000000) +#define RPI3_RNG_STATUS_OFFSET ULL(0x00000004) +#define RPI3_RNG_DATA_OFFSET ULL(0x00000008) +#define RPI3_RNG_INT_MASK_OFFSET ULL(0x00000010) +/* Enable/disable RNG */ +#define RPI3_RNG_CTRL_ENABLE U(0x1) +#define RPI3_RNG_CTRL_DISABLE U(0x0) +/* Number of currently available words */ +#define RPI3_RNG_STATUS_NUM_WORDS_SHIFT U(24) +#define RPI3_RNG_STATUS_NUM_WORDS_MASK U(0xFF) +/* Value to mask interrupts caused by the RNG */ +#define RPI3_RNG_INT_MASK_DISABLE U(0x1) + +/* + * Serial port (called 'Mini UART' in the BCM docucmentation). + */ +#define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040) +#define RPI3_MINI_UART_BASE (RPI3_IO_BASE + RPI3_IO_MINI_UART_OFFSET) +#define RPI3_MINI_UART_CLK_IN_HZ ULL(500000000) + +/* + * GPIO controller + */ +#define RPI3_IO_GPIO_OFFSET ULL(0x00200000) +#define RPI3_GPIO_BASE (RPI3_IO_BASE + RPI3_IO_GPIO_OFFSET) + +/* + * SDHost controller + */ +#define RPI3_IO_SDHOST_OFFSET ULL(0x00202000) +#define RPI3_SDHOST_BASE (RPI3_IO_BASE + RPI3_IO_SDHOST_OFFSET) + +/* + * Local interrupt controller + */ +#define RPI3_INTC_BASE_ADDRESS ULL(0x40000000) +/* Registers on top of RPI3_INTC_BASE_ADDRESS */ +#define RPI3_INTC_CONTROL_OFFSET ULL(0x00000000) +#define RPI3_INTC_PRESCALER_OFFSET ULL(0x00000008) +#define RPI3_INTC_MBOX_CONTROL_OFFSET ULL(0x00000050) +#define RPI3_INTC_MBOX_CONTROL_SLOT3_FIQ ULL(0x00000080) +#define RPI3_INTC_PENDING_FIQ_OFFSET ULL(0x00000070) +#define RPI3_INTC_PENDING_FIQ_MBOX3 ULL(0x00000080) + +#endif /* RPI_HW_H */ diff --git a/plat/rpi/rpi3/platform.mk b/plat/rpi/rpi3/platform.mk index c011c0a..21a880c 100644 --- a/plat/rpi/rpi3/platform.mk +++ b/plat/rpi/rpi3/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -21,7 +21,8 @@ plat/rpi/rpi3/aarch64/plat_helpers.S \ plat/rpi/rpi3/rpi3_bl1_setup.c \ plat/rpi/rpi3/rpi3_io_storage.c \ - plat/rpi/rpi3/rpi3_mbox.c + drivers/rpi3/mailbox/rpi3_mbox.c \ + plat/rpi/rpi3/rpi_mbox_board.c BL2_SOURCES += common/desc_image_load.c \ drivers/io/io_fip.c \ @@ -158,7 +159,7 @@ endif ifneq ($(ENABLE_STACK_PROTECTOR), 0) -PLAT_BL_COMMON_SOURCES += plat/rpi/rpi3/rpi3_rng.c \ +PLAT_BL_COMMON_SOURCES += drivers/rpi3/rng/rpi3_rng.c \ plat/rpi/rpi3/rpi3_stack_protector.c endif diff --git a/plat/rpi/rpi3/rpi3_common.c b/plat/rpi/rpi3/rpi3_common.c index 9b10974..85a26c2 100644 --- a/plat/rpi/rpi3/rpi3_common.c +++ b/plat/rpi/rpi3/rpi3_common.c @@ -16,7 +16,7 @@ #include #include -#include "rpi3_hw.h" +#include #include "rpi3_private.h" #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ diff --git a/plat/rpi/rpi3/rpi3_hw.h b/plat/rpi/rpi3/rpi3_hw.h deleted file mode 100644 index 1a86835..0000000 --- a/plat/rpi/rpi3/rpi3_hw.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef RPI3_HW_H -#define RPI3_HW_H - -#include - -/* - * Peripherals - */ - -#define RPI3_IO_BASE ULL(0x3F000000) -#define RPI3_IO_SIZE ULL(0x01000000) - -/* - * ARM <-> VideoCore mailboxes - */ -#define RPI3_MBOX_OFFSET ULL(0x0000B880) -#define RPI3_MBOX_BASE (RPI3_IO_BASE + RPI3_MBOX_OFFSET) -/* VideoCore -> ARM */ -#define RPI3_MBOX0_READ_OFFSET ULL(0x00000000) -#define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010) -#define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014) -#define RPI3_MBOX0_STATUS_OFFSET ULL(0x00000018) -#define RPI3_MBOX0_CONFIG_OFFSET ULL(0x0000001C) -/* ARM -> VideoCore */ -#define RPI3_MBOX1_WRITE_OFFSET ULL(0x00000020) -#define RPI3_MBOX1_PEEK_OFFSET ULL(0x00000030) -#define RPI3_MBOX1_SENDER_OFFSET ULL(0x00000034) -#define RPI3_MBOX1_STATUS_OFFSET ULL(0x00000038) -#define RPI3_MBOX1_CONFIG_OFFSET ULL(0x0000003C) -/* Mailbox status constants */ -#define RPI3_MBOX_STATUS_FULL_MASK U(0x80000000) /* Set if full */ -#define RPI3_MBOX_STATUS_EMPTY_MASK U(0x40000000) /* Set if empty */ - -/* - * Power management, reset controller, watchdog. - */ -#define RPI3_IO_PM_OFFSET ULL(0x00100000) -#define RPI3_PM_BASE (RPI3_IO_BASE + RPI3_IO_PM_OFFSET) -/* Registers on top of RPI3_PM_BASE. */ -#define RPI3_PM_RSTC_OFFSET ULL(0x0000001C) -#define RPI3_PM_RSTS_OFFSET ULL(0x00000020) -#define RPI3_PM_WDOG_OFFSET ULL(0x00000024) -/* Watchdog constants */ -#define RPI3_PM_PASSWORD U(0x5A000000) -#define RPI3_PM_RSTC_WRCFG_MASK U(0x00000030) -#define RPI3_PM_RSTC_WRCFG_FULL_RESET U(0x00000020) -/* - * The RSTS register is used by the VideoCore firmware when booting the - * Raspberry Pi to know which partition to boot from. The partition value is - * formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware - * to indicate halt. - */ -#define RPI3_PM_RSTS_WRCFG_HALT U(0x00000555) - -/* - * Hardware random number generator. - */ -#define RPI3_IO_RNG_OFFSET ULL(0x00104000) -#define RPI3_RNG_BASE (RPI3_IO_BASE + RPI3_IO_RNG_OFFSET) -#define RPI3_RNG_CTRL_OFFSET ULL(0x00000000) -#define RPI3_RNG_STATUS_OFFSET ULL(0x00000004) -#define RPI3_RNG_DATA_OFFSET ULL(0x00000008) -#define RPI3_RNG_INT_MASK_OFFSET ULL(0x00000010) -/* Enable/disable RNG */ -#define RPI3_RNG_CTRL_ENABLE U(0x1) -#define RPI3_RNG_CTRL_DISABLE U(0x0) -/* Number of currently available words */ -#define RPI3_RNG_STATUS_NUM_WORDS_SHIFT U(24) -#define RPI3_RNG_STATUS_NUM_WORDS_MASK U(0xFF) -/* Value to mask interrupts caused by the RNG */ -#define RPI3_RNG_INT_MASK_DISABLE U(0x1) - -/* - * Serial port (called 'Mini UART' in the BCM docucmentation). - */ -#define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040) -#define RPI3_MINI_UART_BASE (RPI3_IO_BASE + RPI3_IO_MINI_UART_OFFSET) -#define RPI3_MINI_UART_CLK_IN_HZ ULL(500000000) - -/* - * GPIO controller - */ -#define RPI3_IO_GPIO_OFFSET ULL(0x00200000) -#define RPI3_GPIO_BASE (RPI3_IO_BASE + RPI3_IO_GPIO_OFFSET) - -/* - * SDHost controller - */ -#define RPI3_IO_SDHOST_OFFSET ULL(0x00202000) -#define RPI3_SDHOST_BASE (RPI3_IO_BASE + RPI3_IO_SDHOST_OFFSET) - -/* - * Local interrupt controller - */ -#define RPI3_INTC_BASE_ADDRESS ULL(0x40000000) -/* Registers on top of RPI3_INTC_BASE_ADDRESS */ -#define RPI3_INTC_CONTROL_OFFSET ULL(0x00000000) -#define RPI3_INTC_PRESCALER_OFFSET ULL(0x00000008) -#define RPI3_INTC_MBOX_CONTROL_OFFSET ULL(0x00000050) -#define RPI3_INTC_MBOX_CONTROL_SLOT3_FIQ ULL(0x00000080) -#define RPI3_INTC_PENDING_FIQ_OFFSET ULL(0x00000070) -#define RPI3_INTC_PENDING_FIQ_MBOX3 ULL(0x00000080) - -#endif /* RPI3_HW_H */ diff --git a/plat/rpi/rpi3/rpi3_mbox.c b/plat/rpi/rpi3/rpi3_mbox.c deleted file mode 100644 index 2db605e..0000000 --- a/plat/rpi/rpi3/rpi3_mbox.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include -#include -#include - -#include "rpi3_hw.h" - -/* This struct must be aligned to 16 bytes */ -typedef struct __packed __aligned(16) rpi3_mbox_request { - uint32_t size; /* Buffer size in bytes */ - uint32_t code; /* Request/response code */ - uint32_t tags[0]; -} rpi3_mbox_request_t; - -#define RPI3_MBOX_BUFFER_SIZE U(256) -static uint8_t __aligned(16) rpi3_mbox_buffer[RPI3_MBOX_BUFFER_SIZE]; - -/* Constants to perform a request/check the status of a request. */ -#define RPI3_MBOX_PROCESS_REQUEST U(0x00000000) -#define RPI3_MBOX_REQUEST_SUCCESSFUL U(0x80000000) -#define RPI3_MBOX_REQUEST_ERROR U(0x80000001) - -/* Command constants */ -#define RPI3_TAG_HARDWARE_GET_BOARD_REVISION U(0x00010002) -#define RPI3_TAG_END U(0x00000000) - -#define RPI3_TAG_REQUEST U(0x00000000) -#define RPI3_TAG_IS_RESPONSE U(0x80000000) /* Set if response */ -#define RPI3_TAG_RESPONSE_LENGTH_MASK U(0x7FFFFFFF) - -#define RPI3_CHANNEL_ARM_TO_VC U(0x8) -#define RPI3_CHANNEL_MASK U(0xF) - -#define RPI3_MAILBOX_MAX_RETRIES U(1000000) - -/******************************************************************************* - * Helpers to send requests to the VideoCore using the mailboxes. - ******************************************************************************/ -static void rpi3_vc_mailbox_request_send(void) -{ - uint32_t st, data; - uintptr_t resp_addr, addr; - unsigned int retries; - - /* This is the location of the request buffer */ - addr = (uintptr_t) &rpi3_mbox_buffer; - - /* Make sure that the changes are seen by the VideoCore */ - flush_dcache_range(addr, RPI3_MBOX_BUFFER_SIZE); - - /* Wait until the outbound mailbox is empty */ - retries = 0U; - - do { - st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX1_STATUS_OFFSET); - - retries++; - if (retries == RPI3_MAILBOX_MAX_RETRIES) { - ERROR("rpi3: mbox: Send request timeout\n"); - return; - } - - } while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) == 0U); - - /* Send base address of this message to start request */ - mmio_write_32(RPI3_MBOX_BASE + RPI3_MBOX1_WRITE_OFFSET, - RPI3_CHANNEL_ARM_TO_VC | (uint32_t) addr); - - /* Wait until the inbound mailbox isn't empty */ - retries = 0U; - - do { - st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_STATUS_OFFSET); - - retries++; - if (retries == RPI3_MAILBOX_MAX_RETRIES) { - ERROR("rpi3: mbox: Receive response timeout\n"); - return; - } - - } while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) != 0U); - - /* Get location and channel */ - data = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_READ_OFFSET); - - if ((data & RPI3_CHANNEL_MASK) != RPI3_CHANNEL_ARM_TO_VC) { - ERROR("rpi3: mbox: Wrong channel: 0x%08x\n", data); - panic(); - } - - resp_addr = (uintptr_t)(data & ~RPI3_CHANNEL_MASK); - if (addr != resp_addr) { - ERROR("rpi3: mbox: Unexpected address: 0x%08x\n", data); - panic(); - } - - /* Make sure that the data seen by the CPU is up to date */ - inv_dcache_range(addr, RPI3_MBOX_BUFFER_SIZE); -} - -/******************************************************************************* - * Request board revision. Returns the revision and 0 on success, -1 on error. - ******************************************************************************/ -int rpi3_vc_hardware_get_board_revision(uint32_t *revision) -{ - uint32_t tag_request_size = sizeof(uint32_t); - rpi3_mbox_request_t *req = (rpi3_mbox_request_t *) rpi3_mbox_buffer; - - assert(revision != NULL); - - VERBOSE("rpi3: mbox: Sending request at %p\n", (void *)req); - - req->size = sizeof(rpi3_mbox_buffer); - req->code = RPI3_MBOX_PROCESS_REQUEST; - - req->tags[0] = RPI3_TAG_HARDWARE_GET_BOARD_REVISION; - req->tags[1] = tag_request_size; /* Space available for the response */ - req->tags[2] = RPI3_TAG_REQUEST; - req->tags[3] = 0; /* Placeholder for the response */ - - req->tags[4] = RPI3_TAG_END; - - rpi3_vc_mailbox_request_send(); - - if (req->code != RPI3_MBOX_REQUEST_SUCCESSFUL) { - ERROR("rpi3: mbox: Code = 0x%08x\n", req->code); - return -1; - } - - if (req->tags[2] != (RPI3_TAG_IS_RESPONSE | tag_request_size)) { - ERROR("rpi3: mbox: get board revision failed (0x%08x)\n", - req->tags[2]); - return -1; - } - - *revision = req->tags[3]; - - return 0; -} diff --git a/plat/rpi/rpi3/rpi3_pm.c b/plat/rpi/rpi3/rpi3_pm.c index 4f586b5..b79e273 100644 --- a/plat/rpi/rpi3/rpi3_pm.c +++ b/plat/rpi/rpi3/rpi3_pm.c @@ -15,7 +15,7 @@ #include #include -#include "rpi3_hw.h" +#include /* Make composite power state parameter till power level 0 */ #if PSCI_EXTENDED_STATE_ID diff --git a/plat/rpi/rpi3/rpi3_private.h b/plat/rpi/rpi3/rpi3_private.h index 53078f8..b01c40c 100644 --- a/plat/rpi/rpi3/rpi3_private.h +++ b/plat/rpi/rpi3/rpi3_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -33,9 +33,6 @@ /* IO storage utility functions */ void plat_rpi3_io_setup(void); -/* Hardware RNG functions */ -void rpi3_rng_read(void *buf, size_t len); - /* VideoCore firmware commands */ int rpi3_vc_hardware_get_board_revision(uint32_t *revision); diff --git a/plat/rpi/rpi3/rpi3_rng.c b/plat/rpi/rpi3/rpi3_rng.c deleted file mode 100644 index fd69adb..0000000 --- a/plat/rpi/rpi3/rpi3_rng.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include - -#include "rpi3_hw.h" - -/* Initial amount of values to discard */ -#define RNG_WARMUP_COUNT U(0x40000) - -static void rpi3_rng_initialize(void) -{ - uint32_t int_mask, ctrl; - - /* Return if it is already enabled */ - ctrl = mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_CTRL_OFFSET); - if ((ctrl & RPI3_RNG_CTRL_ENABLE) != 0U) { - return; - } - - /* Mask interrupts */ - int_mask = mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_INT_MASK_OFFSET); - int_mask |= RPI3_RNG_INT_MASK_DISABLE; - mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_INT_MASK_OFFSET, int_mask); - - /* Discard several values when initializing to give it time to warmup */ - mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_STATUS_OFFSET, RNG_WARMUP_COUNT); - - mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_CTRL_OFFSET, - RPI3_RNG_CTRL_ENABLE); -} - -static uint32_t rpi3_rng_get_word(void) -{ - size_t nwords; - - do { - /* Get number of available words to read */ - nwords = (mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_STATUS_OFFSET) - >> RPI3_RNG_STATUS_NUM_WORDS_SHIFT) - & RPI3_RNG_STATUS_NUM_WORDS_MASK; - } while (nwords == 0U); - - return mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_DATA_OFFSET); -} - -void rpi3_rng_read(void *buf, size_t len) -{ - uint32_t data; - size_t left = len; - uint32_t *dst = buf; - - assert(buf != NULL); - assert(len != 0U); - assert(check_uptr_overflow((uintptr_t) buf, (uintptr_t) len) == 0); - - rpi3_rng_initialize(); - - while (left >= sizeof(uint32_t)) { - data = rpi3_rng_get_word(); - *dst++ = data; - left -= sizeof(uint32_t); - } - - if (left > 0U) { - data = rpi3_rng_get_word(); - memcpy(dst, &data, left); - } -} diff --git a/plat/rpi/rpi3/rpi_mbox_board.c b/plat/rpi/rpi3/rpi_mbox_board.c new file mode 100644 index 0000000..e7c1e2b --- /dev/null +++ b/plat/rpi/rpi3/rpi_mbox_board.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +#include + +#define RPI3_MBOX_BUFFER_SIZE U(256) +static uint8_t __aligned(16) rpi3_mbox_buffer[RPI3_MBOX_BUFFER_SIZE]; + +/******************************************************************************* + * Request board revision. Returns the revision and 0 on success, -1 on error. + ******************************************************************************/ +int rpi3_vc_hardware_get_board_revision(uint32_t *revision) +{ + uint32_t tag_request_size = sizeof(uint32_t); + rpi3_mbox_request_t *req = (rpi3_mbox_request_t *) rpi3_mbox_buffer; + + assert(revision != NULL); + + VERBOSE("rpi3: mbox: Sending request at %p\n", (void *)req); + + req->size = sizeof(rpi3_mbox_buffer); + req->code = RPI3_MBOX_PROCESS_REQUEST; + + req->tags[0] = RPI3_TAG_HARDWARE_GET_BOARD_REVISION; + req->tags[1] = tag_request_size; /* Space available for the response */ + req->tags[2] = RPI3_TAG_REQUEST; + req->tags[3] = 0; /* Placeholder for the response */ + + req->tags[4] = RPI3_TAG_END; + + rpi3_vc_mailbox_request_send(req, RPI3_MBOX_BUFFER_SIZE); + + if (req->code != RPI3_MBOX_REQUEST_SUCCESSFUL) { + ERROR("rpi3: mbox: Code = 0x%08x\n", req->code); + return -1; + } + + if (req->tags[2] != (RPI3_TAG_IS_RESPONSE | tag_request_size)) { + ERROR("rpi3: mbox: get board revision failed (0x%08x)\n", + req->tags[2]); + return -1; + } + + *revision = req->tags[3]; + + return 0; +}