diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 7385b5d..397013e 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __ARCH_H__ -#define __ARCH_H__ +#ifndef ARCH_H +#define ARCH_H #include @@ -37,10 +37,10 @@ #define MPIDR_AFF3_SHIFT U(32) #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) #define MPIDR_AFFLVL_SHIFT U(3) -#define MPIDR_AFFLVL0 ULL(0x0) -#define MPIDR_AFFLVL1 ULL(0x1) -#define MPIDR_AFFLVL2 ULL(0x2) -#define MPIDR_AFFLVL3 ULL(0x3) +#define MPIDR_AFFLVL0 U(0x0) +#define MPIDR_AFFLVL1 U(0x1) +#define MPIDR_AFFLVL2 U(0x2) +#define MPIDR_AFFLVL3 U(0x3) #define MPIDR_AFFLVL0_VAL(mpidr) \ (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) #define MPIDR_AFFLVL1_VAL(mpidr) \ @@ -739,4 +739,4 @@ #define ERXMISC0_EL1 S3_0_C5_C4_4 #define ERXMISC1_EL1 S3_0_C5_C4_5 -#endif /* __ARCH_H__ */ +#endif /* ARCH_H */ diff --git a/include/lib/psci/psci.h b/include/lib/psci/psci.h index 1aa9633..f2ee62e 100644 --- a/include/lib/psci/psci.h +++ b/include/lib/psci/psci.h @@ -22,14 +22,14 @@ #ifdef PLAT_NUM_PWR_DOMAINS #define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS #else -#define PSCI_NUM_PWR_DOMAINS (U(2) * PLATFORM_CORE_COUNT) +#define PSCI_NUM_PWR_DOMAINS (2 * PLATFORM_CORE_COUNT) #endif #define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \ PLATFORM_CORE_COUNT) /* This is the power level corresponding to a CPU */ -#define PSCI_CPU_PWR_LVL (0) +#define PSCI_CPU_PWR_LVL U(0) /* * The maximum power level supported by PSCI. Since PSCI CPU_SUSPEND @@ -89,9 +89,9 @@ /******************************************************************************* * PSCI Migrate and friends ******************************************************************************/ -#define PSCI_TOS_UP_MIG_CAP U(0) -#define PSCI_TOS_NOT_UP_MIG_CAP U(1) -#define PSCI_TOS_NOT_PRESENT_MP U(2) +#define PSCI_TOS_UP_MIG_CAP 0 +#define PSCI_TOS_NOT_UP_MIG_CAP 1 +#define PSCI_TOS_NOT_PRESENT_MP 2 /******************************************************************************* * PSCI CPU_SUSPEND 'power_state' parameter specific defines @@ -163,10 +163,10 @@ /* * SYSTEM_RESET2 macros */ -#define PSCI_RESET2_TYPE_VENDOR_SHIFT 31 -#define PSCI_RESET2_TYPE_VENDOR (1U << PSCI_RESET2_TYPE_VENDOR_SHIFT) -#define PSCI_RESET2_TYPE_ARCH (0U << PSCI_RESET2_TYPE_VENDOR_SHIFT) -#define PSCI_RESET2_SYSTEM_WARM_RESET (PSCI_RESET2_TYPE_ARCH | 0) +#define PSCI_RESET2_TYPE_VENDOR_SHIFT U(31) +#define PSCI_RESET2_TYPE_VENDOR (U(1) << PSCI_RESET2_TYPE_VENDOR_SHIFT) +#define PSCI_RESET2_TYPE_ARCH (U(0) << PSCI_RESET2_TYPE_VENDOR_SHIFT) +#define PSCI_RESET2_SYSTEM_WARM_RESET (PSCI_RESET2_TYPE_ARCH | U(0)) #ifndef __ASSEMBLY__ @@ -214,11 +214,9 @@ * specified CPU. The definitions of these states can be found in Section 5.15.3 * of PSCI specification (ARM DEN 0022C). */ -typedef enum { - HW_ON = U(0), - HW_OFF = U(1), - HW_STANDBY = U(2) -} node_hw_state_t; +#define HW_ON 0 +#define HW_OFF 1 +#define HW_STANDBY 2 /* * Macro to represent invalid affinity level within PSCI. @@ -231,7 +229,7 @@ typedef uint8_t plat_local_state_t; /* The local state macro used to represent RUN state. */ -#define PSCI_LOCAL_STATE_RUN U(0) +#define PSCI_LOCAL_STATE_RUN U(0) /* * Function to test whether the plat_local_state is RUN state @@ -288,7 +286,7 @@ * Highest power level which takes part in a power management * operation. */ - unsigned char target_pwrlvl; + unsigned int target_pwrlvl; /* The local power state of this CPU */ plat_local_state_t local_state; diff --git a/include/lib/psci/psci_compat.h b/include/lib/psci/psci_compat.h index 65ac15f..11ed16d 100644 --- a/include/lib/psci/psci_compat.h +++ b/include/lib/psci/psci_compat.h @@ -1,14 +1,15 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __PSCI_COMPAT_H__ -#define __PSCI_COMPAT_H__ +#ifndef PSCI_COMPAT_H +#define PSCI_COMPAT_H #include #include +#include #ifndef __ASSEMBLY__ /* @@ -25,10 +26,10 @@ #define PSCI_AFF_ABSENT 0x0 #define PSCI_AFF_PRESENT 0x1 -#define PSCI_STATE_ON 0x0 -#define PSCI_STATE_OFF 0x1 -#define PSCI_STATE_ON_PENDING 0x2 -#define PSCI_STATE_SUSPEND 0x3 +#define PSCI_STATE_ON U(0x0) +#define PSCI_STATE_OFF U(0x1) +#define PSCI_STATE_ON_PENDING U(0x2) +#define PSCI_STATE_SUSPEND U(0x3) /* * Using the compatibility platform interfaces means that the local states @@ -38,8 +39,8 @@ * involved. Hence if we assume 3 generic states viz, run, standby and * power down, we can assign 1 and 2 to standby and power down respectively. */ -#define PLAT_MAX_RET_STATE 1 -#define PLAT_MAX_OFF_STATE 2 +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) /* * Macro to represent invalid affinity level within PSCI. @@ -89,4 +90,4 @@ int psci_get_suspend_afflvl(void); #endif /* ____ASSEMBLY__ */ -#endif /* __PSCI_COMPAT_H__ */ +#endif /* PSCI_COMPAT_H */ diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index e3d0edb..98f96f2 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __ARM_DEF_H__ -#define __ARM_DEF_H__ +#ifndef ARM_DEF_H +#define ARM_DEF_H #include #include @@ -40,12 +40,12 @@ * within the power-state parameter. */ /* Local power state for power domains in Run state. */ -#define ARM_LOCAL_STATE_RUN 0 +#define ARM_LOCAL_STATE_RUN U(0) /* Local power state for retention. Valid only for CPU power domains */ -#define ARM_LOCAL_STATE_RET 1 +#define ARM_LOCAL_STATE_RET U(1) /* Local power state for OFF/power-down. Valid for CPU and cluster power domains */ -#define ARM_LOCAL_STATE_OFF 2 +#define ARM_LOCAL_STATE_OFF U(2) /* Memory location options for TSP */ #define ARM_TRUSTED_SRAM_ID 0 @@ -509,4 +509,4 @@ SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) -#endif /* __ARM_DEF_H__ */ +#endif /* ARM_DEF_H */ diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h index eb0605e..7eb2fc0 100644 --- a/lib/psci/psci_private.h +++ b/lib/psci/psci_private.h @@ -111,7 +111,7 @@ * Index of the first CPU power domain node level 0 which has this node * as its parent. */ - unsigned int cpu_start_idx; + int cpu_start_idx; /* * Number of CPU power domains which are siblings of the domain indexed diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h index d039188..b46d410 100644 --- a/plat/allwinner/common/include/platform_def.h +++ b/plat/allwinner/common/include/platform_def.h @@ -4,12 +4,13 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __PLATFORM_DEF_H__ -#define __PLATFORM_DEF_H__ +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H #include #include #include +#include #define BL31_BASE SUNXI_SRAM_A2_BASE #define BL31_LIMIT (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE) @@ -23,11 +24,11 @@ #define MAX_MMAP_REGIONS (4 + PLATFORM_MMAP_REGIONS) #define MAX_XLAT_TABLES 2 -#define PLAT_MAX_PWR_LVL_STATES 2 -#define PLAT_MAX_RET_STATE 1 -#define PLAT_MAX_OFF_STATE 2 +#define PLAT_MAX_PWR_LVL_STATES U(2) +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) -#define PLAT_MAX_PWR_LVL 2 +#define PLAT_MAX_PWR_LVL U(2) #define PLAT_NUM_PWR_DOMAINS (1 + \ PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) @@ -48,4 +49,4 @@ #endif #endif -#endif /* __PLATFORM_DEF_H__ */ +#endif /* PLATFORM_DEF_H */ diff --git a/plat/arm/board/fvp/fvp_def.h b/plat/arm/board/fvp/fvp_def.h index acf3cf4..4e20c31 100644 --- a/plat/arm/board/fvp/fvp_def.h +++ b/plat/arm/board/fvp/fvp_def.h @@ -4,8 +4,10 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __FVP_DEF_H__ -#define __FVP_DEF_H__ +#ifndef FVP_DEF_H +#define FVP_DEF_H + +#include #ifndef FVP_CLUSTER_COUNT #define FVP_CLUSTER_COUNT 2 @@ -153,4 +155,4 @@ #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) -#endif /* __FVP_DEF_H__ */ +#endif /* FVP_DEF_H */ diff --git a/plat/arm/board/juno/juno_def.h b/plat/arm/board/juno/juno_def.h index 63e2456..95f2b39 100644 --- a/plat/arm/board/juno/juno_def.h +++ b/plat/arm/board/juno/juno_def.h @@ -1,12 +1,13 @@ /* - * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __JUNO_DEF_H__ -#define __JUNO_DEF_H__ +#ifndef JUNO_DEF_H +#define JUNO_DEF_H +#include /******************************************************************************* * Juno memory map related constants @@ -90,4 +91,4 @@ #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) -#endif /* __JUNO_DEF_H__ */ +#endif /* JUNO_DEF_H */ diff --git a/plat/arm/css/sgi/include/platform_def.h b/plat/arm/css/sgi/include/platform_def.h index 84ef2c4..7a2a6bd 100644 --- a/plat/arm/css/sgi/include/platform_def.h +++ b/plat/arm/css/sgi/include/platform_def.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __PLATFORM_DEF_H__ -#define __PLATFORM_DEF_H__ +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H #include #include @@ -13,6 +13,7 @@ #include #include #include +#include #define CSS_SGI_MAX_CPUS_PER_CLUSTER 4 @@ -57,7 +58,7 @@ #define PLAT_ARM_NSRAM_BASE 0x06000000 #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ -#define PLAT_MAX_PWR_LVL 1 +#define PLAT_MAX_PWR_LVL U(1) #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ CSS_IRQ_MHU @@ -108,4 +109,4 @@ V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) -#endif /* __PLATFORM_DEF_H__ */ +#endif /* PLATFORM_DEF_H */ diff --git a/plat/common/plat_psci_common.c b/plat/common/plat_psci_common.c index 0e818d0..6c5cd55 100644 --- a/plat/common/plat_psci_common.c +++ b/plat/common/plat_psci_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,7 +16,7 @@ #pragma weak plat_psci_stat_get_residency /* Ticks elapsed in one second by a signal of 1 MHz */ -#define MHZ_TICKS_PER_SEC 1000000 +#define MHZ_TICKS_PER_SEC 1000000U /* Maximum time-stamp value read from architectural counters */ #ifdef AARCH32 @@ -49,7 +49,7 @@ * convert time-stamp into microseconds. */ residency_div = read_cntfrq_el0() / MHZ_TICKS_PER_SEC; - assert(residency_div); + assert(residency_div > 0U); if (pwrupts < pwrdnts) res = MAX_TS - pwrdnts + pwrupts; diff --git a/plat/hisilicon/hikey/include/platform_def.h b/plat/hisilicon/hikey/include/platform_def.h index b240448..54be978 100644 --- a/plat/hisilicon/hikey/include/platform_def.h +++ b/plat/hisilicon/hikey/include/platform_def.h @@ -4,14 +4,15 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __PLATFORM_DEF_H__ -#define __PLATFORM_DEF_H__ +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H #include #include #include #include /* BL memory region sizes, etc */ #include +#include /* Special value used to verify platform parameters from BL2 to BL3-1 */ #define HIKEY_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL @@ -34,8 +35,8 @@ #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ PLATFORM_CLUSTER_COUNT + 1) -#define PLAT_MAX_RET_STATE 1 -#define PLAT_MAX_OFF_STATE 2 +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) #define MAX_IO_DEVICES 3 #define MAX_IO_HANDLES 4 @@ -79,4 +80,4 @@ #define CACHE_WRITEBACK_SHIFT 6 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) -#endif /* __PLATFORM_DEF_H__ */ +#endif /* PLATFORM_DEF_H */ diff --git a/plat/hisilicon/hikey960/include/platform_def.h b/plat/hisilicon/hikey960/include/platform_def.h index beff47c..5a6021a 100644 --- a/plat/hisilicon/hikey960/include/platform_def.h +++ b/plat/hisilicon/hikey960/include/platform_def.h @@ -4,10 +4,11 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __PLATFORM_DEF_H__ -#define __PLATFORM_DEF_H__ +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H #include +#include #include "../hikey960_def.h" /* Special value used to verify platform parameters from BL2 to BL3-1 */ @@ -31,8 +32,8 @@ #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ PLATFORM_CLUSTER_COUNT + 1) -#define PLAT_MAX_RET_STATE 1 -#define PLAT_MAX_OFF_STATE 2 +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) #define MAX_IO_DEVICES 3 #define MAX_IO_HANDLES 4 @@ -140,4 +141,4 @@ #define CACHE_WRITEBACK_SHIFT 6 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) -#endif /* __PLATFORM_DEF_H__ */ +#endif /* PLATFORM_DEF_H */ diff --git a/plat/hisilicon/poplar/include/platform_def.h b/plat/hisilicon/poplar/include/platform_def.h index 8e8f009..824ca34 100644 --- a/plat/hisilicon/poplar/include/platform_def.h +++ b/plat/hisilicon/poplar/include/platform_def.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __PLATFORM_DEF_H__ -#define __PLATFORM_DEF_H__ +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H #include #include @@ -131,8 +131,8 @@ /* Power states */ #define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL1) -#define PLAT_MAX_OFF_STATE 2 -#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_OFF_STATE U(2) +#define PLAT_MAX_RET_STATE U(1) /* Interrupt controller */ #define PLAT_ARM_GICD_BASE GICD_BASE @@ -168,4 +168,4 @@ #define PLAT_ARM_G0_IRQ_PROPS(grp) -#endif /* __PLATFORM_DEF_H__ */ +#endif /* PLATFORM_DEF_H */ diff --git a/plat/imx/imx8qm/include/platform_def.h b/plat/imx/imx8qm/include/platform_def.h index 51c2e1e..1cf7511 100644 --- a/plat/imx/imx8qm/include/platform_def.h +++ b/plat/imx/imx8qm/include/platform_def.h @@ -4,6 +4,11 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include + #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" #define PLATFORM_LINKER_ARCH aarch64 @@ -22,10 +27,10 @@ #define IMX_PWR_LVL1 MPIDR_AFFLVL1 #define IMX_PWR_LVL2 MPIDR_AFFLVL2 -#define PWR_DOMAIN_AT_MAX_LVL 1 -#define PLAT_MAX_PWR_LVL 2 -#define PLAT_MAX_OFF_STATE 2 -#define PLAT_MAX_RET_STATE 1 +#define PWR_DOMAIN_AT_MAX_LVL U(1) +#define PLAT_MAX_PWR_LVL U(2) +#define PLAT_MAX_OFF_STATE U(2) +#define PLAT_MAX_RET_STATE U(1) #define BL31_BASE 0x80000000 #define BL31_LIMIT 0x80020000 @@ -62,3 +67,5 @@ #define DEBUG_CONSOLE 0 #define DEBUG_CONSOLE_A53 0 #define PLAT_IMX8QM 1 + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/imx/imx8qx/include/platform_def.h b/plat/imx/imx8qx/include/platform_def.h index 8c86174..b9fd96c 100644 --- a/plat/imx/imx8qx/include/platform_def.h +++ b/plat/imx/imx8qx/include/platform_def.h @@ -4,8 +4,10 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __PLATFORM_DEF_H__ -#define __PLATFORM_DEF_H__ +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" #define PLATFORM_LINKER_ARCH aarch64 @@ -20,10 +22,10 @@ #define PLATFORM_CLUSTER0_CORE_COUNT 4 #define PLATFORM_CLUSTER1_CORE_COUNT 0 -#define PWR_DOMAIN_AT_MAX_LVL 1 -#define PLAT_MAX_PWR_LVL 2 -#define PLAT_MAX_OFF_STATE 2 -#define PLAT_MAX_RET_STATE 1 +#define PWR_DOMAIN_AT_MAX_LVL U(1) +#define PLAT_MAX_PWR_LVL U(2) +#define PLAT_MAX_OFF_STATE U(2) +#define PLAT_MAX_RET_STATE U(1) #define BL31_BASE 0x80000000 #define BL31_LIMIT 0x80020000 @@ -57,4 +59,4 @@ #define DEBUG_CONSOLE_A35 0 #define PLAT_IMX8QX 1 -#endif /* __PLATFORM_DEF_H__ */ +#endif /* PLATFORM_DEF_H */ diff --git a/plat/layerscape/board/ls1043/include/ls_def.h b/plat/layerscape/board/ls1043/include/ls_def.h index 1015129..9c83720 100644 --- a/plat/layerscape/board/ls1043/include/ls_def.h +++ b/plat/layerscape/board/ls1043/include/ls_def.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __LS_DEF_H__ -#define __LS_DEF_H__ +#ifndef LS_DEF_H +#define LS_DEF_H #include #include @@ -36,14 +36,14 @@ * within the power-state parameter. */ /* Local power state for power domains in Run state. */ -#define LS_LOCAL_STATE_RUN 0 +#define LS_LOCAL_STATE_RUN U(0) /* Local power state for retention. Valid only for CPU power domains */ -#define LS_LOCAL_STATE_RET 1 +#define LS_LOCAL_STATE_RET U(1) /* * Local power state for OFF/power-down. Valid for CPU and cluster power * domains */ -#define LS_LOCAL_STATE_OFF 2 +#define LS_LOCAL_STATE_OFF U(2) #define LS_MAP_NS_DRAM MAP_REGION_FLAT( \ (LS_NS_DRAM_BASE), \ @@ -104,4 +104,4 @@ */ #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) -#endif /* __LS_DEF_H__ */ +#endif /* LS_DEF_H */ diff --git a/plat/layerscape/board/ls1043/include/platform_def.h b/plat/layerscape/board/ls1043/include/platform_def.h index 0e1cae6..46b2031 100644 --- a/plat/layerscape/board/ls1043/include/platform_def.h +++ b/plat/layerscape/board/ls1043/include/platform_def.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __PLATFORM_DEF_H__ -#define __PLATFORM_DEF_H__ +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H #include #include @@ -209,4 +209,4 @@ #define MAX_IO_DEVICES 3 #define MAX_IO_HANDLES 4 -#endif /* __PLATFORM_DEF_H__ */ +#endif /* PLATFORM_DEF_H */ diff --git a/plat/mediatek/mt6795/include/platform_def.h b/plat/mediatek/mt6795/include/platform_def.h index 6c64ba5..0fa63a1 100644 --- a/plat/mediatek/mt6795/include/platform_def.h +++ b/plat/mediatek/mt6795/include/platform_def.h @@ -1,11 +1,13 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __PLATFORM_DEF_H__ -#define __PLATFORM_DEF_H__ +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include #define PLAT_PRIMARY_CPU 0x0 @@ -146,7 +148,7 @@ #if ENABLE_PLAT_COMPAT #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 #else -#define PLAT_MAX_PWR_LVL 2 /* MPIDR_AFFLVL2 */ +#define PLAT_MAX_PWR_LVL U(2) /* MPIDR_AFFLVL2 */ #endif #define PLATFORM_CACHE_LINE_SIZE 64 @@ -239,4 +241,4 @@ #define PAGE_SIZE_2MB (1 << PAGE_SIZE_2MB_SHIFT) #define PAGE_SIZE_2MB_SHIFT TWO_MB_SHIFT -#endif /* __PLATFORM_DEF_H__ */ +#endif /* PLATFORM_DEF_H */ diff --git a/plat/mediatek/mt8173/include/platform_def.h b/plat/mediatek/mt8173/include/platform_def.h index 5e79df2..6e3f4a3 100644 --- a/plat/mediatek/mt8173/include/platform_def.h +++ b/plat/mediatek/mt8173/include/platform_def.h @@ -1,17 +1,17 @@ /* - * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __PLATFORM_DEF_H__ -#define __PLATFORM_DEF_H__ +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H #include #include +#include #include "mt8173_def.h" - /******************************************************************************* * Platform binary types for linking ******************************************************************************/ @@ -37,9 +37,9 @@ #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 #if !ENABLE_PLAT_COMPAT -#define PLAT_MAX_PWR_LVL 2 -#define PLAT_MAX_RET_STATE 1 -#define PLAT_MAX_OFF_STATE 2 +#define PLAT_MAX_PWR_LVL U(2) +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) #endif #define PLATFORM_SYSTEM_COUNT 1 #define PLATFORM_CLUSTER_COUNT 2 @@ -137,4 +137,4 @@ #define PLAT_ARM_G0_IRQ_PROPS(grp) -#endif /* __PLATFORM_DEF_H__ */ +#endif /* PLATFORM_DEF_H */ diff --git a/plat/qemu/include/platform_def.h b/plat/qemu/include/platform_def.h index 2f2ca6f..55252c3 100644 --- a/plat/qemu/include/platform_def.h +++ b/plat/qemu/include/platform_def.h @@ -1,15 +1,16 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __PLATFORM_DEF_H__ -#define __PLATFORM_DEF_H__ +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H #include #include #include +#include /* Special value used to verify platform parameters from BL2 to BL3-1 */ #define QEMU_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL @@ -36,13 +37,13 @@ PLATFORM_CORE_COUNT) #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 -#define PLAT_MAX_RET_STATE 1 -#define PLAT_MAX_OFF_STATE 2 +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) /* Local power state for power domains in Run state. */ -#define PLAT_LOCAL_STATE_RUN 0 +#define PLAT_LOCAL_STATE_RUN U(0) /* Local power state for retention. Valid only for CPU power domains */ -#define PLAT_LOCAL_STATE_RET 1 +#define PLAT_LOCAL_STATE_RET U(1) /* * Local power state for OFF/power-down. Valid for CPU and cluster power * domains. @@ -229,4 +230,4 @@ */ #define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16) -#endif /* __PLATFORM_DEF_H__ */ +#endif /* PLATFORM_DEF_H */ diff --git a/plat/rockchip/rk3328/include/platform_def.h b/plat/rockchip/rk3328/include/platform_def.h index 019f4e1..56d51ee 100644 --- a/plat/rockchip/rk3328/include/platform_def.h +++ b/plat/rockchip/rk3328/include/platform_def.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __PLATFORM_DEF_H__ -#define __PLATFORM_DEF_H__ +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H #include #include @@ -58,13 +58,13 @@ * This macro defines the deepest retention state possible. A higher state * id will represent an invalid or a power down state. */ -#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_RET_STATE U(1) /* * This macro defines the deepest power down states possible. Any state ID * higher than this is invalid. */ -#define PLAT_MAX_OFF_STATE 2 +#define PLAT_MAX_OFF_STATE U(2) /******************************************************************************* * Platform memory map related constants @@ -123,4 +123,4 @@ #define PSRAM_DO_DDR_RESUME 0 #define PSRAM_CHECK_WAKEUP_CPU 0 -#endif /* __PLATFORM_DEF_H__ */ +#endif /* PLATFORM_DEF_H */ diff --git a/plat/rockchip/rk3368/include/platform_def.h b/plat/rockchip/rk3368/include/platform_def.h index a61663c..d9a80a7 100644 --- a/plat/rockchip/rk3368/include/platform_def.h +++ b/plat/rockchip/rk3368/include/platform_def.h @@ -1,15 +1,16 @@ /* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __PLATFORM_DEF_H__ -#define __PLATFORM_DEF_H__ +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H #include #include #include +#include #define DEBUG_XLAT_TABLE 0 @@ -58,13 +59,13 @@ * This macro defines the deepest retention state possible. A higher state * id will represent an invalid or a power down state. */ -#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_RET_STATE U(1) /* * This macro defines the deepest power down states possible. Any state ID * higher than this is invalid. */ -#define PLAT_MAX_OFF_STATE 2 +#define PLAT_MAX_OFF_STATE U(2) /******************************************************************************* * Platform memory map related constants @@ -125,4 +126,4 @@ #define PSRAM_DO_DDR_RESUME 0 #define PSRAM_CHECK_WAKEUP_CPU 0 -#endif /* __PLATFORM_DEF_H__ */ +#endif /* PLATFORM_DEF_H */ diff --git a/plat/rockchip/rk3399/include/platform_def.h b/plat/rockchip/rk3399/include/platform_def.h index 7139b41..26204a1 100644 --- a/plat/rockchip/rk3399/include/platform_def.h +++ b/plat/rockchip/rk3399/include/platform_def.h @@ -1,16 +1,17 @@ /* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __PLATFORM_DEF_H__ -#define __PLATFORM_DEF_H__ +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H #include #include #include #include +#include #define DEBUG_XLAT_TABLE 0 @@ -57,13 +58,13 @@ * This macro defines the deepest retention state possible. A higher state * id will represent an invalid or a power down state. */ -#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_RET_STATE U(1) /* * This macro defines the deepest power down states possible. Any state ID * higher than this is invalid. */ -#define PLAT_MAX_OFF_STATE 2 +#define PLAT_MAX_OFF_STATE U(2) /******************************************************************************* * Platform specific page table and MMU setup constants @@ -110,4 +111,4 @@ #define PSRAM_DO_DDR_RESUME 1 #define PSRAM_CHECK_WAKEUP_CPU 0 -#endif /* __PLATFORM_DEF_H__ */ +#endif /* PLATFORM_DEF_H */ diff --git a/plat/socionext/synquacer/include/platform_def.h b/plat/socionext/synquacer/include/platform_def.h index 3e16642..bde7348 100644 --- a/plat/socionext/synquacer/include/platform_def.h +++ b/plat/socionext/synquacer/include/platform_def.h @@ -4,10 +4,11 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __PLATFORM_DEF_H__ -#define __PLATFORM_DEF_H__ +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H #include +#include /* CPU topology */ #define PLAT_MAX_CORES_PER_CLUSTER 2 @@ -15,9 +16,9 @@ #define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * \ PLAT_MAX_CORES_PER_CLUSTER) -#define PLAT_MAX_PWR_LVL 1 -#define PLAT_MAX_RET_STATE 1 -#define PLAT_MAX_OFF_STATE 2 +#define PLAT_MAX_PWR_LVL U(1) +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) #define SQ_LOCAL_STATE_RUN 0 #define SQ_LOCAL_STATE_RET 1 @@ -78,4 +79,4 @@ #define PLAT_SQ_GPIO_BASE 0x51000000 -#endif /* __PLATFORM_DEF_H__ */ +#endif /* PLATFORM_DEF_H */ diff --git a/plat/socionext/uniphier/include/platform_def.h b/plat/socionext/uniphier/include/platform_def.h index 301aa14..3d71db2 100644 --- a/plat/socionext/uniphier/include/platform_def.h +++ b/plat/socionext/uniphier/include/platform_def.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __PLATFORM_DEF_H__ -#define __PLATFORM_DEF_H__ +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H #include #include @@ -23,10 +23,10 @@ #define PLATFORM_CORE_COUNT \ ((UNIPHIER_MAX_CPUS_PER_CLUSTER) * (UNIPHIER_CLUSTER_COUNT)) -#define PLAT_MAX_PWR_LVL 1 +#define PLAT_MAX_PWR_LVL U(1) -#define PLAT_MAX_OFF_STATE 2 -#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_OFF_STATE U(2) +#define PLAT_MAX_RET_STATE U(1) #define BL2_BASE ULL(0x80000000) #define BL2_LIMIT ULL(0x80080000) @@ -59,4 +59,4 @@ #define TSP_SEC_MEM_SIZE ((BL32_LIMIT) - (BL32_BASE)) #define TSP_IRQ_SEC_PHY_TIMER 29 -#endif /* __PLATFORM_DEF_H__ */ +#endif /* PLATFORM_DEF_H */ diff --git a/plat/ti/k3/board/generic/include/board_def.h b/plat/ti/k3/board/generic/include/board_def.h index 4c59c75..fe0a062 100644 --- a/plat/ti/k3/board/generic/include/board_def.h +++ b/plat/ti/k3/board/generic/include/board_def.h @@ -4,8 +4,10 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __BOARD_DEF_H__ -#define __BOARD_DEF_H__ +#ifndef BOARD_DEF_H +#define BOARD_DEF_H + +#include /* The ports must be in order and contiguous */ #define K3_CLUSTER0_CORE_COUNT 2 @@ -27,7 +29,7 @@ #define SEC_SRAM_BASE 0x70000000 /* Base of MSMC SRAM */ #define SEC_SRAM_SIZE 0x00020000 /* 128k */ -#define PLAT_MAX_OFF_STATE 2 -#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_OFF_STATE U(2) +#define PLAT_MAX_RET_STATE U(1) -#endif /* __BOARD_DEF_H__ */ +#endif /* BOARD_DEF_H */ diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h index 49766cc..d721778 100644 --- a/plat/xilinx/zynqmp/include/platform_def.h +++ b/plat/xilinx/zynqmp/include/platform_def.h @@ -1,15 +1,16 @@ /* - * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __PLATFORM_DEF_H__ -#define __PLATFORM_DEF_H__ +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H #include #include #include +#include #include "../zynqmp_def.h" /******************************************************************************* @@ -21,9 +22,9 @@ #define PLATFORM_CORE_COUNT 4 #define PLAT_NUM_POWER_DOMAINS 5 -#define PLAT_MAX_PWR_LVL 1 -#define PLAT_MAX_RET_STATE 1 -#define PLAT_MAX_OFF_STATE 2 +#define PLAT_MAX_PWR_LVL U(1) +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) /******************************************************************************* * BL31 specific defines. @@ -142,4 +143,4 @@ #define PLAT_ARM_G0_IRQ_PROPS(grp) -#endif /* __PLATFORM_DEF_H__ */ +#endif /* PLATFORM_DEF_H */