diff --git a/plat/arm/board/arm_fpga/aarch64/fpga_helpers.S b/plat/arm/board/arm_fpga/aarch64/fpga_helpers.S
new file mode 100644
index 0000000..57e5320
--- /dev/null
+++ b/plat/arm/board/arm_fpga/aarch64/fpga_helpers.S
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <platform_def.h>
+
+	.globl	plat_get_my_entrypoint
+	.globl	plat_secondary_cold_boot_setup
+	.globl	plat_is_my_cpu_primary
+	.globl	platform_mem_init
+	.globl	plat_my_core_pos
+	.globl	plat_fpga_calc_core_pos
+	.globl	plat_crash_console_init
+	.globl	plat_crash_console_putc
+	.globl	plat_crash_console_flush
+
+/* -----------------------------------------------------------------------
+ * unsigned long plat_get_my_entrypoint (void);
+ * TODO: determine if warm boot should be supported for FPGA images
+ * -----------------------------------------------------------------------
+ */
+func plat_get_my_entrypoint
+	mov	x0, #0
+	ret
+endfunc plat_get_my_entrypoint
+
+/* -----------------------------------------------------------------------
+ * void plat_secondary_cold_boot_setup (void);
+ * TODO: add placeholder PSCI implementation for FPGA images
+ * -----------------------------------------------------------------------
+ */
+func plat_secondary_cold_boot_setup
+	ret
+endfunc plat_secondary_cold_boot_setup
+
+/* -----------------------------------------------------------------------
+ * unsigned int plat_is_my_cpu_primary (void);
+ *
+ * Find out whether the current cpu is the primary cpu
+ * -----------------------------------------------------------------------
+ */
+func plat_is_my_cpu_primary
+	mrs	x0, mpidr_el1
+	mov_imm	x1, MPIDR_AFFINITY_MASK
+	and	x0, x0, x1
+	cmp	x0, #FPGA_PRIMARY_CPU
+	cset	w0, eq
+	ret
+endfunc plat_is_my_cpu_primary
+
+func platform_mem_init
+	ret
+endfunc platform_mem_init
+
+func plat_my_core_pos
+	mrs	x0, mpidr_el1
+	b	plat_fpga_calc_core_pos
+endfunc plat_my_core_pos
+
+/* -----------------------------------------------------------------------
+ * unsigned int plat_fpga_calc_core_pos(u_register_t mpidr)
+ * TODO: add calculation of the core position for FPGA image CPUs
+ * -----------------------------------------------------------------------
+ */
+func plat_fpga_calc_core_pos
+	mov	x0, #0
+	ret
+endfunc plat_fpga_calc_core_pos
+
+func plat_crash_console_init
+	mov_imm	x0, PLAT_FPGA_CRASH_UART_BASE
+	mov_imm	x1, PLAT_FPGA_CRASH_UART_CLK_IN_HZ
+	mov_imm	x2, PLAT_FPGA_CONSOLE_BAUDRATE
+	b	console_pl011_core_init
+endfunc plat_crash_console_init
+
+func plat_crash_console_putc
+	mov_imm	x1, PLAT_FPGA_CRASH_UART_BASE
+	b	console_pl011_core_putc
+endfunc plat_crash_console_putc
+
+func plat_crash_console_flush
+	mov_imm	x0, PLAT_FPGA_CRASH_UART_BASE
+	b	console_pl011_core_flush
+endfunc plat_crash_console_flush
diff --git a/plat/arm/board/arm_fpga/fpga_bl31_setup.c b/plat/arm/board/arm_fpga/fpga_bl31_setup.c
new file mode 100644
index 0000000..aaa25bc
--- /dev/null
+++ b/plat/arm/board/arm_fpga/fpga_bl31_setup.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+#include "fpga_private.h"
+
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+				u_register_t arg2, u_register_t arg3)
+{
+	fpga_console_init();
+	/*
+	 * TODO: implement any extra early platform setup before jumping to BL33
+	 * payload
+	 */
+}
+
+void bl31_plat_arch_setup(void)
+{
+}
+
+void bl31_platform_setup(void)
+{
+	/* TODO: initialize GIC and timer using the specifications of the FPGA image */
+}
+
+entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
+{
+	/*
+	 * TODO: return entry_point_info_t struct containing information about the
+	 *       BL33 payload, which will run in EL2NS mode.
+	 */
+	return NULL;
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+	/*
+	 * TODO: return the frequency of the System Counter as configured by the
+	 * FPGA image
+	 */
+	return 0;
+}
+
+void bl31_plat_enable_mmu(uint32_t flags)
+{
+	/* TODO: determine if MMU needs to be enabled */
+}
diff --git a/plat/arm/board/arm_fpga/fpga_console.c b/plat/arm/board/arm_fpga/fpga_console.c
new file mode 100644
index 0000000..b4ebf34
--- /dev/null
+++ b/plat/arm/board/arm_fpga/fpga_console.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/console.h>
+#include <drivers/arm/pl011.h>
+
+#include <platform_def.h>
+
+static console_t console;
+
+void fpga_console_init(void)
+{
+	(void)console_pl011_register(PLAT_FPGA_BOOT_UART_BASE,
+		PLAT_FPGA_BOOT_UART_CLK_IN_HZ,
+		PLAT_FPGA_CONSOLE_BAUDRATE,
+		&console);
+
+	console_set_scope(&console, CONSOLE_FLAG_BOOT |
+		CONSOLE_FLAG_RUNTIME);
+}
diff --git a/plat/arm/board/arm_fpga/fpga_def.h b/plat/arm/board/arm_fpga/fpga_def.h
new file mode 100644
index 0000000..8c542e0
--- /dev/null
+++ b/plat/arm/board/arm_fpga/fpga_def.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/utils_def.h>
+
+#ifndef FPGA_DEF_H
+#define FPGA_DEF_H
+
+/*
+ * The initial FPGA image configures a system with 2 clusters, 1 core in each,
+ * and multi-threading is unimplemented.
+ */
+#define FPGA_MAX_CLUSTER_COUNT			2
+#define FPGA_MAX_CPUS_PER_CLUSTER		1
+#define FPGA_MAX_PE_PER_CPU			1
+
+#define FPGA_PRIMARY_CPU			0x0
+
+/*******************************************************************************
+ * FPGA image memory map related constants
+ ******************************************************************************/
+
+/* UART base address and clock frequency, as configured by the image */
+#define PLAT_FPGA_BOOT_UART_BASE 		0x7ff80000
+#define PLAT_FPGA_BOOT_UART_CLK_IN_HZ 		10000000
+
+#define PLAT_FPGA_CRASH_UART_BASE		PLAT_FPGA_BOOT_UART_BASE
+#define PLAT_FPGA_CRASH_UART_CLK_IN_HZ		PLAT_FPGA_BOOT_UART_CLK_IN_HZ
+
+#endif
diff --git a/plat/arm/board/arm_fpga/fpga_pm.c b/plat/arm/board/arm_fpga/fpga_pm.c
new file mode 100644
index 0000000..dc95028
--- /dev/null
+++ b/plat/arm/board/arm_fpga/fpga_pm.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/common/platform.h>
+
+/* TODO: add PSCI implementation */
+
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+			const plat_psci_ops_t **psci_ops)
+{
+	return 0;
+}
diff --git a/plat/arm/board/arm_fpga/fpga_private.h b/plat/arm/board/arm_fpga/fpga_private.h
new file mode 100644
index 0000000..28aaef2
--- /dev/null
+++ b/plat/arm/board/arm_fpga/fpga_private.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FPGA_PRIVATE_H
+#define FPGA_PRIVATE_H
+
+unsigned int plat_fpga_calc_core_pos(u_register_t mpidr);
+
+void fpga_console_init(void);
+
+#endif
diff --git a/plat/arm/board/arm_fpga/fpga_topology.c b/plat/arm/board/arm_fpga/fpga_topology.c
new file mode 100644
index 0000000..5458376
--- /dev/null
+++ b/plat/arm/board/arm_fpga/fpga_topology.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+
+#include "fpga_private.h"
+#include <platform_def.h>
+
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+	/* TODO: add description of power domain topology and PSCI implementation */
+	return NULL;
+}
+
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+	/*
+	 * TODO: calculate core position in a way that accounts for CPUs that
+	 *       potentially implement multithreading
+	 */
+	return (int) plat_fpga_calc_core_pos(mpidr);
+}
diff --git a/plat/arm/board/arm_fpga/include/plat_macros.S b/plat/arm/board/arm_fpga/include/plat_macros.S
new file mode 100644
index 0000000..44cddeb
--- /dev/null
+++ b/plat/arm/board/arm_fpga/include/plat_macros.S
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
+
+.macro plat_crash_print_regs
+.endm
+
+#endif
diff --git a/plat/arm/board/arm_fpga/include/platform_def.h b/plat/arm/board/arm_fpga/include/platform_def.h
new file mode 100644
index 0000000..3138920
--- /dev/null
+++ b/plat/arm/board/arm_fpga/include/platform_def.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <arch.h>
+#include "../fpga_def.h"
+
+#define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
+
+#define PLATFORM_LINKER_ARCH		aarch64
+
+#define PLATFORM_STACK_SIZE		UL(0x800)
+
+#define CACHE_WRITEBACK_SHIFT		U(6)
+#define CACHE_WRITEBACK_GRANULE		(U(1) << CACHE_WRITEBACK_SHIFT)
+
+#define PLATFORM_CORE_COUNT \
+	(FPGA_MAX_CLUSTER_COUNT * FPGA_MAX_CPUS_PER_CLUSTER * FPGA_MAX_PE_PER_CPU)
+
+#define PLAT_NUM_PWR_DOMAINS		(FPGA_MAX_CLUSTER_COUNT + \
+					PLATFORM_CORE_COUNT) + 1
+
+#define BL31_BASE			UL(0x80000000)
+#define BL31_LIMIT			UL(0x80100000)
+
+#define PLAT_MAX_RET_STATE		1
+#define PLAT_MAX_OFF_STATE		2
+
+#define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL2
+
+#define PLAT_FPGA_CONSOLE_BAUDRATE	38400
+
+#endif
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
new file mode 100644
index 0000000..73e1870
--- /dev/null
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -0,0 +1,59 @@
+#
+# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+RESET_TO_BL31 := 1
+ifeq (${RESET_TO_BL31}, 0)
+$(error "This is a BL31-only port; RESET_TO_BL31 must be enabled")
+endif
+
+CTX_INCLUDE_AARCH32_REGS := 0
+ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
+$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
+endif
+
+ifeq (${TRUSTED_BOARD_BOOT}, 1)
+$(error "TRUSTED_BOARD_BOOT must be disabled")
+endif
+
+ifndef PRELOADED_BL33_BASE
+$(error "PRELOADED_BL33_BASE is not set")
+endif
+
+ifndef FPGA_PRELOADED_DTB_BASE
+$(error "FPGA_PRELOADED_DTB_BASE is not set")
+else
+$(eval $(call add_define,FPGA_PRELOADED_DTB_BASE))
+endif
+
+# Treating this as a memory-constrained port for now
+USE_COHERENT_MEM	:=	0
+
+# The CPU in the initial image makes use of this feature
+HW_ASSISTED_COHERENCY	:=	1
+
+FPGA_CPU_LIBS		:=	lib/cpus/${ARCH}/aem_generic.S		\
+				lib/cpus/aarch64/neoverse_zeus.S
+
+FPGA_GIC_SOURCES	:=	drivers/arm/gic/common/gic_common.c	\
+				drivers/arm/gic/v3/gicv3_main.c		\
+				plat/common/plat_gicv3.c
+
+PLAT_INCLUDES		:=	-Iplat/arm/board/arm_fpga/include
+
+PLAT_BL_COMMON_SOURCES	:=	plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S
+
+BL31_SOURCES		+=	drivers/delay_timer/delay_timer.c		\
+				drivers/delay_timer/generic_delay_timer.c	\
+				drivers/arm/pl011/${ARCH}/pl011_console.S	\
+				plat/common/plat_psci_common.c			\
+				plat/arm/board/arm_fpga/fpga_pm.c			\
+				plat/arm/board/arm_fpga/fpga_topology.c		\
+				plat/arm/board/arm_fpga/fpga_console.c		\
+				plat/arm/board/arm_fpga/fpga_bl31_setup.c		\
+				${FPGA_CPU_LIBS}				\
+				${FPGA_GIC_SOURCES}
+
+all: bl31