diff --git a/plat/intel/soc/common/aarch64/plat_helpers.S b/plat/intel/soc/common/aarch64/plat_helpers.S index 00fe2d9..27b538a 100644 --- a/plat/intel/soc/common/aarch64/plat_helpers.S +++ b/plat/intel/soc/common/aarch64/plat_helpers.S @@ -8,6 +8,7 @@ #include #include #include +#include .globl plat_secondary_cold_boot_setup .globl platform_is_primary_cpu @@ -17,6 +18,7 @@ .globl plat_crash_console_putc .globl plat_crash_console_flush .globl platform_mem_init + .globl plat_secondary_cpus_bl31_entry .globl plat_get_my_entrypoint @@ -33,7 +35,6 @@ /* Wait until the it gets reset signal from rstmgr gets populated */ poll_mailbox: wfi - mov_imm x0, PLAT_SEC_ENTRY ldr x1, [x0] mov_imm x2, PLAT_CPUID_RELEASE @@ -114,3 +115,14 @@ mov x0, #0 ret endfunc platform_mem_init + +func plat_secondary_cpus_bl31_entry + el3_entrypoint_common \ + _init_sctlr=0 \ + _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ + _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ + _init_memory=1 \ + _init_c_runtime=1 \ + _exception_vectors=runtime_exceptions \ + _pie_fixup_size=BL31_LIMIT - BL31_BASE +endfunc plat_secondary_cpus_bl31_entry diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h index e57aafb..d6014d3 100644 --- a/plat/intel/soc/common/include/platform_def.h +++ b/plat/intel/soc/common/include/platform_def.h @@ -16,8 +16,8 @@ #define PLAT_SOCFPGA_STRATIX10 1 #define PLAT_SOCFPGA_AGILEX 2 -#define PLAT_CPUID_RELEASE 0xffe1b000 -#define PLAT_SEC_ENTRY 0xffe1b008 +/* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ +#define PLAT_CPU_RELEASE_ADDR 0xffd12210 /* Define next boot image name and offset */ #define PLAT_NS_IMAGE_OFFSET 0x50000 @@ -106,19 +106,24 @@ */ -#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" +#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" -#define BL1_RO_BASE (0xffe00000) -#define BL1_RO_LIMIT (0xffe0f000) -#define BL1_RW_BASE (0xffe10000) -#define BL1_RW_LIMIT (0xffe1ffff) -#define BL1_RW_SIZE (0x14000) +#define BL1_RO_BASE (0xffe00000) +#define BL1_RO_LIMIT (0xffe0f000) +#define BL1_RW_BASE (0xffe10000) +#define BL1_RW_LIMIT (0xffe1ffff) +#define BL1_RW_SIZE (0x14000) -#define BL2_BASE (0xffe00000) -#define BL2_LIMIT (0xffe1b000) +#define BL2_BASE (0xffe00000) +#define BL2_LIMIT (0xffe1b000) -#define BL31_BASE (0xffe1c000) -#define BL31_LIMIT (0xffe3bfff) +#define BL31_BASE (0x1000) +#define BL31_LIMIT (0x81000) + +#define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET + +#define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16) +#define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8) /******************************************************************************* * Platform specific page table and MMU setup constants @@ -194,5 +199,16 @@ #define MAX_IO_DEVICES 4 #define MAX_IO_BLOCK_DEVICES 2 +#ifndef __ASSEMBLER__ +struct socfpga_bl31_params { + param_header_t h; + image_info_t *bl31_image_info; + entry_point_info_t *bl32_ep_info; + image_info_t *bl32_image_info; + entry_point_info_t *bl33_ep_info; + image_info_t *bl33_image_info; +}; +#endif + #endif /* PLATFORM_DEF_H */ diff --git a/plat/intel/soc/common/include/socfpga_private.h b/plat/intel/soc/common/include/socfpga_private.h index 3754844..ca38f62 100644 --- a/plat/intel/soc/common/include/socfpga_private.h +++ b/plat/intel/soc/common/include/socfpga_private.h @@ -61,5 +61,6 @@ unsigned long socfpga_get_ns_image_entrypoint(void); +void plat_secondary_cpus_bl31_entry(void); #endif /* SOCFPGA_PRIVATE_H */ diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c index e298361..65a4b09 100644 --- a/plat/intel/soc/common/socfpga_psci.c +++ b/plat/intel/soc/common/socfpga_psci.c @@ -15,8 +15,6 @@ #include "socfpga_plat_def.h" -uintptr_t *socfpga_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY; -uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE; /******************************************************************************* * plat handler called when a CPU is about to enter standby. @@ -45,7 +43,7 @@ if (cpu_id == -1) return PSCI_E_INTERN_FAIL; - *cpuid_release = cpu_id; + mmio_write_64(PLAT_CPUID_RELEASE, cpu_id); /* release core reset */ mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id); @@ -183,8 +181,8 @@ const struct plat_psci_ops **psci_ops) { /* Save warm boot entrypoint.*/ - *socfpga_sec_entry = sec_entrypoint; - + mmio_write_64(PLAT_SEC_ENTRY, sec_entrypoint); *psci_ops = &socfpga_psci_pm_ops; + return 0; } diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c index a133f82..29bd176 100644 --- a/plat/intel/soc/stratix10/bl31_plat_setup.c +++ b/plat/intel/soc/stratix10/bl31_plat_setup.c @@ -53,23 +53,33 @@ void *from_bl2 = (void *) arg0; bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; - assert(params_from_bl2 != NULL); - assert(params_from_bl2->h.type == PARAM_BL_PARAMS); - assert(params_from_bl2->h.version >= VERSION_2); /* * Copy BL32 (if populated by BL31) and BL33 entry point information. * They are stored in Secure RAM, in BL31's address space. */ - bl_params_node_t *bl_params = params_from_bl2->head; + if (params_from_bl2->h.type == PARAM_BL_PARAMS && + params_from_bl2->h.version >= VERSION_2) { - while (bl_params) { - if (bl_params->image_id == BL33_IMAGE_ID) - bl33_image_ep_info = *bl_params->ep_info; + bl_params_node_t *bl_params = params_from_bl2->head; - bl_params = bl_params->next_params_info; + while (bl_params) { + if (bl_params->image_id == BL33_IMAGE_ID) + bl33_image_ep_info = *bl_params->ep_info; + + bl_params = bl_params->next_params_info; + } + } else { + struct socfpga_bl31_params *arg_from_bl2 = + (struct socfpga_bl31_params *) from_bl2; + + assert(arg_from_bl2->h.type == PARAM_BL31); + assert(arg_from_bl2->h.version >= VERSION_1); + + bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; + bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; } SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); } @@ -100,6 +110,10 @@ gicv2_distif_init(); gicv2_pcpu_distif_init(); gicv2_cpuif_enable(); + + /* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */ + mmio_write_64(PLAT_CPU_RELEASE_ADDR, + (uint64_t)plat_secondary_cpus_bl31_entry); } const mmap_region_t plat_stratix10_mmap[] = {