diff --git a/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c b/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c index 3b81814..cdbae9d 100644 --- a/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c +++ b/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -18,9 +19,6 @@ #include "mss_scp_bootloader.h" -/* IO windows configuration */ -#define IOW_GCR_OFFSET (0x70) - /* MSS windows configuration */ #define MSS_AEBR(base) (base + 0x160) #define MSS_AIBR(base) (base + 0x164) @@ -51,7 +49,7 @@ */ static int bl2_plat_mmap_init(void) { - int cfg_num, win_id, cfg_idx; + int cfg_num, win_id, cfg_idx, cp; cfg_num = ARRAY_SIZE(ccu_mem_map); @@ -71,8 +69,14 @@ ccu_enable_win(MVEBU_AP0, &ccu_mem_map[cfg_idx], win_id); } - /* Set the default target id to PIDI */ - mmio_write_32(MVEBU_IO_WIN_BASE(MVEBU_AP0) + IOW_GCR_OFFSET, PIDI_TID); + /* Config address for each cp other than cp0 */ + for (cp = 1; cp < CP_COUNT; cp++) + update_cp110_default_win(cp); + + /* There is need to configure IO_WIN windows again to overwrite + * temporary configuration done during update_cp110_default_win + */ + init_io_win(MVEBU_AP0); /* Open AMB bridge required for MG access */ for (cp = 0; cp < CP_COUNT; cp++) diff --git a/plat/marvell/armada/a8k/common/plat_bl31_setup.c b/plat/marvell/armada/a8k/common/plat_bl31_setup.c index 621f43c..552c9b2 100644 --- a/plat/marvell/armada/a8k/common/plat_bl31_setup.c +++ b/plat/marvell/armada/a8k/common/plat_bl31_setup.c @@ -116,21 +116,12 @@ marvell_bl31_plat_arch_setup(); for (cp = 0; cp < CP_COUNT; cp++) { - if (cp >= 1) - update_cp110_default_win(cp); - cp110_init(MVEBU_CP_REGS_BASE(cp), STREAM_ID_BASE + (cp * MAX_STREAM_ID_PER_CP)); marvell_bl31_mpp_init(cp); } - /* - * There is need to configure IO_WIN windows again to overwrite - * temporary configuration done during update_cp110_default_win - */ - init_io_win(MVEBU_AP0); - for (cp = 1; cp < CP_COUNT; cp++) mci_link_tune(cp - 1);