diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index e49c73e..07983a9 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -143,6 +143,9 @@
 -  ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55
    CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
 
+-  ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55
+   CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
+
 For Cortex-A57, the following errata build flags are defined :
 
 -  ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
diff --git a/include/lib/cpus/aarch64/cortex_a55.h b/include/lib/cpus/aarch64/cortex_a55.h
index feac1d2..60ed957 100644
--- a/include/lib/cpus/aarch64/cortex_a55.h
+++ b/include/lib/cpus/aarch64/cortex_a55.h
@@ -39,4 +39,10 @@
 /* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */
 #define CORTEX_A55_CORE_PWRDN_EN_MASK	U(0x1)
 
+/* Instruction patching registers */
+#define CPUPSELR_EL3	S3_6_C15_C8_0
+#define CPUPCR_EL3	S3_6_C15_C8_1
+#define CPUPOR_EL3	S3_6_C15_C8_2
+#define CPUPMR_EL3	S3_6_C15_C8_3
+
 #endif /* CORTEX_A55_H */
diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S
index 0ef373a..8e13824 100644
--- a/lib/cpus/aarch64/cortex_a55.S
+++ b/lib/cpus/aarch64/cortex_a55.S
@@ -175,6 +175,53 @@
 	b	cpu_rev_var_ls
 endfunc check_errata_903758
 
+	/* -----------------------------------------------------
+	 * Errata Workaround for Cortex A55 Errata #1221012.
+	 * This applies only to revisions <= r1p0 of Cortex A55.
+	 * Inputs:
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0-x17
+	 * -----------------------------------------------------
+	 */
+func errata_a55_1221012_wa
+	/*
+	 * Compare x0 against revision r1p0
+	 */
+	mov	x17, x30
+	bl	check_errata_1221012
+	cbz	x0, 1f
+	mov	x0, #0x0020
+	movk	x0, #0x0850, lsl #16
+	msr	CPUPOR_EL3, x0
+	mov	x0, #0x0000
+	movk	x0, #0x1FF0, lsl #16
+	movk	x0, #0x2, lsl #32
+	msr	CPUPMR_EL3, x0
+	mov	x0, #0x03fd
+	movk	x0, #0x0110, lsl #16
+	msr	CPUPCR_EL3, x0
+	mov	x0, #0x1
+	msr	CPUPSELR_EL3, x0
+	mov	x0, #0x0040
+	movk	x0, #0x08D0, lsl #16
+	msr	CPUPOR_EL3, x0
+	mov	x0, #0x0040
+	movk	x0, #0x1FF0, lsl #16
+	movk	x0, #0x2, lsl #32
+	msr	CPUPMR_EL3, x0
+	mov	x0, #0x03fd
+	movk	x0, #0x0110, lsl #16
+	msr	CPUPCR_EL3, x0
+	isb
+1:
+	ret	x17
+endfunc errata_a55_1221012_wa
+
+func check_errata_1221012
+	mov	x1, #0x10
+	b	cpu_rev_var_ls
+endfunc check_errata_1221012
+
 func cortex_a55_reset_func
 	mov	x19, x30
 
@@ -214,6 +261,11 @@
 	bl	errata_a55_903758_wa
 #endif
 
+#if ERRATA_A55_1221012
+	mov	x0, x18
+	bl	errata_a55_1221012_wa
+#endif
+
 	ret	x19
 endfunc cortex_a55_reset_func
 
@@ -253,6 +305,7 @@
 	report_errata ERRATA_A55_798797, cortex_a55, 798797
 	report_errata ERRATA_A55_846532, cortex_a55, 846532
 	report_errata ERRATA_A55_903758, cortex_a55, 903758
+	report_errata ERRATA_A55_1221012, cortex_a55, 1221012
 
 	ldp	x8, x30, [sp], #16
 	ret
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index e45d79d..599e11e 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -134,6 +134,10 @@
 # only to revision <= r0p1 of the Cortex A55 cpu.
 ERRATA_A55_903758	?=0
 
+# Flag to apply erratum 1221012 workaround during reset. This erratum applies
+# only to revision <= r1p0 of the Cortex A55 cpu.
+ERRATA_A55_1221012	?=0
+
 # Flag to apply erratum 806969 workaround during reset. This erratum applies
 # only to revision r0p0 of the Cortex A57 cpu.
 ERRATA_A57_806969	?=0
@@ -319,6 +323,10 @@
 $(eval $(call assert_boolean,ERRATA_A55_903758))
 $(eval $(call add_define,ERRATA_A55_903758))
 
+# Process ERRATA_A55_1221012 flag
+$(eval $(call assert_boolean,ERRATA_A55_1221012))
+$(eval $(call add_define,ERRATA_A55_1221012))
+
 # Process ERRATA_A57_806969 flag
 $(eval $(call assert_boolean,ERRATA_A57_806969))
 $(eval $(call add_define,ERRATA_A57_806969))