diff --git a/readme.md b/readme.md index cc2294b..d9a1714 100644 --- a/readme.md +++ b/readme.md @@ -1,4 +1,4 @@ -ARM Trusted Firmware - version 1.2 +ARM Trusted Firmware - version 1.3 ================================== ARM Trusted Firmware provides a reference implementation of secure world @@ -17,17 +17,25 @@ License ------- -The software is provided under a BSD 3-Clause [license]. Certain source files -are derived from FreeBSD code: the original license is included in these -source files. +The software is provided under a BSD-3-Clause [license]. Contributions to this +project are accepted under the same license with developer sign-off as +described in the [Contributing Guidelines]. + +This project contains code from other projects as listed below. The original +license text is included in those source files. + +* The stdlib source code is derived from FreeBSD code. + +* The libfdt source code is dual licensed. It is used by this project under + the terms of the BSD-2-Clause license. This Release ------------ This release provides a suitable starting point for productization of secure -world boot and runtime firmware. Future versions will contain new features, -optimizations and quality improvements. +world boot and runtime firmware, executing in either the AArch32 or AArch64 +execution state. Users are encouraged to do their own security validation, including penetration testing, on any secure world code derived from ARM Trusted Firmware. @@ -42,7 +50,7 @@ * Library support for CPU specific reset and power down sequences. This includes support for errata workarounds. -* Drivers for both the version 2.0 and version 3.0 ARM Generic Interrupt +* Drivers for both versions 2.0 and 3.0 of the ARM Generic Interrupt Controller specifications (GICv2 and GICv3). The latter also enables GICv3 hardware systems that do not contain legacy GICv2 support. @@ -53,18 +61,26 @@ * SMC (Secure Monitor Call) handling, conforming to the [SMC Calling Convention][SMCCC] using an EL3 runtime services framework. -* SMC handling relating to [PSCI] for the Secondary CPU Boot, CPU Hotplug, - CPU Idle and System Shutdown/Reset/Suspend use-cases. +* [PSCI] library support for the Secondary CPU Boot, CPU Hotplug, CPU Idle + and System Shutdown/Reset/Suspend use-cases. + This library is pre-integrated with the provided AArch64 EL3 Runtime + Software, and is also suitable for integration into other EL3 Runtime + Software. + +* A minimal AArch32 Secure Payload to demonstrate [PSCI] library integration + on platforms with AArch32 EL3 Runtime Software. * Secure Monitor library code such as world switching, EL1 context management - and interrupt routing. This must be integrated with a Secure-EL1 Payload - Dispatcher (SPD) component to customize the interaction with a Secure-EL1 - Payload (SP), for example a Secure OS. + and interrupt routing. + When using the provided AArch64 EL3 Runtime Software, this must be + integrated with a Secure-EL1 Payload Dispatcher (SPD) component to + customize the interaction with a Secure-EL1 Payload (SP), for example a + Secure OS. -* A Test Secure-EL1 Payload and Dispatcher to demonstrate Secure Monitor - functionality and Secure-EL1 interaction with PSCI. +* A Test Secure-EL1 Payload and Dispatcher to demonstrate AArch64 Secure + Monitor functionality and Secure-EL1 interaction with PSCI. -* SPDs for the [OP-TEE Secure OS] and [NVidia Trusted Little Kernel] +* AArch64 SPDs for the [OP-TEE Secure OS] and [NVidia Trusted Little Kernel] [NVidia TLK]. * A Trusted Board Boot implementation, conforming to all mandatory TBBR @@ -72,11 +88,12 @@ Firmware Update (or recovery mode) boot flow, and packaging of the various firmware images into a Firmware Image Package (FIP) to be loaded from non-volatile storage. + The TBBR implementation is currently only supported in the AArch64 build. * Support for alternative boot flows. Some platforms have their own boot - firmware and only require the ARM Trusted Firmware Secure Monitor - functionality. Other platforms require minimal initialization before - booting into an arbitrary EL3 payload. + firmware and only require the AArch64 EL3 Runtime Software provided by this + project. Other platforms require minimal initialization before booting + into an arbitrary EL3 payload. For a full description of functionality and implementation details, please see the [Firmware Design] and supporting documentation. The [Change Log] @@ -84,36 +101,46 @@ ### Platforms -This release of the Trusted Firmware has been tested on variants r0 and r1 of -the [Juno ARM Development Platform] [Juno] with [Linaro Release 15.10] -[Linaro Release Notes]. +The AArch64 build of this release has been tested on variants r0, r1 and r2 +of the [Juno ARM Development Platform] [Juno] with [Linaro Release 16.06]. -The Trusted Firmware has also been tested on the 64-bit Linux versions of the -following ARM [FVP]s: +The AArch64 build of this release has been tested on the following ARM +[FVP]s (64-bit host machine only): -* `Foundation_Platform` (Version 9.4, Build 9.4.59) -* `FVP_Base_AEMv8A-AEMv8A` (Version 7.0, Build 0.8.7004) -* `FVP_Base_Cortex-A57x4-A53x4` (Version 7.0, Build 0.8.7004) -* `FVP_Base_Cortex-A57x1-A53x1` (Version 7.0, Build 0.8.7004) -* `FVP_Base_Cortex-A57x2-A53x4` (Version 7.0, Build 0.8.7004) +* `Foundation_Platform` (Version 10.1, Build 10.1.32) +* `FVP_Base_AEMv8A-AEMv8A` (Version 7.7, Build 0.8.7701) +* `FVP_Base_Cortex-A57x4-A53x4` (Version 7.7, Build 0.8.7701) +* `FVP_Base_Cortex-A57x1-A53x1` (Version 7.7, Build 0.8.7701) +* `FVP_Base_Cortex-A57x2-A53x4` (Version 7.7, Build 0.8.7701) + +The AArch32 build of this release has been tested on the following ARM +[FVP]s (64-bit host machine only): + +* `FVP_Base_AEMv8A-AEMv8A` (Version 7.7, Build 0.8.7701) +* `FVP_Base_Cortex-A32x4` (Version 10.1, Build 10.1.32) The Foundation FVP can be downloaded free of charge. The Base FVPs can be licensed from ARM: see [www.arm.com/fvp] [FVP]. This release also contains the following platform support: +* MediaTek MT6795 and MT8173 SoCs * NVidia T210 and T132 SoCs -* MediaTek MT8173 SoC +* QEMU emulator +* RockChip RK3368 and RK3399 SoCs +* Xilinx Zynq UltraScale + MPSoC ### Still to Come -* Complete implementation of the [PSCI] v1.0 specification. - -* Support for new CPUs and System IP. +* AArch32 TBBR support and ongoing TBBR alignment. * More platform support. -* Optimization and quality improvements. +* Ongoing support for new architectural features, CPUs and System IP. + +* Ongoing [PSCI] alignment and feature support. + +* Ongoing security hardening, optimization and quality improvements. For a full list of detailed issues in the current code, please see the [Change Log] and the [GitHub issue tracker]. @@ -147,7 +174,7 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - -_Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved._ +_Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved._ [License]: ./license.md "BSD license for ARM Trusted Firmware" @@ -167,4 +194,4 @@ [GitHub issue tracker]: https://github.com/ARM-software/tf-issues/issues [OP-TEE Secure OS]: https://github.com/OP-TEE/optee_os [NVidia TLK]: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary -[Linaro Release Notes]: https://community.arm.com/docs/DOC-10952#jive_content_id_Linaro_Release_1510 +[Linaro Release 16.06]: https://community.arm.com/docs/DOC-10952#jive_content_id_Linaro_Release_1606