diff --git a/plat/imx/common/include/imx_clock.h b/plat/imx/common/include/imx_clock.h index ce245ad..d75dcff 100644 --- a/plat/imx/common/include/imx_clock.h +++ b/plat/imx/common/include/imx_clock.h @@ -1,6 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * SPDX-License-Identifier: BSD-3-Clause */ #ifndef IMX_CLOCK_H @@ -819,6 +818,8 @@ #define CCM_TRGT_MUX_WDOG_CLK_ROOT_USB_PLL (BIT(26) | BIT(24)) #define CCM_TRGT_MUX_WDOG_CLK_ROOT_REF_1M (BIT(26) | BIT(25)) #define CCM_TRGT_MUX_WDOG_CLK_ROOT_SYS_PLL_PFD1_DIV2 ((BIT(26) | BIT(25) | BIT(24)) +#define WDOG_DEFAULT_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ + CCM_TRGT_MUX_WDOG_CLK_ROOT_OSC_24M) /* Target CSI_MCLK_CLK_ROOT */ diff --git a/plat/imx/imx7/common/imx7.mk b/plat/imx/imx7/common/imx7.mk new file mode 100644 index 0000000..849ddcd --- /dev/null +++ b/plat/imx/imx7/common/imx7.mk @@ -0,0 +1,110 @@ +# +# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# Architecture +$(eval $(call add_define,ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING)) + +TF_CFLAGS += -mfpu=neon +ASFLAGS += -mfpu=neon + +# Platform +PLAT_INCLUDES := -Idrivers/imx/uart \ + -Iplat/imx/common/include \ + -Iplat/imx/imx7/include \ + -Idrivers/imx/timer \ + -Idrivers/imx/usdhc \ + +# Translation tables library +include lib/xlat_tables_v2/xlat_tables.mk + +BL2_SOURCES += common/desc_image_load.c \ + drivers/delay_timer/delay_timer.c \ + drivers/mmc/mmc.c \ + drivers/io/io_block.c \ + drivers/io/io_fip.c \ + drivers/io/io_memmap.c \ + drivers/io/io_storage.c \ + drivers/imx/timer/imx_gpt.c \ + drivers/imx/uart/imx_uart.c \ + drivers/imx/uart/imx_crash_uart.S \ + lib/aarch32/arm32_aeabi_divmod.c \ + lib/aarch32/arm32_aeabi_divmod_a32.S \ + lib/cpus/aarch32/cortex_a7.S \ + lib/optee/optee_utils.c \ + plat/imx/common/imx_aips.c \ + plat/imx/common/imx_caam.c \ + plat/imx/common/imx_clock.c \ + plat/imx/common/imx_csu.c \ + plat/imx/common/imx_io_mux.c \ + plat/imx/common/imx_snvs.c \ + plat/imx/common/imx_wdog.c \ + plat/imx/common/imx7_clock.c \ + plat/imx/imx7/common/imx7_bl2_mem_params_desc.c \ + plat/imx/imx7/common/imx7_bl2_el3_common.c \ + plat/imx/imx7/common/imx7_helpers.S \ + plat/imx/imx7/common/imx7_image_load.c \ + plat/imx/imx7/common/imx7_io_storage.c \ + plat/imx/common/aarch32/imx_uart_console.S \ + ${XLAT_TABLES_LIB_SRCS} + +ifneq (${TRUSTED_BOARD_BOOT},0) + +include drivers/auth/mbedtls/mbedtls_crypto.mk +include drivers/auth/mbedtls/mbedtls_x509.mk + +AUTH_SOURCES := drivers/auth/auth_mod.c \ + drivers/auth/crypto_mod.c \ + drivers/auth/img_parser_mod.c \ + drivers/auth/tbbr/tbbr_cot.c + +BL2_SOURCES += ${AUTH_SOURCES} \ + plat/common/tbbr/plat_tbbr.c \ + plat/imx/imx7/common/imx7_trusted_boot.c \ + plat/imx/imx7/common/imx7_rotpk.S + +ROT_KEY = $(BUILD_PLAT)/rot_key.pem +ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin + +$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"')) +$(eval $(call MAKE_LIB_DIRS)) + +$(BUILD_PLAT)/bl2/imx7_rotpk.o: $(ROTPK_HASH) + +certificates: $(ROT_KEY) + +$(ROT_KEY): | $(BUILD_PLAT) + @echo " OPENSSL $@" + @if [ ! -f $(ROT_KEY) ]; then \ + openssl genrsa 2048 > $@ 2>/dev/null; \ + fi + +$(ROTPK_HASH): $(ROT_KEY) + @echo " OPENSSL $@" + $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ + openssl dgst -sha256 -binary > $@ 2>/dev/null +endif + +# Add the build options to pack BLx images and kernel device tree +# in the FIP if the platform requires. +ifneq ($(BL2),) +$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert)) +endif +ifneq ($(BL32_EXTRA1),) +$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1)) +endif +ifneq ($(BL32_EXTRA2),) +$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2)) +endif +ifneq ($(HW_CONFIG),) +$(eval $(call TOOL_ADD_IMG,HW_CONFIG,--hw-config)) +endif + +# Verify build config +# ------------------- + +ifeq (${ARCH},aarch64) + $(error Error: AArch64 not supported on i.mx7) +endif diff --git a/plat/imx/imx7/common/imx7_bl2_el3_common.c b/plat/imx/imx7/common/imx7_bl2_el3_common.c new file mode 100644 index 0000000..a1e2aaf --- /dev/null +++ b/plat/imx/imx7/common/imx7_bl2_el3_common.c @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef AARCH32_SP_OPTEE +#error "Must build with OPTEE support included" +#endif + +uintptr_t plat_get_ns_image_entrypoint(void) +{ + return IMX7_UBOOT_BASE; +} + +static uint32_t imx7_get_spsr_for_bl32_entry(void) +{ + return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, + DISABLE_ALL_EXCEPTIONS); +} + +static uint32_t imx7_get_spsr_for_bl33_entry(void) +{ + return SPSR_MODE32(MODE32_svc, + plat_get_ns_image_entrypoint() & 0x1, + SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); +} + +int bl2_plat_handle_post_image_load(unsigned int image_id) +{ + int err = 0; + bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); + bl_mem_params_node_t *hw_cfg_mem_params = NULL; + + bl_mem_params_node_t *pager_mem_params = NULL; + bl_mem_params_node_t *paged_mem_params = NULL; + + assert(bl_mem_params); + + switch (image_id) { + case BL32_IMAGE_ID: + pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); + assert(pager_mem_params); + + paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); + assert(paged_mem_params); + + err = parse_optee_header(&bl_mem_params->ep_info, + &pager_mem_params->image_info, + &paged_mem_params->image_info); + if (err != 0) + WARN("OPTEE header parse error.\n"); + + /* + * When ATF loads the DTB the address of the DTB is passed in + * arg2, if an hw config image is present use the base address + * as DTB address an pass it as arg2 + */ + hw_cfg_mem_params = get_bl_mem_params_node(HW_CONFIG_ID); + + bl_mem_params->ep_info.args.arg0 = + bl_mem_params->ep_info.args.arg1; + bl_mem_params->ep_info.args.arg1 = 0; + if (hw_cfg_mem_params) + bl_mem_params->ep_info.args.arg2 = + hw_cfg_mem_params->image_info.image_base; + else + bl_mem_params->ep_info.args.arg2 = 0; + bl_mem_params->ep_info.args.arg3 = 0; + bl_mem_params->ep_info.spsr = imx7_get_spsr_for_bl32_entry(); + break; + + case BL33_IMAGE_ID: + /* AArch32 only core: OP-TEE expects NSec EP in register LR */ + pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); + assert(pager_mem_params); + pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; + + /* BL33 expects to receive the primary CPU MPID (through r0) */ + bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); + bl_mem_params->ep_info.spsr = imx7_get_spsr_for_bl33_entry(); + break; + + default: + /* Do nothing in default case */ + break; + } + + return err; +} + +void bl2_el3_plat_arch_setup(void) +{ + /* Setup the MMU here */ +} + +static void imx7_setup_system_counter(void) +{ + unsigned long freq = SYS_COUNTER_FREQ_IN_TICKS; + + /* Set the frequency table index to our target frequency */ + write_cntfrq(freq); + + /* Enable system counter @ frequency table index 0, halt on debug */ + mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, + CNTCR_FCREQ(0) | CNTCR_HDBG | CNTCR_EN); +} + +static void imx7_setup_wdog_clocks(void) +{ + uint32_t wdog_en_bits = (uint32_t)WDOG_DEFAULT_CLK_SELECT; + + imx_clock_set_wdog_clk_root_bits(wdog_en_bits); + imx_clock_enable_wdog(0); + imx_clock_enable_wdog(1); + imx_clock_enable_wdog(2); + imx_clock_enable_wdog(3); +} + + +/* + * bl2_el3_early_platform_setup() + * MMU off + */ +void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, + u_register_t arg3, u_register_t arg4) +{ + static console_imx_uart_t console; + int console_scope = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME; + + /* Initialize common components */ + imx_aips_init(); + imx_csu_init(); + imx_snvs_init(); + imx_gpt_ops_init(GPT1_BASE_ADDR); + imx_clock_init(); + imx7_setup_system_counter(); + imx7_setup_wdog_clocks(); + + /* Platform specific setup */ + imx7_platform_setup(arg1, arg2, arg3, arg4); + + /* Init UART, clock should be enabled in imx7_platform_setup() */ + console_imx_uart_register(PLAT_IMX7_BOOT_UART_BASE, + PLAT_IMX7_BOOT_UART_CLK_IN_HZ, + PLAT_IMX7_CONSOLE_BAUDRATE, + &console); + console_set_scope(&console.console, console_scope); + + /* Open handles to persistent storage */ + plat_imx7_io_setup(); + + /* Setup higher-level functionality CAAM, RTC etc */ + imx_caam_init(); + imx_wdog_init(); + + /* Print out the expected memory map */ + VERBOSE("\tOPTEE 0x%08x-0x%08x\n", IMX7_OPTEE_BASE, IMX7_OPTEE_LIMIT); + VERBOSE("\tATF/BL2 0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT); + VERBOSE("\tSHRAM 0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT); + VERBOSE("\tFIP 0x%08x-0x%08x\n", IMX7_FIP_BASE, IMX7_FIP_LIMIT); + VERBOSE("\tDTB-OVERLAY 0x%08x-0x%08x\n", IMX7_DTB_OVERLAY_BASE, IMX7_DTB_OVERLAY_LIMIT); + VERBOSE("\tDTB 0x%08x-0x%08x\n", IMX7_DTB_BASE, IMX7_DTB_LIMIT); + VERBOSE("\tUBOOT/BL33 0x%08x-0x%08x\n", IMX7_UBOOT_BASE, IMX7_UBOOT_LIMIT); +} + +/* + * bl2_platform_setup() + * MMU on - enabled by bl2_el3_plat_arch_setup() + */ +void bl2_platform_setup(void) +{ +} diff --git a/plat/imx/imx7/common/imx7_bl2_mem_params_desc.c b/plat/imx/imx7/common/imx7_bl2_mem_params_desc.c new file mode 100644 index 0000000..f9b2983 --- /dev/null +++ b/plat/imx/imx7/common/imx7_bl2_mem_params_desc.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include + +static bl_mem_params_node_t bl2_mem_params_descs[] = { + { + .image_id = BL32_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, + entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = BL32_BASE, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, + image_info_t, 0), + + .image_info.image_base = IMX7_OPTEE_BASE, + .image_info.image_max_size = IMX7_OPTEE_SIZE, + + .next_handoff_image_id = BL33_IMAGE_ID, + }, + { + .image_id = BL32_EXTRA1_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, + entry_point_info_t, + SECURE | NON_EXECUTABLE), + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, + image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .image_info.image_base = IMX7_OPTEE_BASE, + .image_info.image_max_size = IMX7_OPTEE_SIZE, + + .next_handoff_image_id = INVALID_IMAGE_ID, + }, + { + /* This is a zero sized image so we don't set base or size */ + .image_id = BL32_EXTRA2_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | NON_EXECUTABLE), + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, + IMAGE_ATTRIB_SKIP_LOADING), + .next_handoff_image_id = INVALID_IMAGE_ID, + }, + { + .image_id = BL33_IMAGE_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, + entry_point_info_t, + NON_SECURE | EXECUTABLE), + # ifdef PRELOADED_BL33_BASE + .ep_info.pc = PRELOADED_BL33_BASE, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, + IMAGE_ATTRIB_SKIP_LOADING), + # else + .ep_info.pc = BL33_BASE, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = IMX7_UBOOT_BASE, + .image_info.image_max_size = IMX7_UBOOT_SIZE, + # endif /* PRELOADED_BL33_BASE */ + + .next_handoff_image_id = INVALID_IMAGE_ID, + } +}; + +REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs); diff --git a/plat/imx/imx7/common/imx7_helpers.S b/plat/imx/imx7/common/imx7_helpers.S new file mode 100644 index 0000000..661fd29 --- /dev/null +++ b/plat/imx/imx7/common/imx7_helpers.S @@ -0,0 +1,59 @@ +/* + * Copyright (c) Linaro 2018-2019 Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + + .globl platform_mem_init + .globl plat_get_my_entrypoint + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl plat_crash_console_flush + .globl plat_panic_handler + + /* --------------------------------------------- + * int plat_mem_init(void) + * Function to initialize memory. + * The HAB hands off the DDR controller already + * setup and ready to use. + * Implement the mandatory function as a NOP + * --------------------------------------------- + */ +func platform_mem_init + bx lr +endfunc platform_mem_init + +func plat_get_my_entrypoint + mov r0, #0 + bx lr +endfunc plat_get_my_entrypoint + +func plat_crash_console_init + mov_imm r0, PLAT_IMX7_BOOT_UART_BASE + mov_imm r1, PLAT_IMX7_BOOT_UART_CLK_IN_HZ + mov_imm r2, PLAT_IMX7_CONSOLE_BAUDRATE + b imx_crash_uart_init +endfunc plat_crash_console_init + +func plat_crash_console_putc + mov_imm r1, PLAT_IMX7_BOOT_UART_BASE + b imx_crash_uart_putc +endfunc plat_crash_console_putc + +func plat_crash_console_flush + /* Placeholder */ + mov r0, #0 + bx lr +endfunc plat_crash_console_flush + +func plat_panic_handler + mov r3, #HAB_ROM_VECTOR_TABLE_FAILSAFE + ldr r3, [r3, #0] + blx r3 +endfunc plat_panic_handler diff --git a/plat/imx/imx7/common/imx7_image_load.c b/plat/imx/imx7/common/imx7_image_load.c new file mode 100644 index 0000000..c3e47b9 --- /dev/null +++ b/plat/imx/imx7/common/imx7_image_load.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +void plat_flush_next_bl_params(void) +{ + flush_bl_params_desc(); +} + +bl_load_info_t *plat_get_bl_image_load_info(void) +{ + return get_bl_load_info_from_mem_params_desc(); +} + +bl_params_t *plat_get_next_bl_params(void) +{ + return get_next_bl_params_from_mem_params_desc(); +} diff --git a/plat/imx/imx7/common/imx7_io_storage.c b/plat/imx/imx7/common/imx7_io_storage.c new file mode 100644 index 0000000..977181d --- /dev/null +++ b/plat/imx/imx7/common/imx7_io_storage.c @@ -0,0 +1,270 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +static const io_dev_connector_t *fip_dev_con; +static uintptr_t fip_dev_handle; + +#ifndef IMX7_FIP_MMAP +static const io_dev_connector_t *mmc_dev_con; +static uintptr_t mmc_dev_handle; + +static const io_block_spec_t mmc_fip_spec = { + .offset = IMX7_FIP_MMC_BASE, + .length = IMX7_FIP_SIZE +}; + +static const io_block_dev_spec_t mmc_dev_spec = { + /* It's used as temp buffer in block driver. */ + .buffer = { + .offset = IMX7_FIP_BASE, + /* do we need a new value? */ + .length = IMX7_FIP_SIZE + }, + .ops = { + .read = mmc_read_blocks, + .write = mmc_write_blocks, + }, + .block_size = MMC_BLOCK_SIZE, +}; + +static int open_mmc(const uintptr_t spec); + +#else +static const io_dev_connector_t *memmap_dev_con; +static uintptr_t memmap_dev_handle; + +static const io_block_spec_t fip_block_spec = { + .offset = IMX7_FIP_BASE, + .length = IMX7_FIP_SIZE +}; +static int open_memmap(const uintptr_t spec); +#endif +static int open_fip(const uintptr_t spec); + +static const io_uuid_spec_t bl32_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32, +}; + +static const io_uuid_spec_t bl32_extra1_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1, +}; + +static const io_uuid_spec_t bl32_extra2_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2, +}; + +static const io_uuid_spec_t bl33_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, +}; + +#if TRUSTED_BOARD_BOOT +static const io_uuid_spec_t tb_fw_cert_uuid_spec = { + .uuid = UUID_TRUSTED_BOOT_FW_CERT, +}; + +static const io_uuid_spec_t trusted_key_cert_uuid_spec = { + .uuid = UUID_TRUSTED_KEY_CERT, +}; + +static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = { + .uuid = UUID_TRUSTED_OS_FW_KEY_CERT, +}; + +static const io_uuid_spec_t tos_fw_cert_uuid_spec = { + .uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT, +}; + +static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FW_KEY_CERT, +}; + +static const io_uuid_spec_t nt_fw_cert_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT, +}; +#endif /* TRUSTED_BOARD_BOOT */ + +/* TODO: this structure is replicated multiple times. rationalize it ! */ +struct plat_io_policy { + uintptr_t *dev_handle; + uintptr_t image_spec; + int (*check)(const uintptr_t spec); +}; + +static const struct plat_io_policy policies[] = { +#ifndef IMX7_FIP_MMAP + [FIP_IMAGE_ID] = { + &mmc_dev_handle, + (uintptr_t)&mmc_fip_spec, + open_mmc + }, +#else + [FIP_IMAGE_ID] = { + &memmap_dev_handle, + (uintptr_t)&fip_block_spec, + open_memmap + }, +#endif + [BL32_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_uuid_spec, + open_fip + }, + [BL32_EXTRA1_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_extra1_uuid_spec, + open_fip + }, + [BL32_EXTRA2_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_extra2_uuid_spec, + open_fip + }, + [BL33_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl33_uuid_spec, + open_fip + }, +#if TRUSTED_BOARD_BOOT + [TRUSTED_BOOT_FW_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tb_fw_cert_uuid_spec, + open_fip + }, + [TRUSTED_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&trusted_key_cert_uuid_spec, + open_fip + }, + [TRUSTED_OS_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tos_fw_key_cert_uuid_spec, + open_fip + }, + [NON_TRUSTED_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&nt_fw_key_cert_uuid_spec, + open_fip + }, + [TRUSTED_OS_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tos_fw_cert_uuid_spec, + open_fip + }, + [NON_TRUSTED_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&nt_fw_cert_uuid_spec, + open_fip + }, +#endif /* TRUSTED_BOARD_BOOT */ +}; + +static int open_fip(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + /* See if a Firmware Image Package is available */ + result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); + if (result == 0) { + result = io_open(fip_dev_handle, spec, &local_image_handle); + if (result == 0) { + VERBOSE("Using FIP\n"); + io_close(local_image_handle); + } + } + return result; +} + +#ifndef IMX7_FIP_MMAP +static int open_mmc(const uintptr_t spec) +{ + int result; + uintptr_t local_handle; + + result = io_dev_init(mmc_dev_handle, (uintptr_t)NULL); + if (result == 0) { + result = io_open(mmc_dev_handle, spec, &local_handle); + if (result == 0) + io_close(local_handle); + } + return result; +} +#else +static int open_memmap(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL); + if (result == 0) { + result = io_open(memmap_dev_handle, spec, &local_image_handle); + if (result == 0) { + VERBOSE("Using Memmap\n"); + io_close(local_image_handle); + } + } + return result; +} +#endif + +int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + int result; + const struct plat_io_policy *policy; + + assert(image_id < ARRAY_SIZE(policies)); + + policy = &policies[image_id]; + result = policy->check(policy->image_spec); + assert(result == 0); + + *image_spec = policy->image_spec; + *dev_handle = *policy->dev_handle; + + return result; +} + +void plat_imx7_io_setup(void) +{ + int result __unused; + +#ifndef IMX7_FIP_MMAP + result = register_io_dev_block(&mmc_dev_con); + assert(result == 0); + + result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_dev_spec, + &mmc_dev_handle); + assert(result == 0); + +#else + result = register_io_dev_memmap(&memmap_dev_con); + assert(result == 0); + + result = io_dev_open(memmap_dev_con, (uintptr_t)NULL, + &memmap_dev_handle); + assert(result == 0); + +#endif + result = register_io_dev_fip(&fip_dev_con); + assert(result == 0); + + result = io_dev_open(fip_dev_con, (uintptr_t)NULL, + &fip_dev_handle); + assert(result == 0); +} diff --git a/plat/imx/imx7/common/imx7_rotpk.S b/plat/imx/imx7/common/imx7_rotpk.S new file mode 100644 index 0000000..8bd53c2 --- /dev/null +++ b/plat/imx/imx7/common/imx7_rotpk.S @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + .global imx7_rotpk_hash + .global imx7_rotpk_hash_end +imx7_rotpk_hash: + /* DER header */ + .byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48 + .byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 + /* SHA256 */ + .incbin ROTPK_HASH +imx7_rotpk_hash_end: diff --git a/plat/imx/imx7/common/imx7_trusted_boot.c b/plat/imx/imx7/common/imx7_trusted_boot.c new file mode 100644 index 0000000..cd27128 --- /dev/null +++ b/plat/imx/imx7/common/imx7_trusted_boot.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +extern char imx7_rotpk_hash[], imx7_rotpk_hash_end[]; + +int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + unsigned int *flags) +{ + *key_ptr = imx7_rotpk_hash; + *key_len = imx7_rotpk_hash_end - imx7_rotpk_hash; + *flags = ROTPK_IS_HASH; + + return 0; +} + +int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) +{ + *nv_ctr = 0; + + return 0; +} + +int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) +{ + return 1; +} + +int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) +{ + return get_mbedtls_heap_helper(heap_addr, heap_size); +} diff --git a/plat/imx/imx7/include/imx7_def.h b/plat/imx/imx7/include/imx7_def.h new file mode 100644 index 0000000..77a8ca3 --- /dev/null +++ b/plat/imx/imx7/include/imx7_def.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IMX7_DEF_H +#define IMX7_DEF_H + +#include + + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ +void plat_imx7_io_setup(void); +void imx7_platform_setup(u_register_t arg1, u_register_t arg2, + u_register_t arg3, u_register_t arg4); + +#endif /*IMX7_DEF_H */ diff --git a/plat/imx/imx7/warp7/aarch32/warp7_helpers.S b/plat/imx/imx7/warp7/aarch32/warp7_helpers.S deleted file mode 100644 index 3695b32..0000000 --- a/plat/imx/imx7/warp7/aarch32/warp7_helpers.S +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include - - .globl platform_mem_init - .globl plat_get_my_entrypoint - .globl plat_crash_console_init - .globl plat_crash_console_putc - .globl plat_crash_console_flush - .globl plat_panic_handler - - /* --------------------------------------------- - * int plat_mem_init(void) - * Function to initialize memory. - * The HAB hands off the DDR controller already - * setup and ready to use. - * Implement the mandatory function as a NOP - * --------------------------------------------- - */ -func platform_mem_init - bx lr -endfunc platform_mem_init - -func plat_get_my_entrypoint - mov r0, #0 - bx lr -endfunc plat_get_my_entrypoint - -func plat_crash_console_init - mov_imm r0, PLAT_WARP7_BOOT_UART_BASE - mov_imm r1, PLAT_WARP7_BOOT_UART_CLK_IN_HZ - mov_imm r2, PLAT_WARP7_CONSOLE_BAUDRATE - b imx_crash_uart_init -endfunc plat_crash_console_init - -func plat_crash_console_putc - mov_imm r1, PLAT_WARP7_BOOT_UART_BASE - b imx_crash_uart_putc -endfunc plat_crash_console_putc - -func plat_crash_console_flush - /* Placeholder */ - mov r0, #0 - bx lr -endfunc plat_crash_console_flush - -func plat_panic_handler - mov r3, #HAB_ROM_VECTOR_TABLE_FAILSAFE - ldr r3, [r3, #0] - blx r3 -endfunc plat_panic_handler diff --git a/plat/imx/imx7/warp7/include/platform_def.h b/plat/imx/imx7/warp7/include/platform_def.h index d58382f..4f71908 100644 --- a/plat/imx/imx7/warp7/include/platform_def.h +++ b/plat/imx/imx7/warp7/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -74,13 +74,13 @@ #define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE) /* Place OPTEE at minus 32 MB from the end of memory. 0x9e000000 - 0xa0000000 */ -#define WARP7_OPTEE_SIZE 0x02000000 -#define WARP7_OPTEE_BASE (DRAM_LIMIT - WARP7_OPTEE_SIZE) -#define WARP7_OPTEE_LIMIT (WARP7_OPTEE_BASE + WARP7_OPTEE_SIZE) +#define IMX7_OPTEE_SIZE 0x02000000 +#define IMX7_OPTEE_BASE (DRAM_LIMIT - IMX7_OPTEE_SIZE) +#define IMX7_OPTEE_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE) /* Place ATF directly beneath OPTEE. 0x9df00000 - 0x9e000000 */ #define BL2_RAM_SIZE 0x00100000 -#define BL2_RAM_BASE (WARP7_OPTEE_BASE - BL2_RAM_SIZE) +#define BL2_RAM_BASE (IMX7_OPTEE_BASE - BL2_RAM_SIZE) #define BL2_RAM_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE) /* Optional Mailbox. Only relevant on i.MX7D. 0x9deff000 - 0x9df00000*/ @@ -89,28 +89,28 @@ #define SHARED_RAM_LIMIT (SHARED_RAM_BASE + SHARED_RAM_SIZE) /* Define the absolute location of u-boot 0x87800000 - 0x87900000 */ -#define WARP7_UBOOT_SIZE 0x00100000 -#define WARP7_UBOOT_BASE (DRAM_BASE + 0x7800000) -#define WARP7_UBOOT_LIMIT (WARP7_UBOOT_BASE + WARP7_UBOOT_SIZE) +#define IMX7_UBOOT_SIZE 0x00100000 +#define IMX7_UBOOT_BASE (DRAM_BASE + 0x7800000) +#define IMX7_UBOOT_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE) /* Define FIP image absolute location 0x80000000 - 0x80100000 */ -#define WARP7_FIP_SIZE 0x00100000 -#define WARP7_FIP_BASE (DRAM_BASE) -#define WARP7_FIP_LIMIT (WARP7_FIP_BASE + WARP7_FIP_SIZE) +#define IMX7_FIP_SIZE 0x00100000 +#define IMX7_FIP_BASE (DRAM_BASE) +#define IMX7_FIP_LIMIT (IMX7_FIP_BASE + IMX7_FIP_SIZE) /* Define FIP image location at 1MB offset */ -#define WARP7_FIP_MMC_BASE (1024 * 1024) +#define IMX7_FIP_MMC_BASE (1024 * 1024) /* Define the absolute location of DTB 0x83000000 - 0x83100000 */ -#define WARP7_DTB_SIZE 0x00100000 -#define WARP7_DTB_BASE (DRAM_BASE + 0x03000000) -#define WARP7_DTB_LIMIT (WARP7_DTB_BASE + WARP7_DTB_SIZE) +#define IMX7_DTB_SIZE 0x00100000 +#define IMX7_DTB_BASE (DRAM_BASE + 0x03000000) +#define IMX7_DTB_LIMIT (IMX7_DTB_BASE + IMX7_DTB_SIZE) /* Define the absolute location of DTB Overlay 0x83100000 - 0x83101000 */ -#define WARP7_DTB_OVERLAY_SIZE 0x00001000 -#define WARP7_DTB_OVERLAY_BASE WARP7_DTB_LIMIT -#define WARP7_DTB_OVERLAY_LIMIT (WARP7_DTB_OVERLAY_BASE + \ - WARP7_DTB_OVERLAY_SIZE) +#define IMX7_DTB_OVERLAY_SIZE 0x00001000 +#define IMX7_DTB_OVERLAY_BASE IMX7_DTB_LIMIT +#define IMX7_DTB_OVERLAY_LIMIT (IMX7_DTB_OVERLAY_BASE + \ + IMX7_DTB_OVERLAY_SIZE) /* * BL2 specific defines. @@ -124,14 +124,14 @@ /* * BL3-2/OPTEE */ -# define BL32_BASE WARP7_OPTEE_BASE -# define BL32_LIMIT (WARP7_OPTEE_BASE + WARP7_OPTEE_SIZE) +# define BL32_BASE IMX7_OPTEE_BASE +# define BL32_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE) /* * BL3-3/U-BOOT */ -#define BL33_BASE WARP7_UBOOT_BASE -#define BL33_LIMIT (WARP7_UBOOT_BASE + WARP7_UBOOT_SIZE) +#define BL33_BASE IMX7_UBOOT_BASE +#define BL33_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE) /* * ATF's view of memory @@ -189,9 +189,9 @@ #error "define PLAT_WARP7_UART=1 or PLAT_WARP7_UART=6" #endif -#define PLAT_WARP7_BOOT_UART_BASE PLAT_WARP7_UART_BASE -#define PLAT_WARP7_BOOT_UART_CLK_IN_HZ 24000000 -#define PLAT_WARP7_CONSOLE_BAUDRATE 115200 +#define PLAT_IMX7_BOOT_UART_BASE PLAT_WARP7_UART_BASE +#define PLAT_IMX7_BOOT_UART_CLK_IN_HZ 24000000 +#define PLAT_IMX7_CONSOLE_BAUDRATE 115200 /* MMC defines */ #ifndef PLAT_WARP7_SD @@ -211,13 +211,6 @@ #endif /* PLAT_WARP7_SD == 3 */ /* - * GIC related constants - */ -#define GICD_BASE 0x31001000 -#define GICC_BASE 0x31002000 -#define GICR_BASE 0 - -/* * System counter */ #define SYS_COUNTER_FREQ_IN_TICKS 8000000 /* 8 MHz */ diff --git a/plat/imx/imx7/warp7/platform.mk b/plat/imx/imx7/warp7/platform.mk index a93f5e0..ea0f001 100644 --- a/plat/imx/imx7/warp7/platform.mk +++ b/plat/imx/imx7/warp7/platform.mk @@ -4,106 +4,21 @@ # SPDX-License-Identifier: BSD-3-Clause # -# Architecture -$(eval $(call add_define,ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING)) - -# Tune compiler for Cortex-A7 -ifeq ($(notdir $(CC)),armclang) - TF_CFLAGS += -mfpu=neon - ASFLAGS += -mfpu=neon -else ifneq ($(findstring clang,$(notdir $(CC))),) - TF_CFLAGS += -mfpu=neon - ASFLAGS += -mfpu=neon -else - TF_CFLAGS += -mfpu=neon - ASFLAGS += -mfpu=neon -endif +# Include imx7 common +include plat/imx/imx7/common/imx7.mk # Platform -PLAT_INCLUDES := -Idrivers/imx/uart \ - -Iplat/imx/common/include/ \ - -Iplat/imx/imx7/warp7/include \ - -Idrivers/imx/timer \ - -Idrivers/imx/usdhc \ - -Iplat/imx/imx7/include +PLAT_INCLUDES += -Iplat/imx/imx7/warp7/include -# Translation tables library -include lib/xlat_tables_v2/xlat_tables.mk - -BL2_SOURCES += common/desc_image_load.c \ - drivers/delay_timer/delay_timer.c \ - drivers/mmc/mmc.c \ - drivers/io/io_block.c \ - drivers/io/io_fip.c \ - drivers/io/io_memmap.c \ - drivers/io/io_storage.c \ - drivers/imx/timer/imx_gpt.c \ - drivers/imx/uart/imx_uart.c \ - drivers/imx/uart/imx_crash_uart.S \ - drivers/imx/usdhc/imx_usdhc.c \ - lib/aarch32/arm32_aeabi_divmod.c \ - lib/aarch32/arm32_aeabi_divmod_a32.S \ - lib/cpus/aarch32/cortex_a7.S \ - lib/optee/optee_utils.c \ - plat/imx/common/imx_aips.c \ - plat/imx/common/imx_caam.c \ - plat/imx/common/imx_clock.c \ - plat/imx/common/imx_csu.c \ - plat/imx/common/imx_io_mux.c \ - plat/imx/common/imx_snvs.c \ - plat/imx/common/imx_wdog.c \ - plat/imx/common/imx7_clock.c \ - plat/imx/imx7/warp7/aarch32/warp7_helpers.S \ - plat/imx/imx7/warp7/warp7_bl2_el3_setup.c \ - plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c \ - plat/imx/imx7/warp7/warp7_io_storage.c \ - plat/imx/imx7/warp7/warp7_image_load.c \ - plat/imx/common/aarch32/imx_uart_console.S \ - ${XLAT_TABLES_LIB_SRCS} - -ifneq (${TRUSTED_BOARD_BOOT},0) - -include drivers/auth/mbedtls/mbedtls_crypto.mk -include drivers/auth/mbedtls/mbedtls_x509.mk - -AUTH_SOURCES := drivers/auth/auth_mod.c \ - drivers/auth/crypto_mod.c \ - drivers/auth/img_parser_mod.c \ - drivers/auth/tbbr/tbbr_cot.c - -BL2_SOURCES += ${AUTH_SOURCES} \ - plat/common/tbbr/plat_tbbr.c \ - plat/imx/imx7/warp7/warp7_trusted_boot.c \ - plat/imx/imx7/warp7/warp7_rotpk.S - -ROT_KEY = $(BUILD_PLAT)/rot_key.pem -ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin - -$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"')) -$(eval $(call MAKE_LIB_DIRS)) - -$(BUILD_PLAT)/bl2/warp7_rotpk.o: $(ROTPK_HASH) - -certificates: $(ROT_KEY) - -$(ROT_KEY): | $(BUILD_PLAT) - @echo " OPENSSL $@" - @if [ ! -f $(ROT_KEY) ]; then \ - openssl genrsa 2048 > $@ 2>/dev/null; \ - fi - -$(ROTPK_HASH): $(ROT_KEY) - @echo " OPENSSL $@" - $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ - openssl dgst -sha256 -binary > $@ 2>/dev/null -endif +BL2_SOURCES += drivers/imx/usdhc/imx_usdhc.c \ + plat/imx/imx7/warp7/warp7_bl2_el3_setup.c # Build config flags # ------------------ +ARM_CORTEX_A7 := yes WORKAROUND_CVE_2017_5715 := 0 -# Enable reset to BL31 by default RESET_TO_BL31 := 0 # Non-TF Boot ROM @@ -118,28 +33,5 @@ # Use Coherent memory USE_COHERENT_MEM := 1 -# PLAT_WARP7_UART PLAT_WARP7_UART :=1 $(eval $(call add_define,PLAT_WARP7_UART)) - -# Add the build options to pack BLx images and kernel device tree -# in the FIP if the platform requires. -ifneq ($(BL2),) -$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert)) -endif -ifneq ($(BL32_EXTRA1),) -$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1)) -endif -ifneq ($(BL32_EXTRA2),) -$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2)) -endif -ifneq ($(HW_CONFIG),) -$(eval $(call TOOL_ADD_IMG,HW_CONFIG,--hw-config)) -endif - -# Verify build config -# ------------------- - -ifeq (${ARCH},aarch64) - $(error Error: AArch64 not supported on i.mx7) -endif diff --git a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c index 0eedd21..935a411 100644 --- a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c +++ b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,30 +8,17 @@ #include -#include -#include #include -#include #include #include -#include -#include -#include -#include #include -#include #include #include -#include -#include #include #include -#include #include -#include - -#include "warp7_private.h" +#include #define UART1_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ CCM_TRGT_MUX_UART1_CLK_ROOT_OSC_24M) @@ -43,102 +30,9 @@ CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\ CCM_TARGET_POST_PODF(2)) -#define WDOG_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ - CCM_TRGT_MUX_WDOG_CLK_ROOT_OSC_24M) - #define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL) -uintptr_t plat_get_ns_image_entrypoint(void) -{ - return WARP7_UBOOT_BASE; -} - -static uint32_t warp7_get_spsr_for_bl32_entry(void) -{ - return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, - DISABLE_ALL_EXCEPTIONS); -} - -static uint32_t warp7_get_spsr_for_bl33_entry(void) -{ - return SPSR_MODE32(MODE32_svc, - plat_get_ns_image_entrypoint() & 0x1, - SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); -} - -#ifndef AARCH32_SP_OPTEE -#error "Must build with OPTEE support included" -#endif - -int bl2_plat_handle_post_image_load(unsigned int image_id) -{ - int err = 0; - bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); - bl_mem_params_node_t *hw_cfg_mem_params = NULL; - - bl_mem_params_node_t *pager_mem_params = NULL; - bl_mem_params_node_t *paged_mem_params = NULL; - - assert(bl_mem_params); - - switch (image_id) { - case BL32_IMAGE_ID: - pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); - assert(pager_mem_params); - - paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); - assert(paged_mem_params); - - err = parse_optee_header(&bl_mem_params->ep_info, - &pager_mem_params->image_info, - &paged_mem_params->image_info); - if (err != 0) - WARN("OPTEE header parse error.\n"); - - /* - * When ATF loads the DTB the address of the DTB is passed in - * arg2, if an hw config image is present use the base address - * as DTB address an pass it as arg2 - */ - hw_cfg_mem_params = get_bl_mem_params_node(HW_CONFIG_ID); - - bl_mem_params->ep_info.args.arg0 = - bl_mem_params->ep_info.args.arg1; - bl_mem_params->ep_info.args.arg1 = 0; - if (hw_cfg_mem_params) - bl_mem_params->ep_info.args.arg2 = - hw_cfg_mem_params->image_info.image_base; - else - bl_mem_params->ep_info.args.arg2 = 0; - bl_mem_params->ep_info.args.arg3 = 0; - bl_mem_params->ep_info.spsr = warp7_get_spsr_for_bl32_entry(); - break; - - case BL33_IMAGE_ID: - /* AArch32 only core: OP-TEE expects NSec EP in register LR */ - pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); - assert(pager_mem_params); - pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; - - /* BL33 expects to receive the primary CPU MPID (through r0) */ - bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); - bl_mem_params->ep_info.spsr = warp7_get_spsr_for_bl33_entry(); - break; - - default: - /* Do nothing in default case */ - break; - } - - return err; -} - -void bl2_el3_plat_arch_setup(void) -{ - /* Setup the MMU here */ -} - #define WARP7_UART1_TX_MUX \ IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT0_UART1_TX_DATA @@ -215,29 +109,6 @@ imx_usdhc_init(¶ms, &info); } -static void warp7_setup_system_counter(void) -{ - unsigned long freq = SYS_COUNTER_FREQ_IN_TICKS; - - /* Set the frequency table index to our target frequency */ - write_cntfrq(freq); - - /* Enable system counter @ frequency table index 0, halt on debug */ - mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, - CNTCR_FCREQ(0) | CNTCR_HDBG | CNTCR_EN); -} - -static void warp7_setup_wdog_clocks(void) -{ - uint32_t wdog_en_bits = (uint32_t)WDOG_CLK_SELECT; - - imx_clock_set_wdog_clk_root_bits(wdog_en_bits); - imx_clock_enable_wdog(0); - imx_clock_enable_wdog(1); - imx_clock_enable_wdog(2); - imx_clock_enable_wdog(3); -} - static void warp7_setup_usb_clocks(void) { uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT; @@ -248,67 +119,24 @@ imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY); imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY); } -/* - * bl2_el3_early_platform_setup() - * MMU off - */ -void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, - u_register_t arg3, u_register_t arg4) + +void imx7_platform_setup(u_register_t arg1, u_register_t arg2, + u_register_t arg3, u_register_t arg4) { uint32_t uart1_en_bits = (uint32_t)UART1_CLK_SELECT; uint32_t uart6_en_bits = (uint32_t)UART6_CLK_SELECT; uint32_t usdhc_clock_sel = PLAT_WARP7_SD - 1; - static console_imx_uart_t console; - int console_scope = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME; - /* Initialize the AIPS */ - imx_aips_init(); - imx_csu_init(); - imx_snvs_init(); - imx_gpt_ops_init(GPT1_BASE_ADDR); - - /* Initialize clocks, regulators, pin-muxes etc */ - imx_clock_init(); + /* Initialize clocks etc */ imx_clock_enable_uart(0, uart1_en_bits); imx_clock_enable_uart(5, uart6_en_bits); + imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT); - warp7_setup_system_counter(); - warp7_setup_wdog_clocks(); + warp7_setup_usb_clocks(); /* Setup pin-muxes */ warp7_setup_pinmux(); - /* Init UART, storage and friends */ - console_imx_uart_register(PLAT_WARP7_BOOT_UART_BASE, - PLAT_WARP7_BOOT_UART_CLK_IN_HZ, - PLAT_WARP7_CONSOLE_BAUDRATE, - &console); - console_set_scope(&console.console, console_scope); - warp7_usdhc_setup(); - - /* Open handles to persistent storage */ - plat_warp7_io_setup(); - - /* Setup higher-level functionality CAAM, RTC etc */ - imx_caam_init(); - imx_wdog_init(); - - /* Print out the expected memory map */ - VERBOSE("\tOPTEE 0x%08x-0x%08x\n", WARP7_OPTEE_BASE, WARP7_OPTEE_LIMIT); - VERBOSE("\tATF/BL2 0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT); - VERBOSE("\tSHRAM 0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT); - VERBOSE("\tFIP 0x%08x-0x%08x\n", WARP7_FIP_BASE, WARP7_FIP_LIMIT); - VERBOSE("\tDTB-OVERLAY 0x%08x-0x%08x\n", WARP7_DTB_OVERLAY_BASE, WARP7_DTB_OVERLAY_LIMIT); - VERBOSE("\tDTB 0x%08x-0x%08x\n", WARP7_DTB_BASE, WARP7_DTB_LIMIT); - VERBOSE("\tUBOOT/BL33 0x%08x-0x%08x\n", WARP7_UBOOT_BASE, WARP7_UBOOT_LIMIT); -} - -/* - * bl2_platform_setup() - * MMU on - enabled by bl2_el3_plat_arch_setup() - */ -void bl2_platform_setup(void) -{ } diff --git a/plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c b/plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c deleted file mode 100644 index c670d42..0000000 --- a/plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include -#include - -static bl_mem_params_node_t bl2_mem_params_descs[] = { - { - .image_id = BL32_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, - entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = BL32_BASE, - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, - image_info_t, 0), - - .image_info.image_base = WARP7_OPTEE_BASE, - .image_info.image_max_size = WARP7_OPTEE_SIZE, - - .next_handoff_image_id = BL33_IMAGE_ID, - }, - { - .image_id = BL32_EXTRA1_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, - entry_point_info_t, - SECURE | NON_EXECUTABLE), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, - image_info_t, IMAGE_ATTRIB_SKIP_LOADING), - .image_info.image_base = WARP7_OPTEE_BASE, - .image_info.image_max_size = WARP7_OPTEE_SIZE, - - .next_handoff_image_id = INVALID_IMAGE_ID, - }, - { - /* This is a zero sized image so we don't set base or size */ - .image_id = BL32_EXTRA2_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | NON_EXECUTABLE), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_SKIP_LOADING), - .next_handoff_image_id = INVALID_IMAGE_ID, - }, - { - .image_id = BL33_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, - entry_point_info_t, - NON_SECURE | EXECUTABLE), - # ifdef PRELOADED_BL33_BASE - .ep_info.pc = PRELOADED_BL33_BASE, - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_SKIP_LOADING), - # else - .ep_info.pc = BL33_BASE, - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = WARP7_UBOOT_BASE, - .image_info.image_max_size = WARP7_UBOOT_SIZE, - # endif /* PRELOADED_BL33_BASE */ - - .next_handoff_image_id = INVALID_IMAGE_ID, - } -}; - -REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs); diff --git a/plat/imx/imx7/warp7/warp7_image_load.c b/plat/imx/imx7/warp7/warp7_image_load.c deleted file mode 100644 index c3e47b9..0000000 --- a/plat/imx/imx7/warp7/warp7_image_load.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -void plat_flush_next_bl_params(void) -{ - flush_bl_params_desc(); -} - -bl_load_info_t *plat_get_bl_image_load_info(void) -{ - return get_bl_load_info_from_mem_params_desc(); -} - -bl_params_t *plat_get_next_bl_params(void) -{ - return get_next_bl_params_from_mem_params_desc(); -} diff --git a/plat/imx/imx7/warp7/warp7_io_storage.c b/plat/imx/imx7/warp7/warp7_io_storage.c deleted file mode 100644 index fcfb503..0000000 --- a/plat/imx/imx7/warp7/warp7_io_storage.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include -#include -#include -#include -#include -#include -#include - -static const io_dev_connector_t *fip_dev_con; -static uintptr_t fip_dev_handle; - -#ifndef WARP7_FIP_MMAP -static const io_dev_connector_t *mmc_dev_con; -static uintptr_t mmc_dev_handle; - -static const io_block_spec_t mmc_fip_spec = { - .offset = WARP7_FIP_MMC_BASE, - .length = WARP7_FIP_SIZE -}; - -static const io_block_dev_spec_t mmc_dev_spec = { - /* It's used as temp buffer in block driver. */ - .buffer = { - .offset = WARP7_FIP_BASE, - /* do we need a new value? */ - .length = WARP7_FIP_SIZE - }, - .ops = { - .read = mmc_read_blocks, - .write = mmc_write_blocks, - }, - .block_size = MMC_BLOCK_SIZE, -}; - -static int open_mmc(const uintptr_t spec); - -#else -static const io_dev_connector_t *memmap_dev_con; -static uintptr_t memmap_dev_handle; - -static const io_block_spec_t fip_block_spec = { - .offset = WARP7_FIP_BASE, - .length = WARP7_FIP_SIZE -}; -static int open_memmap(const uintptr_t spec); -#endif -static int open_fip(const uintptr_t spec); - -static const io_uuid_spec_t bl32_uuid_spec = { - .uuid = UUID_SECURE_PAYLOAD_BL32, -}; - -static const io_uuid_spec_t bl32_extra1_uuid_spec = { - .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1, -}; - -static const io_uuid_spec_t bl32_extra2_uuid_spec = { - .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2, -}; - -static const io_uuid_spec_t bl33_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, -}; - -#if TRUSTED_BOARD_BOOT -static const io_uuid_spec_t tb_fw_cert_uuid_spec = { - .uuid = UUID_TRUSTED_BOOT_FW_CERT, -}; - -static const io_uuid_spec_t trusted_key_cert_uuid_spec = { - .uuid = UUID_TRUSTED_KEY_CERT, -}; - -static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = { - .uuid = UUID_TRUSTED_OS_FW_KEY_CERT, -}; - -static const io_uuid_spec_t tos_fw_cert_uuid_spec = { - .uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT, -}; - -static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FW_KEY_CERT, -}; - -static const io_uuid_spec_t nt_fw_cert_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT, -}; -#endif /* TRUSTED_BOARD_BOOT */ - -/* TODO: this structure is replicated multiple times. rationalize it ! */ -struct plat_io_policy { - uintptr_t *dev_handle; - uintptr_t image_spec; - int (*check)(const uintptr_t spec); -}; - -static const struct plat_io_policy policies[] = { -#ifndef WARP7_FIP_MMAP - [FIP_IMAGE_ID] = { - &mmc_dev_handle, - (uintptr_t)&mmc_fip_spec, - open_mmc - }, -#else - [FIP_IMAGE_ID] = { - &memmap_dev_handle, - (uintptr_t)&fip_block_spec, - open_memmap - }, -#endif - [BL32_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl32_uuid_spec, - open_fip - }, - [BL32_EXTRA1_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl32_extra1_uuid_spec, - open_fip - }, - [BL32_EXTRA2_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl32_extra2_uuid_spec, - open_fip - }, - [BL33_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl33_uuid_spec, - open_fip - }, -#if TRUSTED_BOARD_BOOT - [TRUSTED_BOOT_FW_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&tb_fw_cert_uuid_spec, - open_fip - }, - [TRUSTED_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&trusted_key_cert_uuid_spec, - open_fip - }, - [TRUSTED_OS_FW_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&tos_fw_key_cert_uuid_spec, - open_fip - }, - [NON_TRUSTED_FW_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&nt_fw_key_cert_uuid_spec, - open_fip - }, - [TRUSTED_OS_FW_CONTENT_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&tos_fw_cert_uuid_spec, - open_fip - }, - [NON_TRUSTED_FW_CONTENT_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&nt_fw_cert_uuid_spec, - open_fip - }, -#endif /* TRUSTED_BOARD_BOOT */ -}; - -static int open_fip(const uintptr_t spec) -{ - int result; - uintptr_t local_image_handle; - - /* See if a Firmware Image Package is available */ - result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); - if (result == 0) { - result = io_open(fip_dev_handle, spec, &local_image_handle); - if (result == 0) { - VERBOSE("Using FIP\n"); - io_close(local_image_handle); - } - } - return result; -} - -#ifndef WARP7_FIP_MMAP -static int open_mmc(const uintptr_t spec) -{ - int result; - uintptr_t local_handle; - - result = io_dev_init(mmc_dev_handle, (uintptr_t)NULL); - if (result == 0) { - result = io_open(mmc_dev_handle, spec, &local_handle); - if (result == 0) - io_close(local_handle); - } - return result; -} -#else -static int open_memmap(const uintptr_t spec) -{ - int result; - uintptr_t local_image_handle; - - result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL); - if (result == 0) { - result = io_open(memmap_dev_handle, spec, &local_image_handle); - if (result == 0) { - VERBOSE("Using Memmap\n"); - io_close(local_image_handle); - } - } - return result; -} -#endif - -int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, - uintptr_t *image_spec) -{ - int result; - const struct plat_io_policy *policy; - - assert(image_id < ARRAY_SIZE(policies)); - - policy = &policies[image_id]; - result = policy->check(policy->image_spec); - assert(result == 0); - - *image_spec = policy->image_spec; - *dev_handle = *policy->dev_handle; - - return result; -} - -void plat_warp7_io_setup(void) -{ - int result __unused; - -#ifndef WARP7_FIP_MMAP - result = register_io_dev_block(&mmc_dev_con); - assert(result == 0); - - result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_dev_spec, - &mmc_dev_handle); - assert(result == 0); - -#else - result = register_io_dev_memmap(&memmap_dev_con); - assert(result == 0); - - result = io_dev_open(memmap_dev_con, (uintptr_t)NULL, - &memmap_dev_handle); - assert(result == 0); - -#endif - result = register_io_dev_fip(&fip_dev_con); - assert(result == 0); - - result = io_dev_open(fip_dev_con, (uintptr_t)NULL, - &fip_dev_handle); - assert(result == 0); -} diff --git a/plat/imx/imx7/warp7/warp7_private.h b/plat/imx/imx7/warp7/warp7_private.h deleted file mode 100644 index cb6d900..0000000 --- a/plat/imx/imx7/warp7/warp7_private.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef WARP7_PRIVATE_H -#define WARP7_PRIVATE_H - -/******************************************************************************* - * Function and variable prototypes - ******************************************************************************/ -void plat_warp7_io_setup(void); - -#endif /* WARP7_PRIVATE_H */ diff --git a/plat/imx/imx7/warp7/warp7_rotpk.S b/plat/imx/imx7/warp7/warp7_rotpk.S deleted file mode 100644 index f74b6d25b..0000000 --- a/plat/imx/imx7/warp7/warp7_rotpk.S +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - - .global warp7_rotpk_hash - .global warp7_rotpk_hash_end -warp7_rotpk_hash: - /* DER header */ - .byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48 - .byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 - /* SHA256 */ - .incbin ROTPK_HASH -warp7_rotpk_hash_end: diff --git a/plat/imx/imx7/warp7/warp7_trusted_boot.c b/plat/imx/imx7/warp7/warp7_trusted_boot.c deleted file mode 100644 index 6a00224..0000000 --- a/plat/imx/imx7/warp7/warp7_trusted_boot.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -extern char warp7_rotpk_hash[], warp7_rotpk_hash_end[]; - -int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, - unsigned int *flags) -{ - *key_ptr = warp7_rotpk_hash; - *key_len = warp7_rotpk_hash_end - warp7_rotpk_hash; - *flags = ROTPK_IS_HASH; - - return 0; -} - -int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) -{ - *nv_ctr = 0; - - return 0; -} - -int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) -{ - return 1; -} - -int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) -{ - return get_mbedtls_heap_helper(heap_addr, heap_size); -}