diff --git a/plat/allwinner/sun50i_h6/sunxi_power.c b/plat/allwinner/sun50i_h6/sunxi_power.c
index f109cce..b6e07a2 100644
--- a/plat/allwinner/sun50i_h6/sunxi_power.c
+++ b/plat/allwinner/sun50i_h6/sunxi_power.c
@@ -28,13 +28,8 @@
 {
 	uint32_t reg;
 
-	/* get currently configured function for pins PL0 and PL1 */
-	reg = mmio_read_32(SUNXI_R_PIO_BASE + 0x00);
-	if ((reg & 0xff) == 0x33) {
-		NOTICE("PMIC: already configured for TWI\n");
-	}
-
 	/* switch pins PL0 and PL1 to I2C */
+	reg = mmio_read_32(SUNXI_R_PIO_BASE + 0x00);
 	mmio_write_32(SUNXI_R_PIO_BASE + 0x00, (reg & ~0xff) | 0x33);
 
 	/* level 2 drive strength */
@@ -47,13 +42,11 @@
 
 	/* assert & de-assert reset of R_I2C */
 	reg = mmio_read_32(SUNXI_R_PRCM_BASE + 0x19c);
-	mmio_write_32(SUNXI_R_PRCM_BASE + 0x19c, 0);
-	reg = mmio_read_32(SUNXI_R_PRCM_BASE + 0x19c);
-	mmio_write_32(SUNXI_R_PRCM_BASE + 0x19c, reg | 0x00010000);
+	mmio_write_32(SUNXI_R_PRCM_BASE + 0x19c, reg & ~BIT(16));
+	mmio_write_32(SUNXI_R_PRCM_BASE + 0x19c, reg | BIT(16));
 
 	/* un-gate R_I2C clock */
-	reg = mmio_read_32(SUNXI_R_PRCM_BASE + 0x19c);
-	mmio_write_32(SUNXI_R_PRCM_BASE + 0x19c, reg | 0x00000001);
+	mmio_write_32(SUNXI_R_PRCM_BASE + 0x19c, reg | BIT(16) | BIT(0));
 
 	/* call mi2cv driver */
 	i2c_init((void *)SUNXI_R_I2C_BASE);